EDA用VHDL語(yǔ)言設(shè)計(jì)一個(gè)2-4譯碼器

EDA用VHDL語(yǔ)言設(shè)計(jì)一個(gè)2-4譯碼器EDA用VHDL語(yǔ)言設(shè)計(jì)一個(gè)2-4譯碼器/NUMPAGES8EDA用VHDL語(yǔ)言設(shè)計(jì)一個(gè)2-4譯碼器EDA用VHDL語(yǔ)言設(shè)計(jì)一個(gè)2-4譯碼器2-4譯碼器LIBRARYIEEE;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdecoder2_4ISPORT(a:INSTD_LOGIC_VECTOR(1DOWNTO0);s:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDdecoder2_4;ARCHITECTUREBehavioralOFdecoder2_4_tISBEGINPROCESS(sel)BEGINCASEaISWHEN"00"=>s<=”0001WHEN"01"=>s<=”0010WHEN"10"=>s<=”0100WHEN"11"=>s<=”1000“;WHENOTHERS=>s<=’’0000ENDCASE;ENDPROCESS;ENDBrhavioral;4選1數(shù)據(jù)選擇器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsel4ISPROT(d:INSTD_LOGIC_VECTOR(3DOWNTO0);a:INSTD_LOGIC_VECTOR(1DOWNTO0);s:OUTSTD_LOGIC);ENDsel4:ARCHITECTUREBehavioralOFsel4ISBEGINROCESS(a,d)BEGINCASEaISWHEN"00"=>s<=d(0)WHEN"01"=>s<=d(1)WHEN"10"=>s<=d(2)WHEN"11"=>s<=d(3)“;WHENOTHERS=>s<=’Z’ENDCASE;ENDPROCESS;ENDBrhavioral;100進(jìn)制加法計(jì)數(shù)器LIBRARYIEEE;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcounterISPORT(clk,en,load,rst:INSTD_LOGICd;INSTD_LOGIC_VECTOR(6DOWNTO0);q:OUTSTD_LOGIC_VECTOR(6DOWNTO0):ENDcounter100;ARCHTECTUREBehavioralOFcounter100ISsignalqtemp:STD_LOGIC_VECTOR(6DOWNTO0);BEGINPROCESS(clk,d,en,load,rst)BEGINIFrst=’1’qtemp<=”00000000”ELSIFrising-edge(clk)THEN\IFen=’1’IFload=’1’ELSIFqtemp=”1100011”THENqtemp<=”00000000ELSIFqtemp<=qtemp+’1;ENDIF;ENDIF;ENDIF;ENDPROCESS;q<=qtemp;ENDBehavioral;8位從高至低串入串出移位寄存器LIBRARYIEEE;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYshift.registerISPORT(d,clk:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDdshift.register;ARCHITECTUREBehavioralOFshift.registerISsignalqtemp:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(d,clk)BEGINIFrising-edge(clk)THENq<=dtemp(0);dtemp<=d&dtemp(7DOWNTO1);ENDIF;ENDPROCESS;ENDBehavioral;狀態(tài)機(jī)LIBRARYIEEE;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfsmISPORT(tin,clk:INSTD_LOGIC;yout:OUTSTD_LOGIC_VECTOR(1DOWNTO0));ENDfsm;ARCHITECTUREBehavioralOFfsmISTYPEstate-typeIS(S0,S1,S2)signalstate,next_state:state_type;BEGINSYNC_PROC:PROCESS(clk)BEGINIFrising_edge(clk)THENstate<=next_state;ENDIF;ENDPROCESS;OUTPUT_DECODE:PROCESS(state)BEGINCASEstateISWHENS0=>yout<=”00”WHENS1=>yout<=”01”WHENS2=>yout<=”10”WHENOTHERS=>yout<=”zz”;ENDLAST;ENDPROCESS;NEXT_STATE_DECODE:PROCESS(state,tin)BEGINnext_state<=state;CASEstateISWHENS0=>next_state<=S1;WHENS1=>next_state<=S2;