講稿ni官方培訓(xùn)lesson programming using labview fpga

Lesson

3Programming

Using

LabVIEW

FPGAIntroductionDeveloping

the

FPGA

VIInteractive

Front

PanelCommunicationD.

Selecting

anExecution

ModeD.

Compiling

the

FPGA

VID.

Basic

OptimizationsA.

IntroductionFPGA

Layout

and

ComponentsHow

an

FPGA

Works

Programmable

interconnect

switches

and

wiresroute

signals

between

various

hardwareresources

in

an

FPGA

Hardware

resources

include

logic

gates,

flip-flops,

and

block

memory

For

a

more

detailed

description

of

how

FPGAworks,

see

.How

FPGA

Works

-

ExampleImplements

a

VI

that

calculates

a

value

for

Ffrom

inputs

A,

B,

C,

and

D,

where

F

=

(A

+

B)

xC

x

DProgramming

FPGA

with

LabVIEWLabVIEW

FPGADo

not

have

to

learnVHDL

or

VerilogTrue

parallel

executionDeterministicTrue

Parallel

ExecutionF

=

(A+B)C

and

Z

=

X+Y+M

in

separate

gates

onan

FPGAFPGA

Communication

with

I/O

and

HostFPGA

provides:TimingTriggeringProcessingCustom

I/O

Each

fixed

I/O

uses

aportion

of

the

FPGAhardware

resources

The

bus

interface

to

thehost

computer

also

usesa

portion

of

the

FPGAhardware

resourcesTiming

Benefits

of

FPGA

Multi-loop

analog

PID

loop

rates

exceed

100

kHzon

embedded

RIO

FPGA

hardware

whereas

theyrun

at

30

kHz

in

real-time

without

FPGAhardware

Digital

control

loop

rates

can

execute

up

to

1MS/s

or

more

depending

on

the

target

Single-cycle

timed

loops

execute

up

to

200

MHzor

more

depending

on

the

target

and

clockconfiguration

Due

to

parallel

processing

ability,

addingadditional

computation

does

not

necessarilyreduce

the

speed

of

the

FPGA

applicationB.

Developing

the

FPGA

VIThere

is

no

operating

system

on

the

FPGA

Download

and

run

only

one

top-level

VI

at

atimeFPGA

can

run

independently

of

the

hostFPGA

can

store

data

in

memory

Edit

VI

under

an

FPGA

Target

to

use

the

FPGApalette

Usually

use

integer

or

fixed-point

math

toperform

calculationsAdd

a

VI

Under

the

FPGA

TargetFPGA

Palettes

VIs

under

the

FPGAtarget

inherit

the

FPGAFunction

Palette

Many

palettes

are

similarto

LabVIEW

for

WindowsFPGA-specific

palettesFPGA

I/OMemory

&

FIFOSynchronizationFPGA

Math

&

AnalysisIP

IntegrationFPGA

I/O

PaletteFPGA

Math

&

Analysis

Palette

Keep

calculations

assimple

as

possible

topreserve

FPGA

resources

Functions

perform

point-by-point

calculationsDemonstration

3-1Create

an

FPGA

VI

and

explore

the

Functionspalette

supported

under

FPGA.Top-Level

FPGA

VI

Front

PanelHardware

resourcesinside

an

FPGA

are

limited

Use

the

minimumnecessary

controls

andindicators

forprogrammatic

front

panelcommunication

to

a

host

Add

temporary

controlsand

indicators

fordebugging

if

necessary,but

remove

themafterwardsC.

Interactive

Front

PanelCommunicationFPGAhas

no

userinterfaceMustrelycommunicateexclusivelydata

from

FPGA

to

Host

PCon

I/OorFront

panel

displayed

on

Host

PCBlock

diagram

executes

on

FPGA

as

compiledCommunication

layer

shares

all

control

andindicator

valuesCannot

use

debugging

tools

when

running

FPGA

VITest

with

development

computer

first,

or

addindicators

as

probesInteractive

Front

Panel

CommunicationD.

Selecting

an

Execution

Mode

Right-click

the

FPGATarget

in

the

ProjectExplorer

window

andselect

Properties

tolaunch

FPGA

TargetProperties

dialog

boxOr

Right-click

the

FPGATarget

and

selectExecute

VI

on

to

selectmode

directlySelecting

an

Execution

Mode

–

Options

Execute

VI

on

FPGAtarget

Execute

VI

onDevelopment

Computerwith

Simulated

I/O

Use

Random

Data

forFPGA

I/O

Read

Use

Custom

VI

for

FPGAI/O

Execute

VI

onDevelopment

Computerwith

Real

I/O

Not

supported

by

allFPGA

targetsTesting

with

the

Development

Computer

Compiling

to

run

on

the

FPGA

can

require

a

fewminutes

to

several

hours

Verify

logic

before

compiling

by

executing

theVI

on

the

development

computer

(Windows

PC)Traditional

debugging

tools

are

availableSimulate

FPGA

VI

on

PC

totest(Execute

VI

on

DevComputer)Compile

FPGA

VI

to

run

onFPGA(Execute

VI

on

FPGA

Target)CreateFPGA

VISimulation

does

not

functioncorrectlyExercise

3-1:

VI

Execution

on

theDevelopment

ComputerCreate

an

FPGA

VI

and

verify

the

functionalityof

the

VI

using

the

development

computer.Exercise

3-1:

VI

Execution

on

theDevelopment

Computer

Note

how

quickly

you

were

able

to

progressfrom

development

to

testing.

Have

you

ever

tried

troubleshooting

a

VIwithout

using

the

debugging

tools?

After

verifying

logic

by

executing

the

VI

on

thedevelopment

computer,

you

are

ready

to

compile

theFPGA

VI

and

run

it

on

the

FPGA

targetE.

Compiling

the

FPGA

VISimulate

FPGA

VI

on

PC

totest(Execute

VI

on

DevComputer)Compile

FPGA

VI

to

run

onFPGA(Execute

VI

on

FPGA

Target)CreateFPGA

VISimulation

does

not

functioncorrectlyCompileServerGeneratesIntermediateFilesWhatHappensWhenYouCompileanFPGAVI?LabVIEWCompileWorkerSendsIntermediateFilesBinary

DataFPGA

VI

LabVIEW

convertsFPGA

VI

intointermediate

filesLabVIEWcreatesbitfile

containing

thebinary

datadescribing

how

toconfigure

FPGAcircuitFPGA

VI

hasreference

tocorresponding

bitfileBitfile

(.lvbitx)

Binary

Data

Receivescompilationrequests

fromLabVIEWSends

compilationjobs

to

availablecompile

workerSends

binary

datato

LabVIEW

Transformsintermediate

filesinto

binary

datathat

describes

howto

configure

theFPGA

circuit

of

theFPGA

targetUses

Xilinx

tools

tocompileConfigure

your

FPGA

target

to

Execute

VI

onFPGA

Target

and

click

Run

on

the

FPGA

VILabVIEW

automatically

compiles,

downloads,

andruns

an

FPGA

VI

on

the

FPGA

targetRunning

an

FPGA

VI

on

the

FPGATargetWorking

with

BuildSpecifications

You

must

create

a

buildspecification

before

you

cancompile

an

FPGA

VI.

If

you

do

not

create

one,LabVIEW

creates

andspecifies

a

defaultspecification

for

the

VI.

You

can

specify

a

defaultbuild

specification.

To

create

a

buildspecification,

right-click

abuild

specification

under

anFPGA

target

in

the

ProjectExplorer

window.Available

options

vary

byCommon

Build

Specification

ActionsBuild—This

command

compiles

the

VI.

Estimate

Resource

Usage—Estimates

FPGAresource

usages

without

compiling.

Generate

Intermediate

Files—Generatesintermediate

files

without

compiling

the

VI.Useful

for

catching

certain

code

generationerrors.

Display

Compilation

Results—Displays

theCompilation

Status

window.

You

must

build

thebuild

specification

once

to

display

theCompilation

Status

window.Stages

of

the

Compilation

ProcessGeneration

of

Intermediate

Files

(HDL

code)QueuingHDL

Compilation,

Analysis

and

SynthesisMappingPlacing

and

RoutingGenerating

BitstreamBitfile

CreationGenerate

Intermediate

Files

(HDL

CodeClick

Run

Generating

IntermediateFiles

window

launches

Converts

graphical

codeto

VHDL

Generates

intermediatefiles

Once

compilation

starts,do

not

edit

the

VI

Create

a

compilationqueue

by

startinganother

compilation

whilethe

first

is

still

runningExercise

3-2,

Part

A:

VI

Execution

on

the

FPGATargetBegin

Exercise

3-2

to

start

compilation

of

aworking

VI

to

run

on

an

FPGA

target.Do

only

Part

A.Compilation

Status

WindowReports

Select

the

reportthat

is

displayedClose

OptionClose

windowDisconnect

AllCancel

All

CompilationsHelpCompilation

Status

Window

–Configuration

ReportProject

informationXilinx

compiler

configuration

for

the

FPGA

VICompilationStatusWindow–

DeviceUtilizationReportSeparate

reports

generated

at

pre-synthesis

andsynthesis

stages

of

compilationCompilation

Status

Window

–

TimingReportSeparate

reports

generated

at

mapping

(estimated

values)and

placing

and

routing

(actual

values)

stages

ofcompilationCompilation

Status

Window

–

Xilinx

LoReportIncludes

XilinxLog.txt

and

.twr

filesAvailable

after

compilation

is

completeCan

be

saved

to

a

fileCompile

Worker

WindowView

informationabout

the

compileworker:Server

connectionstatusCurrent

compilationjobsWindows

TaskbarExercise

3-2,

Part

B:

VI

Execution

on

the

FPGATargetComplete

Exercise

3-2

to

view

reportsgenerated

after

compiling

a

working

VI

to

run

onan

FPGA

target.Exercise

3-2,

Part

B:

VI

Execution

on

the

FPGATarget

What

is

the

benefit

of

having

reports

generatedat

different

points

of

the

compilation?

What

if

you

had

not

tested

on

the

developmentcomputer

and

the

VI

did

not

function

as

intended?What

if

your

compilation

fails?FPGA

Compilation

ConsiderationsWhat

causes

a

pile?Compiling

an

FPGA

VI

remotelyCauses

of

compilation

failureXilinx

compiler

optionsWhat

Causes

a

pile?

When

you

run

a

FPGA

VI

that

LabVIEW

hasalready

compiled,

LabVIEW

does

not

need

topile

if

the

VI

does

not

have

any non-cosmeticchangesIf

the

FPGA

VI

has

any non-cosmetic

changes,pile

your

VI

on

the

nextthen

LabVIEW

willrun.Example:Change

algorithm

on

block

diagramAdd

or

delete

functions

on

block

diagramRenamed

control

or

indicatorAdded

control

or

indicator

To

free

resources

on

the

local

computer,install

the

LabVIEW

FPGA

Compile

Server

andCompile

Worker

on

a

remote

computer

andcompile

the

FPGA

VI

remotely

Refer

to

Compiling

an

FPGA

VI

Remotely

(FPGAModule)

in

the

LabVIEW

Help

for

moreinformation

about

compiling

FPGA

code

remotelyDevelopmentCLoambpVuItEeWrCompiling

an

FPGA

VI

RemotelyRCeompoitlee

CoSmepruvteerrCompileWorkerCauses

of

Compilation

FailureTiming

Delays

in

the

designed

circuit

exceed

theperiod

of

the

specified

clockResource

utilization

The

design

requires

more

FPGA

resources

thanare

available

on

the

FPGAXilinx

Compiler

Options

In

your

Build

Specification,

you

can

customizeXilinx

compiler

options

Use

mended

settings

is

the

default

andmended

Xilinx

compiler

option

In

general,

only

choose

a

specific

DesignStrategy

for

Xilinx

compiler

if

necessaryF.

Basic

OptimizationsThese

types

of

optimizations

are

relatively

easyto

implementRequire

no

major

changes

in

code

architectureShould

be

basic

programming

practice

for

allFPGA

VIsBasic

optimizations

in

this

section

primarilyaffect

FPGA

sizeTypes

of

Basic

OptimizationsLimit

front

panel

objects

on

top-level

VIUse

small

data

typesAvoid

large

functionsLimitFrontPanelObjectsonTop-LevelVIEachread

and

writefrom

the

host

to

theFPGAis

broken

downinto

32-bit

packets

to

Each

front

panel

object

on

the

top-level

VImust

have

logic

to

interact

with

the

host

VItransfer

across

the

bus

Arrays/Clusters

with

more

than

32

bits

requireextra

copy

on

the

FPGA

to

guarantee

all

thedata

is

read

or

written

coherentlyLimit

Front

Panel

ArraysAvoid

using

arrays

on

the

front

panelAll

arrays

must

be

of

fixed

size

Compile

fails

if

array

size

is

larger

thanavailable

FPGA

resources

Can

quickly

use

large

amounts

of

FPGAresourcesEach

bit

inthe

arrayuses

its

own

flip-floponthe

FPGAThis

is

amendedoptimizationBitpack

Boolean

Logic

Each

control

hasoverhead

in

addition

tothe

size

of

the

datatype.

Maintain

the

sameinformation

using

fewercontrols

Display

binary

data

asan

integer

Use

a

Boolean

array

orcluster

control/indicatorUse

Small

Data

TypesUse

Small

Data

Types

-

CoercionEliminate

coercion

dotsDetermine

necessary

input

formatInsert

conversion

function

Intentional

coercion

results

in

more

efficientimplementationAvoid

Large

FunctionsNot

all

functions

are

equalQuotientRemainderScale

by

Powerof

2Avoid

Large

Functions

–Quotient

&

RemainderThis

function

consumessignificant

space

onthe

FPGAQuotient

&

Remainderoften

used

toincrement

based

oniteration

numberConsider

replacing

withactual

incrementfunction

and

shiftregisterAvoid

Large

Functions

–Scale

By

Power

of

2

Uses

significant

FPGA

space

if

input

for

poweris

a

control

However,

if

you

wire

a

constant

to

the

input,the

function

consumes

no

space

on

the

FPGA

Use

negative

powers

to

replace

Quotient

&Remainder

function

whenever

possibleSummary—Quiz

You

developed

a

VI

and

set

the

project

toexecute

the

VI

on

the

FPGA

Target.

Youcompile

the

code

and

run

the

VI.Which

of

the

following

statements

is

true?

The

block

diagram

and

the

front

panel

bothexecute

on

the

FPGA

The

block

diagram

executes

on

the

FPGA

andthe

front

panel

executes

on

the

hostcomputer.

The

block

diagram

executes

on

the

hostcomputer

and

the

front

panel

executes

on

theFPGA.

The

block

diagram

and

front

panel

bothexecute

on

the

host

computerSummary—Quiz

Answer

You

developed

a

VI

and

set

the

project

toexecute

the

VI

on

the

FPGA

Target.

Youcompile

the

code

and

run

the

VI.Which

of

the

following

statements

is

true?

The

block

diagram

and

the

front

panel

bothexecute

on

the

FPGA

The

block

diagram

executes

on

the

FPGA

andthe

front