數(shù)字電路第八章

Chapter8sequentiallogicdesignpracticesemphasis：Counter:countercomposedofflip-flopsandMSIcounters,sequencegeneratorShiftregister:datashiftfunction,ringcounter,Johnsoncounter,sequencegeneratoranddetector10/10/202318.1documentationstandardsInlogicblock,inputisontheright,outputisontheleft.inputoutput………………PRCLR……Edge-triggered……CCLKPulse-triggered10/10/202328.2latchesandflip-flops1.SSIlatchesandflip-flops74×74—dualDf-fs74×109—dualJ-K’f-fs74×375—quadDlatch2.Switchdebouncingeliminatebouncingthatoccurswhenthemechanicalswitchisonandoff.3.Bus-holder避免三態(tài)輸出總線上長(zhǎng)期無(wú)信號(hào)而由噪聲、干擾等產(chǎn)生較大電流而損壞器件的問(wèn)題。10/10/20233SwitchdebouncingSomeswitch,buttonAusualswitchdebouncer當(dāng)機(jī)械觸點(diǎn)斷開(kāi)、閉合時(shí),電壓信號(hào)會(huì)抖動(dòng)。抖動(dòng)時(shí)間的長(zhǎng)短由按鍵的機(jī)械特性決定,一般為5ms～10ms。S_LR_LR_LS_LQ10/10/202343.MultibitregistersandlatchesCollectionoftwoormoreDf-fswithacommonclockinput.Cabbeusedtostoredatatemporarily.10/10/202358.4countersAnysequentialcircuitwhosestatediagramisasinglecycle.Transitionofsuccessivestateisunconditional.Modulus—thenumberofstatesinthecycleS1SjSmS3S2……Modulo-mcounter(mstates→n=flip-flops)clocknQ[0..n-1]10/10/20236GeneraltypesofelectroniccountersClassifyincountingsequenceupcounters,whichcountinascendingbinaryorderdowncounters,whichcountindescendingbinaryorderClassifyincountercircuitAsynchronous(ripple)counterSynchronouscounterRingcounterJohnsoncounter10/10/202371、ripplecounters4-bitcounter：Q0Q1Q2Q3Counteroutput（LSB）（MSB）CLKQ1Q0Q3Q2CLKCLKQQTCLKQQTCLKQQTCLKQQT111110/10/202384-bitcounter’sfunctionaltableQ3Q2Q1Q0Q3*Q2*Q1*Q0*0000000100010010001000110011010001000101010101100110011101111000Q3Q2Q1Q0Q3*Q2*Q1*Q0*1000100110011010101010111011110011001101110111101110111111110000000000010010001101000101011001111111111011011100101110101001100010/10/20239Issue1：howtomakeadowncounterbyTf-fs？Issue2：howtomaketheripplecounterbyusingDandJ-Kf-fs？(ashomework,4-bit)--------------------------------------------------------------------------Alsobeactedasadigitalfrequencydivider(divided-by-2n)divide-by-2CLKQ1Q0Q3Q2divide-by-4divide-by-8divide-by-1610/10/2023102、SynchronouscountersAllflip-flopschangetheirstatesatthesametriggeringtimeofacommonCLKsignal.Workingfeatures：

Tsignalpropagatesserially.transitionequations：

Q0*=T0·Q0’+T0’·Q0

Q1*=T1·Q1’+T1’·Q1

Q2*=T2·Q2’+T2’·Q2

Q3*=T3·Q3’+T3’·Q3T0T1T2T3(LSB)(MSB)synchronousserialcounter10/10/202311(LSB)(MSB)T0T1T2T3CNTENsignalcontrolsthef-fssimultaneously;thefastestbinarycountersstructure.Judgethiscircuit’scountingsequence(upordown)?synchronousparallelcounter10/10/202312binarysynchronouscounterdesignwithDflip-flopsExp1:designa3-bitbinarysynchronousdowncounter,counteroutputQ2(msb),Q1,Q0。thefunctionaltable：Q2Q1Q0Q2*Q1*Q0*00011100100001000101101010001110110011010111111010/10/202313excitationtableofthecounterQ2Q1Q0Q2*Q1*Q0*D2D1D0J2K2J1K1J0K00001111111d1d1d0010000000d0dd10100010010dd11d0110100100dd0d1100011011d11d1d101100100d00dd1110101101d0d11d111110110d0d0d1excitationequations：D2=Q2Q1+Q2Q0+Q2’Q1’Q0’D1=Q1Q0+Q1’Q0’D0=Q0’……10/10/202314designsynchronouscounterwithmodulelessthan2nmoduleofthecounterm<2n，thedispositionofunusedstate：minimalriskminimalcost，needtoverifytheunusedstatethatassuresthecircuitcanbereturnedtothenormalExp2：designamodulo-5counter，itcounttheclockticksfrom000to100，synthesisbyDflip-flopinminimalcost.10/10/2023153、MSIcountersandapplicationssynchronous4-bitbinarycounter74×163clearloadingENT=ENP=CLR_L=LD_L=1，countingRCO（ripplecarryoutput）:whenQDQCQBQA=1111，andENT=1，RCO=1。hold10/10/202316workinginfree-runningmode(modulo-16counter)MSBLSB74×163isfullysynchronous,itsoutputschangeonlyontherisingedgeofclock.Countingfrom0to1510/10/202317using74×163inm<16modecounterExp：modulo-11counter

method1：feedback-clearmode(反饋清零)—countthefirstmbinarynumberfrom0000.key：whencountingtothenumberm(m-1),thecounterreturnto0000.so,needafeedbackcircuitF，andwhenQDQCQBQA=1010,makeCLR_Lasserted.Q0Q1Q2Q3FCLR_L74×163QAQBQCQDCLR10/10/202318Q3Q2Q1Q0CLR_L0000100011001010011101001010110110101111100011001110100CLR_L=(Q3·Q1)’Q0Q1Q2Q3FCLR_L74×163QAQBQCQDCLR10/10/202319verifytheunusedstateUnusedstates1011~1111:

10110000110011011110111100010010011010101000………Itcanrunautomatically.CLR_L=(Q3·Q1)’10/10/202320using74×163inm<16modecounterMethod2：feedback-loadmode(反饋置數(shù))—countthelastmstatesorarbitrarymcontinualstatesbetween0000and1111.key：makeLD_Lassertedwhencountingtotheendingstate,andtheinitialstateisloaded.①iftheendingstateis1111，usetheRCOoutputtoreloadtheinitialstate.Initialstate=endingstate–countingmodulo+1=15-11+1=5Soallthecountingstateis0101~1111.10/10/202321referencecircuitoffeedback-load10/10/202322②iftheendingstateisn’t1111,needacombinationalfeedbackcircuittoreloadtheinitialstate.

initialstate=endingstate–modulo+1or,endingstate=initialstate+modulo-1like，knowingtheendingstateis13，sotheinitialstate=13-11+1=3or,knowingtheinitialstateis2，sotheendingstate=2+11-1=12circuitdesign：besimilartofeedback-clearmode，noteditsoutputneedtobeconnectedtothe

LD_Lof74×163.10/10/202323referencecircuitoffeedback-loadcountingfrom3to13(0011~1101)10/10/20232474×163cascadingapplicationifthecountingmodulo>16，multiple74×163couldbecascaded.key：countnestingn74×163→maximummodulo16n。connectinglowergradecounter’sRCOoutputtonexthighergradecounter’sENsignal.10/10/202325Modulo-256free-runcounter10/10/20232616<modulo<256countersExp，amodulo-125countermethods：feedback-clear—0~124；feedback-reload—131~255，orarbitrarytwonumberswhosedifferenceis124between0and255.10/10/202327Othercounters74×161，asynchronousclear4-bitbinarycounter.

asynchronousclear：ifCLR_L=0，QDQCQBQAoutput0000immediately.otherfunctionisasthesameas74×163.use74×161tomodulo-11infeedback-clearmode，countending=1011，CountingNQ3Q2Q1Q00000010001200103001140100501016011070111810009100110101011101110/10/202328Othercountersdecadescounter74×160（asynchronousclear）74×162(fullysynchronous)74×1694-btup/downcounter74x160/16274x16910/10/202329Fromcountertotimer555多諧振蕩器或與非門構(gòu)成的雙穩(wěn)電路74×162ncounterclockT=1sModulo-60BCD-7segmentdecoderdisplayer74LS48或74LS49共陰型LED10/10/2023304、decodingbinary-counterstates以計(jì)數(shù)器的計(jì)數(shù)輸出作為譯碼器的輸入，可在譯碼器的輸出端得到周期為8倍計(jì)數(shù)時(shí)鐘的1：8的脈沖。也稱為8路順序脈沖發(fā)生電路10/10/20233174×163iscombinedwith74×151toobtainasequence-generator.Exp：a“01100101”sequence-generator計(jì)數(shù)器+數(shù)據(jù)選擇器法構(gòu)成的序列發(fā)生器的工作特點(diǎn):只要計(jì)數(shù)器是有效的，在時(shí)鐘的觸發(fā)下，循環(huán)地輸出序列。10/10/202332supplement：buildingsequence-generatorwithDF-Fs設(shè)計(jì)方法：順序計(jì)數(shù)+組合電路例：試設(shè)計(jì)一個(gè)密碼產(chǎn)生器，能依次輸出011010。用順序計(jì)數(shù)器的每個(gè)計(jì)數(shù)值產(chǎn)生一個(gè)碼位。000

0001

1010

1011

0100

1101

0Q2Q1Q0Q2*Q1*Q0*SEQ000001000101010100111011100010010111010000110dddd111dddd10/10/202333circuitforsequence-generatorincountermodeU1A74LS74D1D21Q51Q61CLR11CLK31PR4U1B74LS74D1D21Q51Q61CLR11CLK31PR4U2A74LS74D1D21Q51Q61CLR11CLK31PR4U3A74LS00DU3B74LS00DU3C74LS00DU4A74LS10DU3D74LS00DU5A74LS00DU6A74LS32DD2D1D0Q2Q2'Q1Q1'Q0Q0'SEQ10/10/202334課堂練習(xí)（1）設(shè)計(jì)一個(gè)序列信號(hào)檢測(cè)器，當(dāng)電路的輸入端X收到連續(xù)的“1011”時(shí)，輸出F為1，并且狀態(tài)可以重疊。狀態(tài)賦值采用QmQm-1…，按gray碼序。（2）設(shè)計(jì)一個(gè)5進(jìn)制加/減計(jì)數(shù)器，當(dāng)控制信號(hào)C=0，計(jì)數(shù)器按加1計(jì)數(shù)，當(dāng)C=1，計(jì)數(shù)器按減1計(jì)數(shù)。用D觸發(fā)器綜合。10/10/2023358.5ShiftRegisterAnn-bitregisterwithaprovisionforshiftingitsstoreddatabyonebitpositionatezchtickoftheclock.Classifybystructure：serial-in,serial-outserial-in,parallel-outparallel-in,serial-outparallel-in,parallel-outShift-rightClassifybyshiftingdirection：Shift-left10/10/202336Ann-bitnumberDn-1Dn-2……D1D0isstoredinann-bitshiftregister.Shiftleft：shiftfromLSBtoMSBShiftright：shiftfromMSBtoLSBDnewDn-1Dn-2……D1D0D1……Dn-2Dn-1Qn-1Qn-2Q1Q0…D0D1……Dn-2DnewQn-1Qn-2Q1Q0shiftleftshiftright10/10/2023371、shift-registerstructure（1）、serial-in,serial-outAfternclockticks,aninputbitappearsattheserialoutput.itcanbeusedasapulse-postponedcircuit.inputoutputnclocktickt0tn10/10/202338（2）、serial-in,parallel-out并出serialinparalleloutserial-parallelconversion10/10/202339（3）、parallel-in,serial-outserialout數(shù)據(jù)并入U(xiǎn)1U2D2

Q1

load/shift=1，loaddata，Di=iDload/shift=0，datashift，Di=Qi-11Dn

D100110/10/202340（4）、parallel-in,parallel-out10/10/2023412、MSIshiftregister74×164,serial-in,parallel-outwithasynchronousclearinput（CLR_L）.shiftdirectionSERA·SERBRXDTXDMCUU174HC164QA3QB4QC5QD6A1B2CLR9CLK8QE10QF11QG12QH1310/10/202342MSIshiftregister74×194，4-bitbidirectional,parallel-in,parallel-outFunctioninputNextstatefunctionS1S0QA*QB*QC*QD*00QAQBQCQDHold01RINQAQBQCShiftright10QBQCQDLINShiftleft11ABCDload注意：此處的左移（QD到QA）、右移（QA到QD）是針對(duì)該器件定義的，與數(shù)據(jù)單元的左/右移不同。10/10/2023433、applicationofshiftregister:serial/parallelconversioncontrolcircuitparallel-serialconversionparallel-indataparallel-serialconversioncontrolcircuitparallel-outdatasourcedestinationserialdataclocksignalsynchronoussignal10/10/202344數(shù)字式程控交換機(jī)的時(shí)分多路復(fù)用系統(tǒng)。10/10/20234510/10/2023465、shift-registercountersbedifferfromthebinaryupordowncounters.ringcounterann-bitshiftregistercanbeusedtoobtainacounterwithnstates.4-bitringcounterQ0*=D0=Q3Q1*=D1=Q0Q2*=D2=Q1Q3*=D3=Q210/10/202347ringcounterinitialstate：Q3Q2Q1Q0=0001D0D1D2D3Q3Q2Q1Q0Q3*Q2*Q1*Q0*00010010001001000100100010000001（D1）Q0（D2）Q1（D3）Q2（D0）Q310/10/202348StatediagramofringcounterAsinglecircleincluding4statescouldbeusedasamodulo-4counter.(byusing4F-Fs)(是順序脈沖發(fā)生器的一種)0001001001001000normalcycleNotself-correcting001101101100100101111110110110110101101000001111Abnormalcyc