基于FPGA多功能波形發(fā)生器試驗報告含程序

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課程設(shè)計試驗報告

學(xué)院：電氣與控制工程學(xué)院班級：微電子1101學(xué)號：1106080118姓名：李少飛日期：2023.4.2

一、電路主體電路圖二、各模塊vhdl代碼三、各模塊仿真結(jié)果四、試驗感悟

一、試驗主體電路

二、各模塊

vhdl代碼

三角

LIBRARYieee;

USEieee.std_logic_1164.all;

LIBRARYaltera_mf;USEaltera_mf.all;

ENTITYsanjiaoISPORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));

ENDsanjiao;

ARCHITECTURESYNOFsanjiaoISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTaltsyncramGENERIC(clock_enable_input_a:STRING;clock_enable_output_a:STRING;init_file:STRING;intended_device_family:STRING;lpm_hint:STRING;lpm_type:STRING;numwords_a:NATURAL;operation_mode:STRING;outdata_aclr_a:STRING;outdata_reg_a:STRING;widthad_a:NATURAL;width_a:NATURAL;width_byteena_a:NATURAL);PORT(clock0:INSTD_LOGIC;address_a:INSTD_LOGIC_VECTOR(7DOWNTO0);q_a:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;

BEGINq\clock_enable_output_a=>\init_file=>\intended_device_family=>\lpm_hint=>\lpm_type=>\numwords_a=>256,operation_mode=>\outdata_aclr_a=>\outdata_reg_a=>\widthad_a=>8,width_a=>8,width_byteena_a=>1)PORTMAP(clock0=>inclock,address_a=>address,q_a=>sub_wire0);

ENDSYN;

-正弦

LIBRARYieee;

USEieee.std_logic_1164.all;

LIBRARYaltera_mf;USEaltera_mf.all;

ENTITYsinxISPORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDsinx;

ARCHITECTURESYNOFsinxISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTaltsyncramGENERIC(clock_enable_input_a:STRING;clock_enable_output_a:STRING;init_file:STRING;intended_device_family:STRING;lpm_hint:STRING;lpm_type:STRING;numwords_a:NATURAL;operation_mode:STRING;outdata_aclr_a:STRING;outdata_reg_a:STRING;widthad_a:NATURAL;width_a:NATURAL;width_byteena_a:NATURAL);PORT(clock0:INSTD_LOGIC;address_a:INSTD_LOGIC_VECTOR(7DOWNTO0);q_a:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;

BEGINq\clock_enable_output_a=>\init_file=>\intended_device