SoC設計方法與實現第十一章-低功耗-OK

第十一章

低功耗設計OutlineWhylowpowerSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowertechniquesPoweranalysisandtoolsTrendsinthefuture2023/11/72WhyLowPowerPotablesystem-BatterylifetimeExample:mobilephone,PDA,DigitalcameraDesktops:highpowerconsumptionReliabilityandperformanceNeedexpensivechippackage,coolingsystemSeveraldeleteriouseffectsDecreasedreliabilityandperformanceIncreasedcost:packagingcostandcoolingsystemExceedpowerlimitsofthechip&system2023/11/73Power,CostandHeatComponent:siliconandpackageIncreaseddiesize(widerpowerbusses)Needbetterthermalcapabilities(packagematerial)NeedbetterelectricalcapabilitiesSystem:CoolingandmechanicalsLargerfansOversizedpowersuppliesPowerlimitstothewall~1100Wdclimitfor110V/20Aplug2023/11/74ChallengeofDesignasProcessScaling2023/11/75OutlineWhylowpowerSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowertechniquesPoweranalysisandtoolsTrendsinthefuture2023/11/76SourceofPowerConsumptionDynamicpowerconsumptionStaticpowerconsumptionKeyareasofpowerconsumptioninSOC2023/11/77SourceofPowerDissipationinCMOSDevicesC=nodecapacitancesNsw=switchingactivities(numberofgatetransitionsperclockcycle)F=frequencyofoperationVDD=supplyvoltageQsc=chargecarriedby shortcircuitcurrent pertransitionIleak=leakagecurrent2023/11/78StaticPowerConsumption:Leakagecurrents:Sub-thresholdcurrent(I2)GateleakageGatetunnelling(I4)Gateinduceddrainleakage(I3)pn-junctionreversecurrent(I1)DCcurrentsAnalogcircuit:sense-amps,pull-upsStatedependent2023/11/79Leakagevs.ProcessWhatwillbethedominatedleakagecurrent?LongChannel(L>1um)VerysmallleakageShortchannel(L>180nm,tox>30A)SubthresholdleakageVeryshortchannel(L>90nm,tox>20A)subthreshold+gateleakageNano-scaled(L<90nm,Tox<20A)Subthreshold+gate+junctionleakageSub-thresholdleakagecurrentHasbecomequiteimportantwithtechnologyscalingGateleakagecurrentIsbecomingimportantwithshrinkingdevicedimensionsPNjunctionleakagecurrentNegligible2023/11/710OutlineWhylowpowerSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowertechniquesLowpoweranalysisandtoolsTrendsinthefuture2023/11/711LowPowerDesignMethodologyMustknowyoursystemMaximizetheperformancewhileminimizethepowerconsumptionMinimizethepowerconsumptionwhilemaximizetheperformance2023/11/712OpportunitiesforPowerSaving2023/11/713OutlineWhylowpowerSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowertechniquesPoweranalysisandtoolsTrendsinthefuture2023/11/714LowPowerTechniquesLeakagepowercontrolDynamicpowercontrolArchitecturelevelpoweroptimizationSystemlevelpoweroptimization2023/11/715LowPowerTechniquesProcessscalingLowVdd,Multi-thresholdVoltagescalingSubstratebias(200mv)Multi-voltage(voltageisland)Dynamicvoltagescaling;multi-thresholdHWdesigntechniquesPre-computation,glitchminimization,Logiclevel,PhysicalleveloptimizationLowpowerSystem/SWPowerawareOperationSystem,compiler,SWdesignetc.2023/11/716LowPowerTechniquesonChipDesignLeakagePowerMultiVtoptimizationPowergatingSubstratebiasPowergatingDynamicPowerMulti-voltagedesignAdvancedclock-gatingGate-levelpoweroptimization2023/11/717TechniquesforReduceLeakagePower2023/11/718UsingMulti-VtLibrariesTimingandleakagetradeoffLowVtcell:fasterspeed,highleakageHighVtcell:slowerspeed,lowerleakagePrinciple:lowVtforcriticalpathandhighVtfornon-criticalpathsHighVtcellonCriticalPathHints:YouneedtohavedualVtlibraryYouneedtopayfortheextralayermaskformulti-vt2023/11/719UsingMulti-VtLibraries–cont.SynthesisStrategy:UsehighVtcellsfirst,thenfixsetupviolationbyreplacethehighVtcellsonthecriticalpathtolowVtcellsUselowVtcellsfirst,thenswaptohighVtcells,fixsetupviolationbyswaplowVtcellsonthepathsNoareapenaltyLibrarydesignforfreelymixandmatchonSoCdesign2023/11/720PowerGatingAlsocalledMulti-ThresholdCMOS(MTCOMS),logicsleepcontrol,etc.Activemode:sleepcontroldeviceson,VDDVandGNDVactasvirtualsupplySleepmode:sleepcontroldevicesoff,reduceleakageHighVttransistorsreducingbothleakageandswitchingpower2023/11/721PowerGating–cont.SleeptransistorsusedonlyonthesupplyrailoronbothsupplyandgroundrailsNotaddedoneverygatePowergatingretentionregisterActivemodeHighperformanceregularFFfunctionSleepModeCut-offVddLowleakagestagesavinglatchfunction2023/11/722BodyBiasVariablethresholdaccordingtobodybiasingZerobodybiasinactivemode(LowVt)Reversebodybiasinstand-bymode(HighVt)Tradeoffbetweenthetimeonmoduleturn-onandleakagecurrentTriplewellstructureCMOSInverterHint:Doyouhavethetriplewellstructuredstandardcelllib?2023/11/723TechniquesforReduceDynamicPower2023/11/724MultiVoltageDesignBlockbasedapproachinthedesignflowNeedtoadditionalisolationcellsandvoltagelevel-shiftercellsbetweenvoltagedomains2023/11/725ClockGatingTechnologyTogglingconsumepower.Enablethemoduleclockonlywhenneededgated_clkEnableLogicGlobalClkComb.LogicDataReg2023/11/726ClockGatingCellDesignProblemwithsimpleclockgating:UncompletedcycleGlitch2023/11/727ClockGatingwithLatchAddatransparent-lowlatchMakesuretheclkgatingcellsareplacedtightlyforcorrectfunction–clkcellhardeningCommonlyinSoC:makea“hardmacro”-clkgatingcellRTLcodeforclkcell:always@(clkorclk_en)if(!clk)

ctrl_latch<=clk_en;assigngclk=ctrl_latch&clkClockgatingcellsandaglitchfreeclockgating2023/11/728ClockGatingWithIntegratedTestLogicAbilitytoletclkpassthroughintestmode(TEST=1)2023/11/729GatedClockinClockTreeDesignDisableclockingneartherootofaclocktree,insteadofateachFF.Specialcaremustbetakeninclktreesynthesistopreventthebuffersinsertedbetweenclkrootandtheclkgatingcell2023/11/730GateLevelOptimizationTechnologyindependentoptimization:Circuitoptimization:logicoptimization,reduceredundantlogicTrimmingforlowpower:reducepositiveslackGateresizingPinswapping/reassignmentRe-mappingPhaseassignmentRe-factoringLowpowerdriventechnologymappinglowpowercell2023/11/731GateLevelOptimization–GateSizingGatesizingDown-sizegatesonfastpathstodecreasetheirinputcapacitancesforminimizingswitchingcurrentinfrontdriverEnlargeheavilyloadedgatestoincreasetheiroutputslewratesforminimizingshort-circuitcurrent2023/11/732DealingwithGlitchesForsometypeofdatapathcircuits,upto60%ofthedynamicpowerisduetoglitchesVeryexpensivecalculationNeedtopropagateprobabilisticwaveforms2023/11/733Example:GlitchMinimizationHazardoustransitionoccursattheoutputofANDgateduetodifferentdelaysthroughtwodifferentdelaypathsconvergingattheinputstothegate2023/11/734PhysicalLevelOptimizationLibraryDesign:Energy-efficientcells

Designplanning:developarealizablefloorplanandrealisticbudgetsforpowerPlacementandrouting:reduceglitchesInplacementoptimization:buffer&wireresizing

Transistorresizing:minimizecapacitanceWidth/Spacing/Shielding/MetallayeroptimizationtoreduceC&R.Reduceviaresistancebyaddingmorevias2023/11/735Physicalleveloptimization–cont.Powerplanning:definespowerringsandmesh.

Powerdrivenfloor-planningDecouplingcapbetweenSupplyandGroundSuddenchangeinpowerconsumptionoccurwhenblocksarepoweredonoroffDecouplingcapacitorhelpstoreducethetransientcurrentforhighspeeddesignHaveseeninfillercellat0.13umprocessButtheleakageondecouplingcapitselfat90nmandbelowmusttakeintoaccount2023/11/736GlobalClockRoutingReduceClockLoadReduceoversizedclockdriverReduce#ofclockdriversReduce#ofclocktracksMinimumWidthClockTracksareresistancelimitedLowerRfordrivabilityLowerCforpowerIncreasewidth&spacetominimizeC&Rwherepossible.Addenoughvia’storeduceresistance2023/11/737ArchitecturelevelPowerOptimizationMemoryOptimizationParallel/PipelineAlgorithm2023/11/738MemoryOptimizationMemorycellredesignReduceleakageDualVtSRAMCellGatedVddSRAMcellGatedGNDSRAMcellPower-awareDRAMMemoryhierarchySmallsegmentEachbankcanindependentlyputintoappropriatepowermodeMemorymanagement&datalocalityCacheMultiplepowerstates2023/11/739SystemLevelPowerOptimizationEnergyisconsumedbyallhardwareunitsSoftwareorganizationaffectshardwareenergyconsumptionManagement:run-timesystemmanagementandcontrolofallunits2023/11/740EnergySavingPrincipleOnlyneedtorunjustfastenoughtomeettheapplicationsoftwaredeadlinesandmaintainqualityRuntaskasslowaspossibleReducevoltagetolowerlevelRuntaskintimeavailableReducevoltagetomatchtimeSource:ARM.IEM:IntellectualEnergyManagement2023/11/741DynamicpowermanagementWhatisDynamicpowermanagement?Toselectiveshutofforslow-downofsystemcomponentsthatareidleorunderutilizedPowermanagerobservessystem&respondsatrun-time2023/11/742WhyOSDirectedPowerManagement?2023/11/743DynamicVoltageandFrequencyScalingDynamicPowerManagementChangethepowerstateofthesystemcomponentstolowertheenergyconsumptiondependingontheperformanceconstraintsDynamicVoltageandFrequencyScaling(DVFS)AdjusttheperformanceandenergyconsumptionlevelswhilethedeviceisactiveKeyistomeetusersperformanceneedswhilesavingenergyReducetheprocessor’svoltageandfrequencytoobtainquadricenergysaving2023/11/744ExampleAcloseloopintelligentenergymanagementIncreasethebatterylifeofhandheldportabledevicesinseveralstagesfrom25%upto400%.DVS&DFSdesignedbyARM&NationalSemiconductorARM&NationalSemiconductor2023/11/745NewsonJuly18,2006:TSMCandARMCollaborationAchievesSignificantPowerReductionOn65nmLow-PowerTestChipPowerManagementStrategyMulti-cornertimingclosurecapability,whichanticipatesthetimingimpactofvoltagescalingonthetimingoflibrarycellsthatofferdifferentthresholdvoltages.Thistechniquerecognizesshiftsinthecriticalpathandearmarksthemfortiminganalysisatanypointinthedesigncycle.Multi-threshold(MT)CMOStechnologyisimplementedtogetherwithdynamicvoltageandfrequencyscaling(DVFS)toreducedynamicandstandby(leakage)powerfordifferentoperatingconditions.Designmethodologiesaredemonstratedforpower-gatingcellwake-up/sleepcontrol,powerisolationandtimingsignoffforvoltageislands.ARMIntelligentEnergyManager(IEM)technologysupportsdynamicvoltageandfrequencyscaling,andisnowbeingextendedtoincludeleakagecontrolusingpowergatingandstateretentionundersoftwarecontrol.2023/11/746SummaryofPowerReductionTechniqueSource:conferencepapers,magazinearticles低功耗技術漏電功耗的減小靜態(tài)功耗的減小時序影響面積影響設計方法影響驗證復雜度影響仿真影響面積優(yōu)化10%10%0%-10%無低無多閾值工藝80%0%0%2%低低無時鐘門控020%0%2%低低無多電壓50%40-50%0%<10%中中低電源門控90-98%~0%4-8%5-15%中高低動態(tài)電壓及動態(tài)頻率縮放50-70%40-70%0%<10%高高高體偏置90%-10%<10%高高高2023/11/747OutlineWhylowpowerSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowertechniquesPoweranalysisandtoolsTrendsinthefuture2023/11/748PurposeFindthemainpowerconsumptioncomponentsinourdesigntohelpusoptimizationdesignFindthepowerconsumptioninearlystagetotoenableefficientdesignspaceexplorationandhelpsystemleveldecisions2023/11/749PowerTypesandUsesPeakpowerNeedtosizepowerbusses,limitgroundnoise(bounce)TimeaveragedpowerPackagechoicesCoolingdevicesandsystemBatterylifeRMS(Rootmeansquare)Usedforelectromigrationrules2023/11/750Accuracyvs.EfficiencyTradeoff2023/11/751PowerEstimationandSimulationRTLEarly-analysis,fastest,simulationpatternrefininganddebuggingeasierLessaccurate,resultsdependontheaccuracyoflibrarydata

GateLevelAccurate-analysis,simulationwi