東南大學(xué)計(jì)算結(jié)構(gòu)CPU報(bào)告

ComputerOrganizationandArchitectureCOURSEDESIGNNAMESTUDENTNUMBERCOURSEComputerOrganizationandArchitectureCourseDesignPROJECTACentralProcessingUnit(CPU)BasingOnVerilogHDLSOFTWAREPLATFORMISE14.1DATEAPR.15.2014PurposeThepurposeofthisprojectistodesignasimpleCPU(CentralProcessingUnit).ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosaywe only need consider the following items: Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.AtleastfourpartsconstituteasimpleCPU:thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.TheuseofISEsoftwarefordesignandsimulation.TasksSingle-address instruction format is used in our simple CPU design. instructionwordcontainstwosections:theoperationcode(opcode),whichdefinesthefunctionofinstructions(addition,subtraction,logicoperations,etc.);theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.Forsimplicity,thesizeofmemoryis256×16inthecomputer.Theinstructionwordhas16bits.Theopcodeparthas8bitsandaddressparthas8bits.TheinstructionwordformatcanbeexpressedinFigure1.Figure1.TheinstructionformatTheopcodeoftherelevantinstructionsarelistedinTable1.InstructionOPCODECommentsADDX00000001ACC+[X]->ACCSUBX00000010ACC-[X]->ACCANDX00000011ACCand[X]->ACCORX00000100ACCor[X]->ACCNOTX00000101NOT[X]->ACCSHIFTR00000110SHIFTACCtoRight1bit,LogicShiftSHIFTL00000111SHIFTACCtoLeft1bit,LogicShiftMPYX00001000ACC×[X]->ACCDIVX00001001ACC÷[X]->ACCJMPGEZX00001010IfACC≥0thenX->PCelsePC+1->PCJMPX00001011X->PCHALT00001100HaltaprogramSTOREX00001101ACC->[X]LOADX00001110[X]->ACCTable1.ListofinstructionsandrelevantopcodesTheoverallconnectionexpressedinthetopmoduleformFigure2.TheoverallconnectionexpressedinthetopmoduleformInternalRegistersandMemoryMemory(Dist_mem_gen_v7_1)The Xilinx LogiCORE? IP Distributed Memory Generator core uses XilinxSynthesisTechnology(XST)tocreateavarietyofdistributedmemories. read-onlymemories(ROMs),single,simpledual,anddual-portrandomaccessmemories(RAMs),andSRL16-basedmemories;Supportsdatadepthsrangingfrom16–65,536words;Supportsdatawidthsrangingfrom1–1024bits.ThismemoryisasingleportRAMgeneratedbyDist_mem_gen_v7_1.MAR(MemoryAddressRegister)MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.MBR(MemoryBufferRegister)MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.Themodulehasbeenhorizontallyinverted.PC(ProgramCounter)PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.IR(InstructionRegister)IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.ACC(Accumulator)ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.Themodulehasbeenhorizontallyinverted.ALU(ArithmeticLogicUnit)ALU is a calculation unit which accomplishes basic arithmetic and operations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows:Table2.ALUOperationsCU(MicroprogrammedControlUnit)WehavelearnttheknowledgeofMicroprogrammedcontrolunit.Here,weonlyreviewsometermsandbasicstructures.IntheMicroprogrammedcontrol,themicroprogramconsistsofsomemicroinstructionsandthemicroprogramisstoredincontrolmemorythatgeneratesallthecontrolsignalsrequiredtoexecutetheinstructionsetcorrectly.Themicroinstructioncontainssomemicro-operationswhichareexecutedatthesametime.Figure3showsthekeyelementsofsuchanimplementation.Thesetofmicroinstructionsisstoredinthecontrolmemory.Thecontroladdressregistercontainstheaddressofthenextmicroinstructionstoberead.Whenamicroinstructionisreadfromthecontrolmemory,itistransferredtoacontrolbufferregister.Theregisterconnectstothecontrollinesemanatingfromthecontrolunit.Thus,readingamicroinstructionfromthecontrolmemoryisthesameasexecutingthatmicroinstruction.Thethirdelementshowninthefigureisasequencingunitthatloadsthecontroladdressregisterandissuesareadcommand.Figure3.ControlUnitMicro-architectureInmydesign,IsimplifythestructureofMU.Figure4showstheControlUnitMicro-architectureinmydesign.CMisaDistributedROMgeneratedbyDist_mem_gen_v7_1.Itsfunctionisthesamewiththecontrolmemoryplusthecontrolbufferregisterinfigure3.Similarly,theSequencingLogic’sfunctionisthesamewithsequencinglogicpluscontroladdressregisterinfigure3.Figure4.ControlUnitMicro-architectureinmydesignControlSignalsControlSignals制系統(tǒng)總線數(shù)據(jù)通路C0C1C2C3C5C4C6C7C8C9C10C11C12C13C14C15C16C17ALUCAR<=CAR+1CAR<=***CAR<=0RWmemoryWmemorymemory<=MBRMBR<=memoryIR<=MBR[15..8]MAR<=MBR[7..0]BR<=MBRPC<=MBRMAR<=PCPC<=PC+1ALU<=BRALU<=ACCACC<=ALUACC<=BRMBR<=ACCALU0ALU1ALU2ALU3Table3.Meaningsofeachbitofcontrolsignal運(yùn)算ALU[3：0]ADD0001SUBX0010ANDX0011ORX0100NOTX0101SHIFTR0110SHIFTL0111MPYX1000DIVX1001Table4.MeaningsofALU[3：0]signalTable5.CPUinstructionsetandrelevantmicro-operationsandcontrolsignalsAsfigure4andtable3shows,thereare2outputbusfromControlUnit.OneisthecontrolsignalbusCS[17：0],theotheroneistheALUFlagsignalbusALUFlag[3：0],whichindicatesthatwhichcalculationisgoingtobeexecutedinALU.Morespecifically,table4showsmeaningsofALU[3：0]signal.Table5showstheCPUinstructionsetand accordinglymicro-operationsandcontrolsignals. Thisisthefoundationofthewholedesign.DesigndescriptionofthesimulationinputwaveformsTwosimulationinputsignalsareneededinmydesign.clk: clock signal of the whole system. The clock period is 10 us. All the registers positive-edge-triggered.reset:resetwhenreset=1.Alltheresetsignalsfortheregistersaresynchronizedtotheclocksignal.Simulationresults(1)1+2+3+……+100=5050Table6.Programof1+2+3+……+100Figure5.Waveformof1+2+3+……+100(2)12×3=36Table7.Programof12×3Figure6.Waveformof12×3(3)12÷3=4Table8.Programof12÷3Figure7.Waveformof12÷3ConclusionsandDiscussionsIttakes46mstofinishthecalculation1+2+3+……+100=5050,intheconditionoftheclockperiod10us.Theresultofthemultiplicationcalculationhasbeenlimitedto8bitsincetheMRregisterisnotused.Thedivisioncalculationcanonlybeencalledexactdivision,sincetheoperatorwhichisusedinthecodeis“/”.ISECPU局部尤其是工具設(shè)計(jì)自己的指令集和其對應(yīng)的微操作。這中間很多地方簡潔出錯，也簡潔使人模糊，這時就要勤于動手在紙上規(guī)劃自己的設(shè)計(jì)。ISE的工作起到很大的促進(jìn)作用。在這中間會對課本學(xué)問有更加透徹深入的理解。這個試驗(yàn)完全由我獨(dú)立完成，其中前期設(shè)計(jì)所使用的時間占到了總花費(fèi)時間的一半，后期編程調(diào)試仿真花費(fèi)了總時間的另一半。AppendixmoduleMAR(input[15:0]MBRdata,input[7:0]PCdata,input[17:0]CS,output[7:0]MA);reg[7:0]MA;always@(posedgeCS[8]orposedgeCS[11])beginif(CS[8]==1)beginMA<=MBRdata[7:0];endif(CS[11]==1)beginMA<=PCdata;endendendmodulemoduleMBR(output[15:0]MBdata,input[17:0]CS,input[15:0]ACC,input[15:0]MEM);reg[15:0]MBdata;

----------MAR--------------------MBR----------always@(posedgeCS[6]orposedgeCS[17])beginif(CS[6]==1)beginMBdata<=MEM;endif(CS[17]==1)beginMBdata<=ACC;endendendmodulemodulePC(inputreset,input[17:0]CS,input[15:0]MBRdata,inputclk,output[7:0]PCdata);reg[7:0]PCdata;

-----------PC----------always@(posedgeclk)beginif(reset==1)beginPCdata<=8”b00000000;endif(CS[10]==1)beginPCdata<=MBRdata[7:0];endif(CS[12]==1)beginPCdata<=PCdata+1;endendendmodulemoduleIR(input[17:0]CS,input[15:0]MBRdata,output[7:0]IRdata);reg[7:0]IRdata;

----------IR----------always@(posedgeCS[7])beginif(CS[7]==1)beginIRdata<=MBRdata[15:8];endendendmodule----------ACC----------moduleACC(input[17:0]CS,input[15:0]ALUdata,input[15:0]BRdata,inputreset,inputclk,output[15:0]ACCdata,outputzflag);reg[15:0]ACCdata;regzflag;always@(posedgeclk)beginif(reset==1)beginACCdata<=16”b0000000000000000;zflag<=1;endelseif(ACCdata[15]==0)beginif(CS[15]==1)beginACCdata<=ALUdata;zflag<=1;endelseif(CS[16]==1)beginACCdata<=BRdata;zflag<=1;endelsebeginzflag<=1;endendelsebeginif(CS[15]==1)beginACCdata<=ALUdata;zflag<=0;endelseif(CS[16]==1)beginACCdata<=BRdata;zflag<=0;endelsebeginzflag<=0;endendendendmodulemoduleALU(input[17:0]CS,input[3:0]ALUFlag,input[15:0]BRdata,input[15:0]ACCdata,inputreset,inputclk,output[15:0]ALUdata);reg[15:0]ALUdata;always@(posedgeclk)beginif(reset==1)beginALUdata<=16”b0000000000000000;endelseif(CS[13]==1&&CS[14]==1)begincase(ALUFlag)1:ALUdata<=ACCdata+BRdata;2:ALUdata<=ACCdata-BRdata;3:ALUdata<=ACCdata&BRdata;4:ALUdata<=ACCdata|BRdata;5:ALUdata<=~BRdata;6:ALUdata<=ACCdata>>1;7:ALUdata<=ACCdata<<1;8:ALUdata<