EDA各類實(shí)驗(yàn)程序

1.八進(jìn)制計(jì)數(shù)器2.八位右移寄存器3.八位右移寄存器（并行輸入串行輸出）4.半加5.半加器6.半減器7.兩數(shù)比較器8.三數(shù)比較器9.D觸發(fā)器10.T觸發(fā)器11.JK1觸發(fā)器12.JK觸發(fā)器13.三位全加器14.SR觸發(fā)器15.T1觸發(fā)器16.三太門17.有D觸發(fā)器構(gòu)成的6位2進(jìn)制計(jì)數(shù)器18.帶同步置數(shù)的7進(jìn)制減法計(jì)數(shù)器（6位右移寄存器）19.二十四進(jìn)制雙向計(jì)數(shù)器20.二選一21.分頻器22.含同步清零的十進(jìn)制加計(jì)數(shù)器23.或門24.7段譯碼器25.8-3優(yōu)先編碼器26.32位鎖存器27.八位左移寄存器28.數(shù)據(jù)選擇器4選129.兩個(gè)三位二進(jìn)制數(shù)全加器306位右移寄存器31-6位右移寄存器327段譯碼器338—334--8位右移寄存器358位左移3683優(yōu)先譯碼器370809AD轉(zhuǎn)換382選139兩個(gè)數(shù)比較器403個(gè)書(shū)比較1.八進(jìn)制計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt8isport(clk:instd_logic;aa:outstd_logic_vector(3downto0));endcnt8;architecturebehavofcnt8issignalcqi:std_logic_vector(4downto0);beginprocess(clk)beginifclk'eventandclk='1'thencqi<=cqi+1;endif;endprocess;aa<=cqi(4downto1);endbehav;2.八位右移寄存器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSREG6BISPORT(CLK,LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:outstd_logic_vector(7downto0));ENDSREG6B;ARCHITECTUREbehavOFSREG6BISSIGNALREG6:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(CLK,LOAD)BEGINIFCLK'EVENTANDCLK='1'THENIFLOAD='1'THENREG6<=DIN;ELSEREG6(5DOWNTO0)<=REG6(6DOWNTO1);ENDIF;ENDIF;ENDPROCESS;Q<=REG6;ENDbehav;3.八位右移寄存器（并行輸入串行輸出）libraryieee;useieee.std_logic_1164.all;entitysreg8bisport(clk,rst:instd_logic;load,en:instd_logic;din:instd_logic_vector(7downto0);qb:outstd_logic);endsreg8b;architecturebehanofsreg8bissignalreg8:std_logic_vector(7downto0);beginprocess(clk,rst,load,en)beginifclk'eventandclk='1'thenifrst='1'thenreg8<="00000000";elsif(en='1')thenif(load='1')thenreg8<=din;elsereg8(6downto0)<=reg8(7downto1);endif;endif;endif;endprocess;qb<=reg8(0);endbehan;4.半加libraryieee;useieee.std_logic_1164.all;entityfadderisport( a: instd_logic; b: instd_logic; c: instd_logic; d: outstd_logic; e: outstd_logic);endentityfadder;architecturefd1offadderisbegin e<=axorbxorc; d<=(aandb)or(aandc)or(bandc);endarchitecturefd1;5.半加器libraryieee;useieee.std_logic_1164.all;entityadisport(a,b:instd_logic;co,so:OUTstd_logic);endentityad;architecturefh1ofadisbeginso<=not(axor(notb));co<=aandb;endarchitecturefh1;6.半減器libraryieee;useieee.std_logic_1164.all;entityadisport(a,b:instd_logic;co,so:OUTstd_logic);endentityad;architecturefh1ofadisbeginco<=(nota)andb;so<=axorb;endarchitecturefh1;7.兩數(shù)比較器libraryieee;useieee.std_logic_1164.all;entitycomp_radisport(a1,b1:inbit;q1:outbit);end;architectureoneofcomp_radisbeginprocess(a1,b1)beginifa1>b1thenq1<='1';elsifa1>b1thenq1<='0';endif;endprocess;end;注釋：a1b1輸入Q1輸出A1>b1得出q1=1A1<b1得出q1=08.三數(shù)比較器libraryieee;useieee.std_logic_1164.all;entitycompisport(a1,b1,c1:std_logic_vector(3downto0);q:outstd_logic_vector(3downto0));end;architectureoneofcompissignalq1,q2:std_logic_vector(3downto0);beginprocess(a1,b1,c1)beginifa1>b1thenq1<=a1;elseq1<=b1;endif;ifq1>=c1thenq2<=q1;elseq2<=c1;endif;q<=q2;endprocess;end;9.D觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDCFQISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTSTD_LOGIC);END;ARCHITECTUREbhvOFDCFQISSIGNALQ1:STD_LOGIC;BEGINPROCESS(CLK,Q1)BEGINIFCLk'EVENTANDCLK='1'THENQ1<=D;ENDIF;ENDPROCESS;Q<=Q1;ENDbhv;10.T觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYTCFQISPORT(CLK:INSTD_LOGIC;T:INSTD_LOGIC;Q:OUTSTD_LOGIC);END;ARCHITECTUREbhvOFTcfqISSIGNALQ1:STD_LOGIC;BEGINPROCESS(CLK,Q1)BEGINIFCLk'EVENTANDCLK='1'thenifT='1'thenQ1<=notq1;elseQ1<=q1;ENDIF;endif;ENDPROCESS;Q<=Q1;ENDbhv;11.JK1觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYjkISPORT(CLK:INSTD_LOGIC;J,K:INSTD_LOGIC;Q:BUFFERSTD_LOGIC);ENDENTITYjk;ARCHITECTUREbhvOFjkISBEGINPROCESS(CLK)BEGINIFCLK'EVENTAND(CLK='1')AND(CLK'LAST_VALUE='0')--shangshengyanTHENQ<=(JAND(NOTQ))OR((NOTK)ANDQ);ENDIF;ENDPROCESS;ENDbhv;12.JK觸發(fā)器libraryieee;useieee.std_logic_1164.all;entityjkisport(j,k,clk:instd_logic;q,nq:bufferstd_logic);end;architecturebehaveofjkissignalq_s,nq_s:std_logic;beginprocess(j,k,clk)beginif(clk'eventandclk='1')thenif(j='0')and(k='1')thenq_s<='0';nq_s<='1';elsif(j='1')and(k='0')thenq_s<='1';nq_s<='0';elsif(j='1')and(k='1')thenq_s<=notq;nq_s<=notnq;endif;endif;q<=q_s;nq<=nq_s;endprocess;end;13.三位全加器libraryieee;useieee.std_logic_1164.all;entitysanisport( a: instd_logic; b: instd_logic; c: instd_logic; d: instd_logic; e: outstd_logic; s: outstd_logic);endentitysan;architecturesanofsanisbegin e<=(canda)or(bandd)or(candb)or(aandb)or(aandd)or(candd); s<=((notc)and(nota)and(notb)andd)or ((notc)and(nota)andband(notd))or ((notc)andaand(notb)and(notd))or ((notc)andaandband(notd))or ((notc)andaandbandd)or (cand(nota)and(notb)and(notd))or (candaand(notb)andd)or (candaandband(notd));endarchitecturesan;14.SR觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYRSisPORT(S,R,res:INstd_logic;Q,NOT_Q:outstd_logic);ENDRS;ARCHITECTUREbehavOFRSISsignalsel1,sel2:std_logic;BEGINprocess(res,sel1,sel2)beginifres='0'thensel1<='0';sel2<='1';elsif(S='1'andR='0')thensel1<='1';sel2<='0';elsif(S='0'andR='1')thensel1<='0';sel2<='1';elsif(S='0'andR='0')thensel1<=sel1;sel2<=sel2;endif;Q<=sel1;NOT_Q<=sel2;endprocess;ENDbehav;15.T1觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtpcfqISPORT(CLK:INSTD_LOGIC;tp:INSTD_LOGIC;Q:OUTSTD_LOGIC);END;ARCHITECTUREbhvOFtpcfqISSIGNALQ1:STD_LOGIC;BEGINPROCESS(CLK,Q1)BEGINIFCLk'EVENTANDCLK='1'THENQ1<=nottp;ENDIF;ENDPROCESS;Q<=Q1;ENDbhv;16.三太門LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_sISport(enable:INSTD_LOGIC;datain:INSTD_LOGIC_VECTOR(7DOWNTO0);dataout:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDtri_s;ARCHITECTUREbhvOFtri_sISBEGINPROCESS(enable,datain)BEGINIFenable='1'THENdataout<=datain;ELSEdataout<="ZZZZZZZZ";ENDIF;ENDPROCESS;ENDbhv;17.有D觸發(fā)器構(gòu)成的6位2進(jìn)制計(jì)數(shù)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYd_ffISPORT(d,clk_s:INSTD_LOGIC;q:OUTSTD_LOGIC;nq:OUTSTD_LOGIC);ENDENTITYd_ff;ARCHITECTUREa_rs_ffOFd_ffISBEGINbin_p_rs_ff:PROCESS(CLK_S)BEGINIFclk_s='1'ANDclk_s'EVENTTHENq<=d;nq<=NOTd;ENDIF;ENDPROCESS;ENDARCHITECTUREa_rs_ff;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcnt_bin_nisGENERIC(n:INTEGER:=6);PORT(q:OUTSTD_LOGIC_VECTOR(0TOn-1);in_1:INSTD_LOGIC);ENDENTITYcnt_bin_n;ARCHITECTUREbehvOFcnt_bin_nISCOMPONENTd_ffPORT(d,clk_s:INSTD_LOGIC;Q,NQ:OUTSTD_LOGIC);ENDCOMPONENTd_ff;SIGNALs:STD_LOGIC_VECTOR(0TOn);BEGINs(0)<=in_1;q_1:FORiIN0TOn-1GENERATEdff:d_ffPORTMAP(s(i+1),s(I),q(i),s(i+1));ENDGENERATE;ENDARCHITECTUREbehv;18.帶同步置數(shù)的7進(jìn)制減法計(jì)數(shù)器（6位右移寄存器）LIBRARYIEEE;--6位右移寄存器USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSREG6BISPORT(CLK,LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(2DOWNTO0);Q:outstd_logic_vector(2downto0));ENDSREG6B;ARCHITECTUREbehavOFSREG6BISBEGINPROCESS(CLK,LOAD)variableREG6:STD_LOGIC_VECTOR(2DOWNTO0);BEGINIFCLK'EVENTANDCLK='1'THENIFLOAD='1'THENREG6:=DIN; ELSifREG6<1THENREG6:="110"; ELSEREG6:=REG6-1;ENDIF;ENDIF;Q<=REG6;ENDPROCESS;ENDbehav;19.二十四進(jìn)制雙向計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt24isport(clk,en,u_d:instd_logic;cq:outstd_logic_vector(4downto0));endcnt24;architecturebehavofcnt24issignalcqi:std_logic_vector(4downto0);beginprocess(clk,en,u_d)beginifen='1'thencqi<=cqi;elsifclk'eventandclk='1'thenifu_d='1'thencqi<=cqi+1;elsecqi<=cqi-1;endif;endif;endprocess;cq(4downto0)<=cqi;endbehav;20.二選一ENTITYmux21aisPORT(a,b,s:INBIT; y:OUTBIT);ENDENTITYmux21a;ARCHITECTUREoneOFmux21aISBEGINPROCESS(a,b,s) BEGINIFs='0'THEN y<=a;ELSE y<=b; ENDIF; ENDPROCESS; ENDARCHITECTUREone;21.分頻器LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYFreDeviderISPORT(Clkin:INStd_Logic;Clkout:OUTStd_Logic);END;ARCHITECTUREDeviderOFFreDeviderISCONSTANTN:Integer:=499;signalcounter:Integerrange0toN;signalClk:Std_Logic;BEGINPROCESS(Clkin)beginIFrising_edge(Clkin)THENIFCounter=Nthencounter<=0;Clk<=notclk;elsecounter<=counter+1;endif;endif;endprocess;clkout<=clk;end;22.含同步清零的十進(jìn)制加計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycout10isport(clk,rst,en:instd_logic;cq:outstd_logic_vector(3downto0);cout:outstd_logic);endcout10;architecturebehavofcout10isbeginprocess(clk,rst,en)variablecqi:std_logic_vector(3downto0);beginifclk'eventandclk='1'thenifrst='1'thencqi:=(others=>'0');elsifen='1'thenifcqi<9thencqi:=cqi+1;elsecqi:=(others=>'0');endif;endif;endif;ifcqi=9thencout<='1';elsecout<='0';endif;cq<=cqi;endprocess;endbehav;23.或門LIBRARYIEEE;--或門邏輯描述USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2aISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYor2a;ARCHITECTUREoneOFor2aISBEGINc<=aORb;ENDARCHITECTUREone;24.7段譯碼器libraryieee;useieee.std_logic_1164.all;entitydecl7sis port(d:instd_logic_vector(3downto0);led:outstd_logic_vector(6downto0));end;architectureaofdecl7sisbeginprocess(d)begincasediswhen"0000"=>led<="0111111";when"0001"=>led<="0000110";when"0010"=>led<="1011011";when"0011"=>led<="1001111";when"0100"=>led<="1100110";when"0101"=>led<="1101101";when"0110"=>led<="1111101";when"0111"=>led<="0000111";when"1000"=>led<="1111111";when"1001"=>led<="1101111";when"1010"=>led<="1110111";when"1011"=>led<="1111100";when"1100"=>led<="0111001";when"1101"=>led<="1011110";when"1110"=>led<="1111001";when"1111"=>led<="1110001";whenothers=>null;endcase;endprocess;enda;25.8-3優(yōu)先編碼器libraryieee;useieee.std_logic_1164.all;entitycoderisport(din:instd_logic_vector(0to7);output:outstd_logic_vector(0to2));endcoder;architecturebehavofcoderissignalsint:std_logic_vector(4downto0);beginprocess(din)beginif(din(7)='0')thenoutput<="000";elsif(din(6)='0')thenoutput<="100";elsif(din(5)='0')thenoutput<="010";elsif(din(4)='0')thenoutput<="110";elsif(din(3)='0')thenoutput<="001";elsif(din(2)='0')thenoutput<="101";elsif(din(1)='0')thenoutput<="011";elseoutput<="111";endif;endprocess;endbehav;26.32位鎖存器libraryieee;useieee.std_logic_1164.all;entityreg32bisport(lk:instd_logic;din:instd_logic_vector(31downto0);dout:outstd_logic_vector(31downto0));endreg32b;architecturebehavofreg32bisbeginprocess(lk,din)beginiflk'eventandlk='1'thendout<=din;endif;endprocess;endbehav;27.八位左移寄存器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYr8ISPORT(CLK,LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:outstd_logic_vector(7downto0));ENDr8;ARCHITECTUREbehavOFr8ISSIGNALREG6:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(CLK,LOAD)BEGINIFCLK'EVENTANDCLK='1'THENIFLOAD='1'THENREG6<=DIN;ELSEREG6(7DOWNTO1)<=REG6(6DOWNTO0);ENDIF;ENDIF;ENDPROCESS;Q<=REG6;ENDbehav;28.數(shù)據(jù)選擇器4選1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41aISPORT(a,b,c,d,s0,s1:INBIT;y:OUTBIT);ENDENTITYmux41a;ARCHITECTUREoneOFmux41aISBEGINPROCESS(a,b,c,d,s0,s1)BEGINIFs1&s0="00"THENy<=a;ELSIFs1&s0="01"THENy<=b;ELSIFs1&s0="10"THENy<=c;ELSEy<=d;ENDIF;ENDPROCESS;ENDARCHITECTURE;29.兩個(gè)三位二進(jìn)制數(shù)全加器libraryieee;useieee.std_logic_1164.all;entitysanjiaisport( ain :instd_logic_vector(2downto0); bin :instd_logic_vector(2downto0); cin :instd_logic; dout:outstd_logic_vector(2downto0); eout:outstd_logic);endentity;architecturebjofsanjiaiscomponentf_adder port(a,b,c:instd_logic; d,e: outstd_logic);endcomponent;signalf,g:std_logic;begin u1: f_adderportmap(a=>ain(0),b=>bin(0),c=>cin,d=>f,e=>dout(0)); u2: f_adderportmap(a=>ain(1),b=>bin(1),c=>f,d=>g,e=>dout(1)); u3: f_adderportmap(a=>ain(2),b=>bin(2),c=>g,d=>eout,e=>dout(2));endarchitecture;306位右移寄存器LIBRARYIEEE;--USEIEEE.STD_LOGIC_1164.ALL;ENTITYSREG8BISPORT(CLK,en:INSTD_LOGIC;DIN:INSTD_LOGIC;Q:outstd_logic_vector(5downto0));ENDSREG8B;ARCHITECTUREbehavOFSREG8BISSIGNALREG8:STD_LOGIC_VECTOR(5DOWNTO0);BEGINPROCESS(CLK,en)BEGINIFCLK'EVENTANDCLK='1'THENifen='1'thenREG8(4DOWNTO0)<=REG8(5DOWNTO1);REG8(5)<=DIN;ENDIF;endif;ENDPROCESS;Q<=REG8;ENDbehav;31-6位右移寄存器LIBRARYIEEE;-USEIEEE.STD_LOGIC_1164.ALL;ENTITYSREG6BISPORT(CLK,LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(5DOWNTO0);Q:outstd_logic_vector(5downto0));ENDSREG6B;ARCHITECTUREbehavOFSREG6BISSIGNALREG6:STD_LOGIC_VECTOR(5DOWNTO0);BEGINPROCESS(CLK,LOAD)BEGINIFCLK'EVENTANDCLK='1'THENIFLOAD='1'THENREG6<=DIN;ELSEREG6(4DOWNTO0)<=REG6(5DOWNTO1);ENDIF;ENDIF;ENDPROCESS;Q<=REG6;ENDbehav;327段譯碼器libraryieee;useieee.std_logic_1164.all;entitydecl7sis port(d:instd_logic_vector(3downto0);led:outstd_logic_vector(6downto0));end;architectureoneofdecl7sisbeginprocess(d)begincasediswhen"0000"=>led<="0111111";when"0001"=>led<="0000110";when"0010"=>led<="1011011";when"0011"=>led<="1001111";when"0100"=>led<="1100110";when"0101"=>led<="1101101";when"0110"=>led<="1111101";when"0111"=>led<="0000111";when"1000"=>led<="1111111";when"1001"=>led<="1101111";when"1010"=>led<="1110111";when"1011"=>led<="1111100";when"1100"=>led<="0111001";when"1101"=>led<="1011110";when"1110"=>led<="1111001";when"1111"=>led<="1110001";whenothers=>null;endcase;endprocess;end;338—3libraryieee;useieee.std_logic_1164.all;entitycoderisport(din:instd_logic_vector(0to7);output:outstd_logic_vector(0to2));endcoder;architecturebehavofcoderissignalsint:std_logic_vector(4downto0);beginprocess(din)beginif(din(7)='0')thenoutput<="000";elsif(din(6)='0')thenoutput<="100";elsif(din(5)='0')thenoutput<="010";elsif(din(4)='0')thenoutput<="110";elsif(din(3)='0')thenoutput<="001";elsif(din(2)='0')thenoutput<="101";elsif(din(1)='0')thenoutput<="011";elseoutput<="111";endif;endprocess;endbehav;34--8位右移寄存器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSREG8BISPORT(CLK,LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:outstd_logic_vector(7downto0));ENDSREG8B;ARCHITECTUREbehavOFSREG8BISSIGNALREG8:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(CLK,LOAD)BEGINIFCLK'EVENTANDCLK='1'THENIFLOAD='1'THENREG8<=DIN;ELSEREG8(7DOWNTO1)<=REG8(6DOWNTO0);ENDIF;ENDIF;ENDPROCESS;Q<=REG8;ENDbehav;358位左移LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYr8ISPORT(CLK,LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:outstd_logic_vector(7downto0));ENDr8;ARCHITECTUREbehavOFr8ISSIGNALREG6:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(CLK,LOAD)BEGINIFCLK'EVENTANDCLK='1'THENIFLOAD='1'THENREG6<=DIN;ELSEREG6(7DOWNTO1)<=REG6(6DOWNTO0);ENDIF;ENDIF;ENDPROCESS;Q<=REG6;ENDbehav;3683優(yōu)先譯碼器libraryieee;useieee.std_logic_1164.all;entitycoderisport(dininstd_logic_vector(0to7);outputoutstd_logic_vector(0to2));endcoder;architecturebehavofcoderissignalsintstd_logic_vector(4downto0);beginprocess(din)beginif(din(7)='0')thenoutput=000;elsif(din(6)='0')thenoutput=100;elsif(din(5)='0')thenoutput=010;elsif(din(4)='0')thenoutput=110;elsif(din(3)='0')thenoutput=001;elsif(din(2)='0')thenoutput=101;elsif(din(1)='0')thenoutput=011;elseoutput=111;endif;endprocess;endbehav;370809AD轉(zhuǎn)換libraryieee;useieee.std_logic_1164.all;entityadcintisport(d:instd_logic_vector(7downto0);clk:instd_logic;eoc:instd_logic;ale:outstd_logic;start:outstd_logic;oe:outstd_logic;adda:outstd_logic;lock0:outstd_logic;