100進制同步計數(shù)器設(shè)計報告

浙江萬里學(xué)院實驗報告成績成績：教師：施炯課程名稱：可編程邏輯器件應(yīng)用實驗名稱：100進制同步計數(shù)器設(shè)計專業(yè)班級：電子103姓名：徐強學(xué)號：2010014092實驗日期：2011.5.10一、實驗?zāi)康模?、掌握計數(shù)器的原理及設(shè)計方法；2、設(shè)計一個0~100的計數(shù)器；3、利用實驗二的七段數(shù)碼管電路進行顯示；二、實驗要求：1、用VHDL語言進行描寫；2、有計數(shù)顯示輸出；3、有清零端和計數(shù)使能端；三、實驗結(jié)果：1.VHDL程序LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL;PACKAGEmy_pkgIS Componentnd2--或門PORT(a,b:INSTD_LOGIC; c:OUTSTD_LOGIC);ENDComponent;Componentled_decoder PORT(din:instd_logic_vector(3downto0);--四位二進制碼輸入seg:outstd_logic_vector(6downto0));--輸出LED七段碼 ENDComponent; ComponentCNT60--2位BCD碼60進制計數(shù)器 PORT (CR:INSTD_LOGIC;EN:INSTD_LOGIC; CLK:INSTD_LOGIC; OUTLOW:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0); OUTHIGH:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0) ); ENDComponent; ComponentCNT100--帶使能和清零信號的100進制計數(shù)器 PORT ( CLK:INSTD_LOGIC; EN:INSTD_LOGIC; CLR:INSTD_LOGIC; OUTLOW:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0); OUTHIGH:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0) ); ENDComponent; Componentfreq_div--50MHZ時鐘分頻出1Hz PORT ( clkinput:INSTD_LOGIC; output:OUTSTD_LOGIC ); ENDComponent; Componentjtd--交通燈控制器 PORT ( CLKIN:INSTD_LOGIC;--50MHZ R1,G1,R2,G2,R3,G3,R4,G4:OUTSTD_LOGIC;--紅綠燈信號輸出 GAO,DI:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0)--倒計時輸出 ); ENDComponent; ENDmy_pkg;LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL;USEwork.my_pkg.ALL; --打開程序包ENTITYDemo3ISPORT(CRl:INSTD_LOGIC;ENl:INSTD_LOGIC;CLKIN:INSTD_LOGIC; LEDLOW,LEDHIGH:OUTSTD_LOGIC_VECTOR(6downto0));ENDDemo3;ARCHITECTUREbehvOFDemo3ISSIGNALCLKTEMP:STD_LOGIC;--定義中轉(zhuǎn)信號SIGNALLEDLOWTEMP,LEDHIGHTEMP:STD_LOGIC_VECTOR(3downto0);BEGIN u1:freq_divPORTMAP(CLKIN,CLKTEMP); --位置關(guān)聯(lián)方式 u2:CNT60PORTMAP(CR=>CRl,EN=>ENl,CLK=>CLKTEMP,OUTLOW=>LEDLOWTEMP,OUTHIGH=>LEDHIGHTEMP); --名字關(guān)聯(lián)方式 u3:led_decoderPORTMAP(LEDLOWTEMP,LEDLOW); --低位數(shù)碼管輸出 u4:led_decoderPORTMAP(LEDHIGHTEMP,LEDHIGH); --高位數(shù)碼管輸出ENDbehv;LIBRARYieee;USEieee.std_logic_1164.all;ENTITYfreq_divISPORT( clkinput:INSTD_LOGIC; output:OUTSTD_LOGIC);ENDfreq_div;ARCHITECTURErtOFfreq_divIS SIGNALcount_signal:INTEGER signalmid1:STD_LOGIC; BEGIN PROCESS(clkinput) BEGIN IF(clkinput'EVENTANDclkinput='1')THEN ifcount_signal=24999999then--50MHzdivisionto1Hz count_signal<=0; mid1<=notmid1; else count_signal<=count_signal+1; endif; output<=mid1; endif; ENDPROCESS;endrt;--文件名：decoder.vhdlibraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entityled_decoderisPort(din:instd_logic_vector(3downto0);--四位二進制碼輸入seg:outstd_logic_vector(6downto0));--輸出LED七段碼endled_decoder;architectureBehavioralofled_decoderisbegin process(din) begin casedinis when"0000"=> seg<="1000000";--0 when"0001"=>seg<="1111001";--1 when"0010"=>seg<="0100100";--2 when"0011"=>seg<="0110000";--3 when"0100"=>seg<="0011001";--4 when"0101"=>seg<="0010010";--5 when"0110"=>seg<="0000010";--6 when"0111"=>seg<="1011000";--7 when"1000"=>seg<="0000000";--8 when"1001"=>seg<="0010000";--9 whenothers=>seg<="0000110";--E endcase;endprocess;endBehavioral;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT60ISPORT(CR:INSTD_LOGIC;EN:INSTD_LOGIC;CLK:INSTD_LOGIC;OUTLOW:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0);OUTHIGH:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));ENDCNT60;ARCHITECTUREbehavOFCNT60ISBEGIN PROCESS(CLK,CR,EN) BEGIN ifCR='1'then OUTHIGH<="0000"; OUTLOW<="0000"; elsifEN='1'thenIFCLK'EVENTANDCLK='1'THEN IFOUTHIGH="1001"ANDOUTLOW="1001"THEN OUTHIGH<="0000"; OUTLOW