計算機(jī)系統(tǒng)基礎(chǔ)課件：處理器設(shè)計

計算機(jī)體系結(jié)構(gòu)

處理器設(shè)計2

4次課2PrinciplesofPipeline3ComputationalExampleSystemComputationrequirestotalof300picosecondsAdditional20picosecondstosaveresultinregisterCanmusthaveclockcycleofatleast320psCombinationallogicReg300ps20psClockDelay=320psThroughput=3.12GOPS43-WayPipelinedVersionSystemDividecombinationallogicinto3blocksof100pseachCanbeginnewoperationassoonaspreviousonepassesthroughstageA.Beginnewoperationevery120psOveralllatencyincreases360psfromstarttofinishRegClockComb.logicARegComb.logicBRegComb.logicC100ps20ps100ps20ps100ps20psDelay=360psThroughput=8.33GOPS5PipelineDiagramsUnpipelinedCannotstartnewoperationuntilpreviousonecompletes3-WayPipelinedUpto3operationsinprocesssimultaneouslyTimeOP1OP2OP3TimeABCABCABCOP1OP2OP36Limitations:NonuniformDelaysRegClockRegComb.logicBRegComb.logicC50ps20ps150ps20ps100ps20psDelay=510psThroughput=5.88GOPSComb.logicATimeOP1OP2OP3ABCABCABC7Limitations:NonuniformDelaysThroughputlimitedbysloweststageOtherstagessitidleformuchofthetimeChallengingtopartitionsystemintobalancedstages8Limitations:RegisterOverheadDelay=420ps,Throughput=14.29GOPSClockRegComb.logic50ps20psRegComb.logic50ps20psRegComb.logic50ps20psRegComb.logic50ps20psRegComb.logic50ps20psRegComb.logic50ps20ps9Limitations:RegisterOverheadAstrytodeepenpipeline,overheadofloadingregistersbecomesmoresignificantPercentageofclockcyclespentloadingregister:1-stagepipeline: 6.25%3-stagepipeline: 16.67%6-stagepipeline: 28.57%Highspeedsofmodernprocessordesignsobtainedthroughverydeeppipelining10DataDependenciesSystemEachoperationdependsonresultfromprecedingoneClockCombinationallogicRegTimeOP1OP2OP311DataHazardsRegClockComb.logicARegComb.logicBRegComb.logicCTimeOP1OP2OP3ABCABCABCOP4ABC12DataHazardsResultdoesnotfeedbackaroundintimefornextoperationPipelininghaschangedbehaviorofsystem1irmovl$50,%eax2addl%eax,%ebx3mrmovl100(%ebx),%edx13Na?vePipelinedImplementation1415SEQ+HardwarePCStageTaskistoselectPCforcurrentinstructionBasedonresultscomputedbypreviousinstructionProcessorStatePCisnolongerstoredinregisterBut,candeterminePCbasedonotherstoredinformation16PCComputationintpc=[ picode==ICALL:pValC; picode==IJXX&&pBch:pValC; Picode==IRET:pValM; 1:pValP;];17PipelineStagesFetchSelectcurrentPCReadinstructionComputeincrementedPCDecodeReadprogramregistersExecuteOperateALUMemoryReadorwritedatamemoryWriteBackUpdateregisterfile18PIPE-HardwarePipelineregistersholdintermediatevaluesfrominstructionexecutionForward(Upward)PathsValuespassedfromonestagetonextCannotjumppaststagese.g.,valCpassesthroughdecode1920FeedbackPathsPredictedPCGuessvalueofnextPCBranchinformationJumptaken/not-takenFall-throughortargetaddressReturnpointReadfrommemoryRegisterupdatesToregisterfilewriteports2122StartfetchofnewinstructionaftercurrentonehascompletedfetchstageNotenoughtimetoreliablydeterminenextinstructionGuesswhichinstructionwillfollowRecoverifpredictionwasincorrectPredictingthePC23PredictingthePCM_valP24OurPredictionStrategyInstructionsthatDon’tTransferControlPredictnextPCtobevalPAlwaysreliableCallandUnconditionalJumpsPredictnextPCtobevalC(destination)Alwaysreliable25OurPredictionStrategyConditionalJumpsPredictnextPCtobevalC(destination)OnlycorrectifbranchistakenTypicallyright60%oftimeRecovery:M_CndandM_valA(valP:nextPC)ReturnInstructionDon’ttrytopredict26SelectPCIntF_predPC=[ f_icodein{IJXX,ICALL}:f_valC; 1:f_valP;];27RecoveringfromPCMispredictionMispredictedJumpWillseebranchflagonceinstructionreachesMemorystageCangetfall-throughPCfromvalA(valP)ReturnInstructionWillgetreturnPCwhenretreacheswrite-backstage28SelectPCintf_PC=[#mispredictedbranch.FetchatincrementedPC M_icode==IJXX&&!M_Cnd:M_valA;#completionofRETinstruciton W_icode==IRET:W_valM;#default:UsepredictedvalueofPC 1:F_predPC];29PipelineDemonstration123456789FDEMWFDEMWFDEMWFDEMWFDEMWCycle5WI1MI2EI3DI4FI5irmovl$1,%eax #I1irmovl$2,%ecx #I2irmovl$3,%edx #I3irmovl$4,%ebx #I4halt #I530AvoidingDataHazard31DataDependenciesinProcessorsResultfromoneinstructionusedasoperandforanotherRead-after-write(RAW)dependencyVerycommoninactualprogramsMustmakesureourpipelinehandlestheseproperlyGetcorrectresultsMinimizeperformanceimpact1irmovl$50,%eax2addl%eax,%ebx3mrmovl100(%ebx),%edxDataDependencies:3Nop’sDecodeval←R[%edx]=10val←R[%eax]=3WriteBackR[%eax]←3Cycle6123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW1011FDEMWFDEMWCycle7#demo-h3.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:nop0x00d:nop0x00e:nop0x00f:addl%edx,%eax0x011:halt33DataDependencies:2Nop’s????#demo-h2.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:nop0x00d:nop0x00e:addl%edx,%eax0x010:haltDecodeval←R[%edx]=10val←R[%eax]=0Cycle6WriteBackR[%eax]←3Error123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW10FDEMWFDEMWDataDependencies:1Nop#demo-h1.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:nop0x00d:addl%edx,%eax0x00f:halt123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW??Decodeval←R[%edx]=0val←R[%eax]=0Cycle5WriteBackR[%edx]←10MemoryM_valE=3M_dstE=%eaxErrorDataDependencies:NoNop#demo-h0.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:addl%edx,%eax0x00e:halt12345678FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW??Decodeval←R[%edx]=0val←R[%eax]=0Cycle4MemoryM_valE=10M_dstE=%edxExecutee_valE←0+3=3E_dstE=%eaxError36ClassesofDataHazardsHazardscanpotentiallyoccurwhenoneinstructionupdatespartoftheprogramstatethatreadbyalaterinstruction37ClassesofDataHazardsProgramstates:Programregisters(identified)Conditioncodes(Nohazards)Bothwrittenandreadintheexecutestage.Programcounter(section4.5.11)ConflictsbetweenupdatingandreadingPCcause

controlhazards(e.g.mispredictedbranchesandret)MemoryBothwrittenandreadinthememorystage.Withoutself-modifiedcode,nohazards.38DataDependencies:2Nop’s????#demo-h2.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:nop0x00d:nop0x00e:addl%edx,%eax0x010:haltDecodeval←R[%edx]=10val←R[%eax]=0Cycle6WriteBackR[%eax]←3Error123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW10FDEMWFDEMW39DataDependencies:2Nop’s#demo-h2.ys0x000:irmovl

$10,%edx0x006:irmovl

$3,%eax0x00c:nop0x00d:nop

bubble0x00e:addl%edx,%eax0x010:halt123456789FDEMWFDEMWFDEMWFEMWDDEMWFDEMW10FFDEMW11Ifinstructionfollowstoocloselyafteronethatwritesregister,slowitdownHoldinstructionindecodeDynamicallyinjectnopintoexecutestagedstMdstE40EMWFDPCPCALUDataMemorySelect

PCrBSelectAALUAALUBMem.controlAddrreadALUfunFetchDecodeExecuteMemoryWritebackdataoutdatainM_valAW_valMW_valEM_valAW_valMd_rvalAf_PCPredict

PCvalEvalMdstEdstMCndvalEvalAdstEdstMicodeifunvalCvalAvalBdstEsrcBvalCvalPicodeifunrApredPCCCe_CndM_CndwritedstMsrcARegisterFileABMEsrcAsrcBd_srcAd_srcBInstructionInstructionMemoryincrementicodeicode41StallConditionSourceRegisterssrcAandsrcBofcurrentinstructionindecodestageDestinationRegistersdstEanddstMfieldsInstructionsinexecute,memory,andwrite-backstagesConditionsrcA==dstEorsrcA==dstMsrcB==dstEorsrcB==dstMSpecialCaseDon’tstallforregisterIDFIndicatesabsenceofregisteroperandDataDependencies:2Nop’s????#demo-h2.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:nop0x00d:nop

bubble0x00e:addl%edx,%eax0x010:haltDecodesrcA=%edxsrcB=%eaxCycle6WriteBackW_dstE=%eaxW_valE=3123456789FDEMWFDEMWFDEMWFEMWDDEMWFDEMW10FFDEMW11#demo-h0.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax

bubble bubble bubble0x00c:addl%edx,%eax0x0e:haltStallingX3123456789FDEMWFDEMWFEMWDEMWDDEMWFDEMW10FFDFEMW11Cycle4??????Cycle5Cycle6DecodesrcA=%edxsrcB=%eaxDecodesrcA=%edxsrcB=%eaxDecodesrcA=%edxsrcB=%eaxExecuteE_dstE=%eaxMemoryM_dstE=%eaxWriteBackW_dstE=%eax44WhatHappensWhenStalling?StallinginstructionheldbackindecodestageFollowinginstructionstaysinfetchstageBubblesinjectedintoexecutestageLikedynamicallygeneratednop’sMovethroughlaterstages0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:addl%edx,%eax#demo-h0.ys0x00e:halt

bubble

bubbleCycle80x00c:addl%edx,%eax0x00e:haltWriteBackMemoryExecuteDecodeFetch45PipelineRegisterModesRisingclockRisingclock__Output=yyyOutput=xInput=ystall=0bubble=0xxNormal46PipelineRegisterModesRisingclockRisingclock__Output=xxxOutput=xInput=ystall=1bubble=0xxStall47PipelineRegisterModesnopRisingclockRisingclock__Output=nopxxOutput=xInput=ystall=0bubble=1BubbleImplementingStallingEMWFDrBsrcAsrcBicodevalEvalMdstEdstMCndicodevalEvalAdstEdstMicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrApredPCd_srcBd_srcAD_icodeE_dstEE_dstMPipecontrollogicD_stallE_bubbleM_dstEM_dstMW_dstEW_dstMF_stall49ImplementingStallingPipelineControlCombinationallogicdetectsstallconditionSetsmodesignalsforhowpipelineregistersshouldupdate50InitialVersionofPipelineControlboolF_stall= d_srcAin{E_dstE,E_dstM,M_dstE,M_dstM, W_dstE,W_dstM}&&!(d_dsrcA==F)|| d_srcBin{E_dstE,E_dstM,M_dstE,M_dstM, W_dstE,W_dstM}&&!(d_dsrcB==F)||boolD_stall= d_srcAin{E_dstE,E_dstM,M_dstE,M_dstM, W_dstE,W_dstM}&&!(d_dsrcA==F)|| d_srcBin{E_dstE,E_dstM,M_dstE,M_dstM, W_dstE,W_dstM}&&!(d_dsrcB==F)||boolE_bubble= d_srcAin{E_dstE,E_dstM,M_dstE,M_dstM, W_dstE,W_dstM}&&!(d_dsrcA==F)|| d_srcBin{E_dstE,E_dstM,M_dstE,M_dstM, W_dstE,W_dstM}&&!(d_dsrcB==F)||51DataForwardingObservationValuegeneratedinexecuteormemorystageTrickPassvaluedirectlyfromgeneratinginstructiontodecodestageNeedstobeavailableatendofdecodestageDataDependencies:2Nop’s????#demo-h2.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:nop0x00d:nop

bubble0x00e:addl%edx,%eax0x010:haltDecodesrcA=%edxsrcB=%eaxCycle6WriteBackW_dstE=%eaxW_valE=3irmovlinWstageDestinationvalueinWpipelineregisterForwardasvalBforDstageval←R[%edx]=10val←W_valE=3R[%eax]←3123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW10FDEMWFDEMW54BypassPathsDecodeStageForwardinglogicselectsvalAandvalBNormallyfromregisterfileForwarding:getvalAorvalBfromlaterpipelinestageForwardingSourcesExecute:valEMemory:valE,valMWriteback:valE,valMDataDependencies:NoNop#demo-h0.ys0x000:irmovl$10,%edx0x006:irmovl$3,%eax0x00c:addl%edx,%eax0x00e:halt12345678FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW??DecodesrcA=%edxsrcB=%eaxCycle4MemoryM_valE=10M_dstE=%edxExecutee_valE←0+3=3E_dstE=%eaxval←M_valE=10val←e_valE=3Register%edxGeneratedbyALUduringpreviouscycleForwardfromMstageasvalARegister%eaxValuejustgeneratedbyALUForwardfromEstageasvalB56ImplementingForwardingAddadditionalfeedbackpathsfromE,M,andWpipelineregistersintodecodestageCreatelogicblockstoselectfrommultiplesourcesforvalAandvalBindecodestage57RegisterfileRegisterfileALUALUDatamemoryDatamemorydstEdstMALUBAddrsrcAsrcBALUfun.dataoutdatainABMEM_valEW_valEW_valMW_valEvalEvalAdstEdstMvalAvalBdstEdstMsrcAsrcBd_srcBd_srcASel+FwdAFwdBvalEvalMdstEdstMm_valMW_valMe_valE58ImplementingForwarding##WhatshouldbetheAvalue?intnew_E_valA=[#UseincrementedPC D_icodein{ICALL,IJXX}:D_valP;#ForwardvalEfromexecute d_srcA==E_dstE:e_valE;#ForwardvalMfrommemory d_srcA==M_dstM:m_valM;#ForwardvalEfrommemory d_srcA==M_dstE:M_valE;#ForwardvalMfromwriteback d_srcA==W_dstM:W_valM;#ForwardvalEfromwriteback d_srcA==W_dstE:W_valE;#Usevaluereadfromregisterfile 1:d_rvalA;];59LimitationofForwarding#demo-luh.ys0x000:irmovl$128,%edx0x006:irmovl$3,%ecx0x00c:rmmovl%ecx,0(%edx)0x012:irmovl$10,%ebx#Load%eax0x018:mrmovl0(%edx),%eax

#Use%eax0x10e:addl%ebx,%eax0x020:haltLoad-usedependencyValueneededbyendof

Dstageincycle7Valuereadfrommemory

inMstageofcycle8123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW10FDEMW11MemoryMemoryM_dstE=%ebxM_valE=10Cycle6Cycle7DecodevalA←M_valM=10valB←R[%eax]=0M_dstM=%eaxm_valM←M[128]=3Error??#demo-luh.ys0x000:irmovl$128,%edx0x006:irmovl$3,%ecx0x00c:rmmovl%ecx,0(%edx)0x012:irmovl$10,%ebx#Load%eax0x018:mrmovl0(%edx),%eax

#Use%eax0x10e:addl%ebx,%eax0x020:haltStallusinginstructionforonecycleCanthenpickuploadedvaluebyforwardingfrommemory60123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWEMW10DDEMW11FDEMWFF12AvoidingLoad/UseHazardMemoryWriteBackW_dstE=%ebxW_valE=10Cycle8DecodevalA←W_valM=10valB←m_valM=3M_dstM=%eaxm_valM←M[128]=3?61DRegisterfileRegisterfileCCCCALUALUrBdstEdstMALUAALUBsrcAsrcBALUfun.DecodeExecuteABMEW_valMW_valEEicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrAd_srcBd_srcAe_BchSel+FwdAFwdBe_valEDetectingLoad/UseHazardConditionTriggerLoad/UseHazardE_icodein{IMRMOVL,IPOPL}&&E_dstMin{d_srcA,d_srcB}#demo-luh.ys0x000:irmovl$128,%edx0x006:irmovl$3,%ecx0x00c:rmmovl%ecx,0(%edx)0x012:irmovl$10,%ebx#Load%eax0x018:mrmovl0(%edx),%eax

#Use%eax0x10e:addl%ebx,%eax0x020:haltStallinstructionsinfetchanddecodestagesInjectbubbleintoexecutestageControlforLoad/UseHazardConditionFDEMWLoad/UseHazardstallstallbubblenormalnormal123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWFDEMWEMW10DDEMW11FDEMWFF1263EMWFDrBsrcAsrcBicodevalEvalMdstEdstMCndicodevalEvalAdstEdstMicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrApredPCd_srcBd_srcAE_icodeE_dstMPipecontrollogicD_stallE_bubbleF_stall64BranchMispredictionExample#demo-j.ys0x000:xorl%eax,%eax0x002:jnet#Nottaken0x007:irmovl$1,%eax#Fallthrough0x00d:nop0x00e:nop0x00f:nop0x010:halt0x011:t:irmovl$3,%edx#Target(Shouldnotexecute)0x017:irmovl$4,%ecx#Shouldnotexecute0x01d:irmovl$5,%edx#ShouldnotexecuteShouldonlyexecutefirst7instructions65SelectPCintF_predPC=[ f_icodein{IJXX,ICALL}:f_valC; 1:f_valP;];1:0x000:xorl%eax,%eax2:0x002:jneT#Nottaken3:0x00e:irmovl$2,%edx#T4:0x014:irmovl$3,%ebx#T+15:0x007:irmovl$1,%eax#FallThrough66BranchMispredictionTraceIncorrectlyexecutetwoinstructionsatbranchtarget123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWCycle5Excutee_valEf2E_dstE=%edxMemoryM_Cnd=0M_valA=0x007DDecodeD_valC=3D_dstE=%ebxFFetchf_valCf1rBf%eax#demo-j.ys0x000:xorl%eax,%eax0x002:jneT

#Nottaken0x007:irmovl$1,%eax0x00d:halt0x00e:T:irmovl$2,%edx0x014:irmovl$3,%ebx0x01a:halt67SelectPCintf_PC=[#mispredictedbranch.FetchatincrementedPC

M_icode==IJXX&&!M_Cnd:M_valA;#completionofRETinstruciton W_icode==IRET:W_valM;#default:UsepredictedvalueofPC 1:F_predPC];68ReturnExample#demo-ret.ys0x000:irmovlStack,%esp#Intializestackpointer0x006:nop #Avoidhazardon%esp0x007:nop0x008:nop0x009:callp#Procedurecall0x00e:irmovl$5,%esi#Returnpoint0x014:halt0x020:.pos0x200x020:p:nop #procedure0x021:nop0x022:nop0x023:ret0x024:irmovl$1,%eax #Shouldnotbeexecuted0x02a:irmovl$2,%ecx #Shouldnotbeexecuted0x030:irmovl$3,%edx #Shouldnotbeexecuted0x036:irmovl$4,%ebx#Shouldnotbeexecuted0x100:.pos0x1000x100:Stack:#Stack:StackpointerRequirelotsofnopstoavoiddatahazards1:0x023:ret2:0x024:irmovl$1,%eax#Oops3:0x02a:irmovl$2,%ecx#Oops4:0x030:irmovl$3,%edx#Oops5:0x00e:irmovl$5,%esi#Retpoint69Incorrectlyexecute3instructionsfollowingret123456789FDEMWFDEMWFDEMWFDEMWFDEMWFDEMWCycle5Excutee_valEf2E_dstE=%ecxMemoryM_valE=1M_dstE=%eaxDDecodeD_valC=3D_dstE=%edxFFetchf_valCf5rBf%esiWriteBackW_ValM=0x00eIncorrectReturnExample70HandlingMisprediction#demo-j2.ys0x000:xorl%eax,%eax0x002:jneT

#Nottaken0x007:irmovl$1,%eax0x00d:halt0x00e:T:nop0x00f:nop0x010irmovl$2,%edx0x016:irmovl$3,%ebx0x01c:halt#demo-j.ys0x000:xorl%eax,%eax0x002:jneT

#Nottaken0x007:irmovl$1,%eax0x00d:halt0x00e:T:irmovl$2,%edx0x014:irmovl$3,%ebx0x01a:halt71HandlingMisprediction#demo-j.ys1:0x000:xorl%eax,%eax2:0x002:jneT#NotTaken3:0x00e:irmovl$2,%edx#T4:bubble5:0x014:irmovl$3,%ebx#T+16:bubble7:0x007:irmovl$1,%eax#Fallthrough8:0x00d:haltPredictbranchastakenFetch2instructionsattargetCancelwhenmispredictedDetectbranchnot-takeninexecutestageOnfollowingcycle,replaceinstructionsinexecuteanddecodebybubblesNosideeffectshaveoccurredyet123456789FDEMWFDEMWFDEMWFDEMWEMW10FDEMWDFFDEMWFDEMWFDEMWFDEMW72DetectingMispredictedBranchConditionTriggerMispredictedBranchE_icode=IJXX&!e_CndMCCCCALUALUALUAALUBALUfun.ExecuteCndicodevalEvalAdstEdstMEicodeifunvalCvalAvalBdstEdstMsrcAsrcBe_Cnd73ControlforMisprediction#demo-j.ys1:0x000:xorl%eax,%eax2:0x002:jneT#NotTaken3:0x00e:irmovl$2,%edx#T4:bubble5:0x014:irmovl$3,%ebx#T+16:bubble7:0x007:irmovl$1,%eax#Fallthrough8:0x00d:halt123456789FDEMWFDEMWFDEMWFDEMWEMW10FDEMWDFFDEMWFDEMWFDEMWFDEMWConditionFDEMWMispredictedBranchnormalbubblebubblenormalnormal74EMWFDrBsrcAsrcBicodevalEvalMdstEdstMBchicodevalEvalAdstEdstMicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrApredPCE_icodePipecontrollogicE_bubbleD_bubble75ReturnExamplePreviouslyexecutedthreeadditionalinstructions#demo-retB.ys0x000:irmovlStack,%esp#Intializestackpointer0x006:callp#Procedurecall0x00b:irmovl$5,%esi#Returnpoint0x011:halt0x020:.pos0x200x020:p:irmovl$-1,%edi#procedure0x026:ret0x027:irmovl$1,%eax #Shouldnotbeexecuted0x02d:irmovl$2,%ecx #Shouldnotbeexecuted0x033:irmovl$3,%edx #Shouldnotbeexecuted0x039:irmovl$4,%ebx#Shouldnotbeexecuted0x100:.pos0x1000x100:Stack:#Stack:Stackpointer#demo_retb1:0x026:ret2:bubble3:bubble4:bubble5:0x00b:irmovl$5,%esi#return76CorrectReturnExampleAsretpassesthroughpipeline,stallatFstageWhileinD,E,andMstagefetchthesameinstructionafterret3times.InjectbubbleintoDstageReleasestallwhenreachWstageFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW???123456789Cycle5FFetchf_valCf5rBf%esiWriteBackW_ValM=0x00b77MDRegisterfileRegisterfileCCCCALUALUrBdstEdstMALUAALUBsrcAsrcBALUfun.DecodeExecuteABMECndicodevalEvalAdstEdstMEicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrAd_srcBd_srcAe_CndSel+FwdAFwdBDetectingReturn78ControlforReturnConditionFDEMWProcessingretstallbubblenormalnormalnormalConditionTriggerProcessingretIRETin{D_icode,E_icode,M_icode}#demo_retb1:0x026:ret2:bubble3:bubble4:bubble5:0x00b:irmovl$5,%esi#returnFDEMWFDEMWFDEMWFDEMWFDEMWFDEMW12345678979EMWFDrBicodevalEvalMdstEdstMCndicodevalEvalAdstEdstMicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrApredPCD_icodeE_icodeM_icodePipecontrollogicD_bubbleF_stall80ControlCasesDetectionConditionTriggerProcessingretIRETin{D_icode,E_icode,M_icode}Load/UseHazardE_icodein{IMRMOVL,IPOPL}&&E_dstMin{d_srcA,d_srcB}MispredictedBranchE_icode=IJXX&!e_CndConditionFDEMWProcessingretstallbubblenormalnormalnormalLoad/UseHazardstallstallbubblenormalnormalMispredictedBranchnormalbubblebubblenormalnormalAction81EMWFDCCCCrBsrcAsrcBicodevalEvalMdstEdstMCndicodevalEvalAdstEdstMicodeifunvalCvalAvalBdstEdstMsrcAsrcBvalCvalPicodeifunrApredPCd_srcBd_srcAe_CndD_icodeE_icodeM_icodeE_dstMPipecontrollogicD_bubbleD_stallE_bubbleF_stall82ImplementingPipelineControlCombinationallogicgeneratespipelinecontrolsignalsActionoccursatstartoffollowingcycle83InitialVersionofPipelineControlboolF_stall=

#Conditionsforaload/usehazard E_icodein{IMRMOVL,IPOPL}&& E_dstMin{d_srcA,d_srcB}||

#Stallingatfetch whileretpassesthroughpipeline IRETin{D_icode,E_icode,M_icode};boolD_stall=

#Conditionsforaload/usehazard E_icodein{IMRMOVL,IPOPL}&& E_dstMin{d_srcA,d_srcB};84InitialVersionofPipelineControlboolD_bubble=

#Mispredictedbranch (E_icode==IJXX&&!e_Bch)||

#Stallingatfetch whileretpassesthroughpipeline IRETin{D_icode,E_icode,M_icode};boolE_bubble=

#Mispredictedbranch (E_icode==IJXX&&!e_Bch)||

#Load/usehazard E_icodein{IMRMOVL,IPOPL}&& E_dstMin{d_srcA,d_srcB};85ControlCombinationsSpecialcasesthatcanariseonsameclockcycleCombinationANot-takenbranch

retinstructionatbranchtargetCombinationBInstructionthatreadsfrommemoryto%espFollowedbyretinstructionLoadEUseDMLoad/useJXXEDMMispredictJXXEDMMispredictEretDMret1retEbubbleDMret2bubbleEbubbleDretMret3EretDMret1EretDMret1retEbubbleDMret2retEbubbleDMret2bubbleEbubbleDretMret3bubbleEbubbleDretMret3CombinationBCombinationA86JXXEDMMispredictJXXEDMMispredictEretDMret1EretDMret1EretDMret1CombinationAConditionFDEMWProcessingretstallbubblenormalnormalnormalMispredictedBranchnormalbubblebubblenormalnormalCombinationstallbubblebubblenormalnormalFmemoryInstructionmemoryPCPCincrementSelectPCFetchM_valAW_valMf_PCPCpredPCControlCombinationA87ControlCombinationAShouldhandleasmispredictedbranchStallsFpipelineregisterButPCselectionlogicwillbeusingM_valAanyhowConditionFDEMWProcessingretstallbubblenormalnormalnormalMispredictedBranchnormalbubblebubblenormalnormalCombinationstallbubblebubblenormalnormal88ControlCombinationBWouldattempttobubbleandstallpipelineregisterDSignaledbyprocessoraspipelineerrorLoadEUseDMLoad/useEretDMEretDMretEretDMCombinationBConditionFDEMWProcessingretstallbubblenormalnormalnormalLoad/UseHazardstallstallbubblenormalnormalCombinationstallbubble+stallbubblenormalnormal89Hand