6410裸機LCD獨立完整程序Tiny6410親測可用1

第頁工具是RVDS2.2開發(fā)板是Tiny6410，本人親測可用的。啟動文件，和主函數(shù)可以自己寫，關鍵是mlcd.c文件！啟動文件中的s3c6410.incimage_cfg.inc和MemParam_mDDR.inc比較大放在了最后面。請自建一人main.c文件，并在ExternLCD_Init();ExternLCD_DrewPixel(intx,inty,intcolor);voidmain(){LCD_Init();LCD_DrawPixel(100,100,0x00);}就可以打一個點了。源程序來自網(wǎng)絡！**************啟動文件strartup.s跳到voidmian函數(shù)*****************************************/INCLUDEs3c6410.incINCLUDEimage_cfg.incINCLUDEMemParam_mDDR.incIMPORTmain;CentrypointforSteppingstoneloader.; AREA|.astart|,ALIGN=2,CODE;AreaNameSETS"|.astart|";MemoryStartEntry;內(nèi)存里直接啟動時入口 PRESERVE8 AREA|C$$code|,CODE,READONLY global MemStartMemStart;DisableWatchDogTimerldrr0,=WTCONldrr1,=0x0strr1,[r0];EnableVICPort@AndrewHuang mrcp15,0,r0,c1,c0,0 orrr0,r0,#(1<<24) mcrp15,0,r0,c1,c0,0bmain DCB "ABCDabcd";END/************************************************************************************mlcd.c文件********調(diào)用LCD_Init();就可完成初始化，調(diào)用LCD_DrawPixel就可以在自定義的x，y打一個color顏色的點************///mlcd.c文件#include"s3c6410_addr.h"#include"utils.h"#include"mlcd.h"#defineLCD_YSIZE(272)#defineLCD_XSIZE(480)#ifdefLCDvolatileunsignedintLCD_BUFFER[272][480];unsignedintaddr=(unsignedint)LCD_BUFFER;voidLCD_DrawPixel(unsignedintx,unsignedinty,unsignedintcolor) if((x<480)&&(y<272)) LCD_BUFFER[y][x]=color;voidLCD_Init(void) //（1）將J管腳的第二功能設為LCDVD、HSYNC、VSYNC、VDEN、VCLK，將I管腳的第二功能設為LCDVD //initgpiofuncforLCD + rGPECON=0x00011111; //GPE0:forLCDBacklightON-OFF.GPE1~4isGPIO. rGPEDAT=0x00000001; //BacklightON(someLCD(3.5)needit,butNEC4.3not) rGPEPUD=0x00000000; //gpio->GPECONSLP=0x00000000; //gpio->GPEPUDSLP=0x00000000; rGPFCON=0x96AAAAAA; //PWM1:forBacklightDimming.GPF13isUSB_PWR.GPF0~12isCAMI/F. //PWM0ControlBuzzer,butnowweconfigitasOUTPUT!!! rGPFDAT=0x00002000; //USB_PWRON.BuzzerOFF. rGPFPUD=0x00000000; //gpio->GPFCONSLP=0x00000000; //gpio->GPFPUDSLP=0x00000000; rGPICON=0xAAAAAAAA; rGPIPUD=0x00000000; //gpio->GPICONSLP=0x00000000; //gpio->GPIPUDSLP=0x00000000; rGPJCON=0x00AAAAAA; rGPJPUD=0x00000000; //gpio->GPJCONSLP=0x00000000; //gpio->GPJPUDSLP=0x00000000; //initgpiofuncforLCD - //LCD rSPCON=rSPCON&~(0x3)|1; rMIFPCON&=~(1<<3); rVIDCON0=(0<<29)|(0<<26)|(0<<17)|(0<<16)|(9<<6)|(0<<5)|(1<<4)|(0<<2); //(0<<29)|(0<<26)|(0<<17)|(1<<16)|(5<<6)|(0<<5)|(1<<4)|(0<<2); rVIDCON1=1<<7;//1=RGB類型LCD設備在VCLK上升沿得到視頻數(shù)據(jù)//+設置屏的時序 rVIDTCON0=(0x03<<16)|(0x02<<8)|(0x02<<0); rVIDTCON1=(0x2d<<16)|(0x04<<8)|(0x06<<0); rVIDTCON2=(271<<11)|(479<<0); rWINCON0=11<<2;//窗口格式控制1124顯示816位//+VIDOSDxA,VIDOSDxB:窗口位置控制 rVIDOSD0A=(0<<11)|(0); rVIDOSD0B=(479<<11)|(271<<0); rVIDOSD0C=(((480*272)&0xFFFFFF)<<0); rVIDW00ADD0B0=((addr>>24)<<24)|(addr&0xffffff); rVIDW00ADD1B0=(addr&0xffffff+480*272); rVIDW00ADD2=(0<<13)|(480); rDITHMODE=(1<<5)|(1<<3)|(1<<1);//+開顯示 rVIDCON0|=3; rWINCON0|=1;//s3c6410.inc文件;Copyright(c)MicrosoftCorporation.Allrightsreserved.;UseofthissourcecodeissubjecttothetermsoftheMicrosoftend-user;licenseagreement(EULA)underwhichyoulicensedthisSOFTWAREPRODUCT.;IfyoudidnotacceptthetermsoftheEULA,youarenotauthorizedtouse;thissourcecode.ForacopyoftheEULA,pleaseseetheLICENSE.RTFonyour;installmedia.;Header:s3c6410.inc;Thisheaderonlythoseregistersrequiredbythestartup;code.Alladdressesarebasedoffthephysicaladdresses(PA)defined;ins3c6410_base_reg.h(s3c6410_base_reg.inc).;CPURevisionDefinition(S3C6410HasEVT0,EVT1EVT0EQU(36410100)EVT1EQU(36410101);SystemClockDefinitionCLK_66_5MHZEQU66500000CLK_133MHZEQU133000000CLK_150MHZEQU150000000CLK_200MHZEQU200000000CLK_266MHZEQU266000000CLK_300MHZEQU300000000CLK_400MHZEQU400000000CLK_450MHZEQU450000000CLK_532MHZEQU532000000CLK_600MHZEQU600000000CLK_666MHZEQU666000000;SyncCLK_667MHZEQU667000000;ASyncCLK_798MHZEQU798000000;SyncCLK_800MHZEQU800000000;ASyncCLK_900MHZEQU900000000CLK_1332MHZEQU1332000000ECLK_96MHZEQU96000000ECLK_84MHZEQU84666667;forIIS44.1KHzECLK_92MHZEQU92160000;forIIS48KHzGBLACPU_REVISIONGBLATARGET_ARM_CLKGBLAS3C6410_ECLKGBLLCHANGE_PLL_CLKDIV_ON_EBOOTGBLLCHANGE_PLL_CLKDIV_ON_KERNELGBLLCLEAR_DRAM_ON_EBOOTGBLLCLEAR_DRAM_ON_KERNELCHANGE_PLL_CLKDIV_ON_EBOOTSETL{TRUE}CHANGE_PLL_CLKDIV_ON_KERNELSETL{TRUE}CLEAR_DRAM_ON_EBOOTSETL{FALSE}CLEAR_DRAM_ON_KERNELSETL{FALSE};Define:SYNCMODE;SYNCMODEusedtosetcpuoperationmodetosyncronousmodeorasyncronousmodeGBLLSYNCMODESYNCMODESETL{TRUE};ChangeCPURevision(S3C6410HASEVT0,EVT1)CPU_REVISIONSETAEVT1;ChangeTARGET_ARM_CLKdefinitionforStartUpcode;TARGET_ARM_CLKSETACLK_66_5MHZ;Sync66.5:66.5:66.5;TARGET_ARM_CLKSETACLK_133MHZ;Sync133:133:66.5;TARGET_ARM_CLKSETACLK_266MHZ;Sync266:133:66.5;TARGET_ARM_CLKSETACLK_400MHZ;Sync400:100:50;TARGET_ARM_CLKSETACLK_450MHZ;Sync450:150:65TARGET_ARM_CLKSETACLK_532MHZ;Sync532:133:66.5;TARGET_ARM_CLKSETACLK_600MHZ;Sync600:150:75;TARGET_ARM_CLKSETACLK_666MHZ;Sync666:133.4:66.5;TARGET_ARM_CLKSETACLK_798MHZ;Sync798:133:66.5;TARGET_ARM_CLKSETACLK_800MHZ;Sync800:133.33:66.66;TARGET_ARM_CLKSETACLK_900MHZ;Sync900:150:75FINEQU12000000;Includethebaseregisterdefinitions;Fout=MDIV*Fin/(PDIV*2^SDIV);Fvco=MDIV*Fin/PDIVINCLUDEs3c6410_base_regs.inc;ChangeS3C6410_ECLKdefinitionforEPLLFout;S3C6410_ECLKSETAECLK_96MHZS3C6410_ECLKSETAECLK_84MHZ;S3C6410_ECLKSETAECLK_92MHZ;SetClockSource:MPLL,APLL;MPLLSetting;400:100:25(AsyncronousMode)[(TARGET_ARM_CLK=CLK_400MHZ);Fvco=800MHz,Fout=200MHzMPLL_MVALEQU(400)MPLL_PVALEQU(6)MPLL_SVALEQU(2);OtherClockuse266MhzformDDRinAsynchronousmode;Fvco=1064MHz,Fout=266MHzMPLL_MVALEQU(266)MPLL_PVALEQU(3)MPLL_SVALEQU(2)MPLL_CLKEQU(((FIN>>MPLL_SVAL)/MPLL_PVAL)*MPLL_MVAL);MPLLClock;APLLSetting[(TARGET_ARM_CLK=CLK_400MHZ);Fvco=800MHz,Fout=400MHzAPLL_MVALEQU(400)APLL_PVALEQU(6)APLL_SVALEQU(1)[(TARGET_ARM_CLK=CLK_532MHZ):LOR:(TARGET_ARM_CLK=CLK_266MHZ):LOR:(TARGET_ARM_CLK=CLK_133MHZ):LOR:(TARGET_ARM_CLK=CLK_66_5MHZ);Fvco=1064MHz,Fout=532MHzAPLL_MVALEQU(266)APLL_PVALEQU(3)APLL_SVALEQU(1)[(TARGET_ARM_CLK=CLK_600MHZ):LAND:(SYNCMODE);Fvco=1200MHz,Fout=600MHzAPLL_MVALEQU(300)APLL_PVALEQU(3)APLL_SVALEQU(1)[(TARGET_ARM_CLK=CLK_666MHZ)[(SYNCMODE):LAND:(CPU_REVISION=EVT1);Fvco=1332MHz,Fout=1332MHzAPLL_MVALEQU(333)APLL_PVALEQU(3)APLL_SVALEQU(0);Fvco=1332MHz,Fout=666MHzAPLL_MVALEQU(333)APLL_PVALEQU(3)APLL_SVALEQU(1)[(TARGET_ARM_CLK=CLK_798MHZ):LAND:(SYNCMODE);Fvco=1596MHz,Fout=798MHzAPLL_MVALEQU(399)APLL_PVALEQU(3)APLL_SVALEQU(1)[(TARGET_ARM_CLK=CLK_800MHZ);Fvco=1600MHz,Fout=800MHzAPLL_MVALEQU(400)APLL_PVALEQU(3)APLL_SVALEQU(1)[((TARGET_ARM_CLK=CLK_900MHZ):LAND:(SYNCMODE)):LOR:(TARGET_ARM_CLK=CLK_450MHZ);Fvco=900MHz,Fout=900MHzAPLL_MVALEQU(225)APLL_PVALEQU(3)APLL_SVALEQU(0)APLL_CLKEQU(((FIN>>APLL_SVAL)/APLL_PVAL)*APLL_MVAL);APLLClock;SetClockDividersMPLL_DIVEQU(2-1);DOUT_MPLL=MPLL_Fout/2[(TARGET_ARM_CLK=CLK_450MHZ):LOR:(TARGET_ARM_CLK=CLK_666MHZ):LOR:(TARGET_ARM_CLK=CLK_266MHZ)APLL_DIVEQU(2-1);ARM_CLK=APLL_CLK/2[(TARGET_ARM_CLK=CLK_133MHZ)APLL_DIVEQU(4-1);ARM_CLK=APLL_CLK/4[(TARGET_ARM_CLK=CLK_66_5MHZ)APLL_DIVEQU(8-1);ARM_CLK=APLL_CLK/8APLL_DIVEQU(1-1);ARM_CLK=APLL_CLKHCLK_DIVEQU(2-1);AHB_CLK=HCLKx2/2[(TARGET_ARM_CLK=CLK_66_5MHZ)PCLK_DIVEQU(2-1);PCLK=HCLKx2/2PCLK_DIVEQU(4-1);PCLK=HCLKx2/4[(SYNCMODE);UseAPLLasMemoryClockSource[(TARGET_ARM_CLK=CLK_532MHZ):LOR:(TARGET_ARM_CLK=CLK_600MHZ):LOR:(TARGET_ARM_CLK=CLK_266MHZ):LOR:(TARGET_ARM_CLK=CLK_133MHZ);ARM:AHB:APB=4:2:1,HCLKx2=APLL_CLK/2HCLKx2_DIVEQU(2-1);HCLKx2=APLL_CLK/2[(TARGET_ARM_CLK=CLK_666MHZ):LAND:(CPU_REVISION=EVT1);ThissettingrequiresenablingMISC_CON[19]HCLKx2_DIVEQU(5-1);HCLKx2=APLL_CLK/5=266.4MHz(Hardwired-PreDivideronEVT1)[(TARGET_ARM_CLK=CLK_798MHZ):LOR:(TARGET_ARM_CLK=CLK_900MHZ):LOR:(TARGET_ARM_CLK=CLK_450MHZ):LOR:(TARGET_ARM_CLK=CLK_800MHZ);ARM:AHB:APB=12:2:1,HCLKx2=APLL_CLK/3HCLKx2_DIVEQU(3-1);HCLKx2=APLL_CLK/3[(TARGET_ARM_CLK=CLK_66_5MHZ)HCLKx2_DIVEQU(4-1);HCLKx2=APLL_CLK/4|;UseMPLLasMemoryClockSource[(TARGET_ARM_CLK=CLK_400MHZ):LOR:(TARGET_ARM_CLK=CLK_532MHZ):LOR:(TARGET_ARM_CLK=CLK_666MHZ);ARM:AHB:APB=4:(2:1),HCLKx2=MPLLHCLKx2_DIVEQU(1-1);HCLKx2=MPLL_CLK];(SYNCMODE)ARM_CLKEQU(APLL_CLK/(APLL_DIV+1))[(SYNCMODE)HCLKEQU(APLL_CLK/(HCLKx2_DIV+1)/(HCLK_DIV+1))HCLKEQU(MPLL_CLK/(HCLKx2_DIV+1)/(HCLK_DIV+1));EPLLFout96MHz[S3C6410_ECLK=ECLK_96MHZ;Fout=96MHzEPLL_MVALEQU(32)EPLL_PVALEQU(1)EPLL_SVALEQU(2)EPLL_KVALEQU(0)];96MHz;EPLLFout84.666667MHz[S3C6410_ECLK=ECLK_84MHZ;Fout=84.67MHzEPLL_MVALEQU(254)EPLL_PVALEQU(9)EPLL_SVALEQU(2)EPLL_KVALEQU(0)];84.666667MHz;EPLLFout92,160,000Hz[S3C6410_ECLK=ECLK_92MHZ;Fout=92.16MHzEPLL_MVALEQU(192)EPLL_PVALEQU(25)EPLL_SVALEQU(0)EPLL_KVALEQU(0)];92.16MHz;CPSRModeBitDefinitionMode_USREQU(0x10)Mode_FIQEQU(0x11)Mode_IRQEQU(0x12)Mode_SVCEQU(0x13)Mode_ABTEQU(0x17)Mode_UNDEQU(0x1B)Mode_SYSEQU(0x1F)Mode_MASKEQU(0x1F)NOINTEQU(0xC0)I_BitEQU(0x80)F_BitEQU(0x40);CP15ModeBitDefinitionR1_iAEQU(1<<31)R1_nFEQU(1<<30)R1_VEEQU(1<<24)R1_IEQU(1<<12)R1_BPEQU(1<<11);ZbitR1_CEQU(1<<2)R1_AEQU(1<<1)R1_MEQU(1<<0);MiscellaneousdefinesWORD_SIZEEQU(4)DW8EQU(0x0)DW16EQU(0x1)DW32EQU(0x2)WAITEQU(0x1<<2)UBLBEQU(0x1<<3);SFRAddress;SysConAPLL_LOCKEQU(0x7e00f000)MPLL_LOCKEQU(0x7e00f004)APLL_CONEQU(0x7e00f00c)MPLL_CONEQU(0x7e00f010)EPLL_CON0EQU(0x7e00f014)EPLL_CON1EQU(0x7e00f018)CLK_SRCEQU(0x7e00f01c)CLK_DIV0EQU(0x7e00f020)CLK_OUTEQU(0x7e00f02c)MEM_SYS_CFGEQU(0x7e00f120)OTHERSEQU(0x7e00f900)RST_STATEQU(0x7E00F904)INFORM0EQU(0x7E00FA00)INFORM1EQU(0x7E00FA04)INFORM2EQU(0x7E00FA08)INFORM3EQU(0x7E00FA0C)vPWR_CFGEQU(0xB2A0F804)vSLEEP_CFGEQU(0xB2A0F818)vOSC_STABLEEQU(0xB2A0F824)vPWR_STABLEEQU(0xB2A0F828)vRST_STATEQU(0xB2A0F904)vINFORM0EQU(0xB2A0FA00)vINFORM1EQU(0xB2A0FA04)vINFORM2EQU(0xB2A0FA08)vINFORM3EQU(0xB2A0FA0C);GPIOGPACONEQU(S3C6410_BASE_REG_PA_GPIO+0x000);GPHCON0EQU(S3C6410_BASE_REG_PA_IOPORT+0x0E0);GPHCON1EQU(S3C6410_BASE_REG_PA_IOPORT+0x0E4);GPHDATEQU(S3C6410_BASE_REG_PA_IOPORT+0x0E8);GPHPUDEQU(S3C6410_BASE_REG_PA_IOPORT+0x0EC);GPH_OneNDEQU0x2GPNCONEQU(S3C6410_BASE_REG_PA_GPIO+0x830)GPNDATEQU(S3C6410_BASE_REG_PA_GPIO+0x834)GPNPUDEQU(S3C6410_BASE_REG_PA_GPIO+0x838)MEM1DRVCONEQU(S3C6410_BASE_REG_PA_GPIO+0x1D4);//0x7F000000->0x92B00000;vGPHCON0EQU(0xB2B08000+0x0E0);vGPHCON1EQU(0xB2B08000+0x0E4);vGPHDATEQU(0xB2B08000+0x0E8);vGPHPUDEQU(0xB2B08000+0x0EC)vGPNCONEQU(0xB2B08000+0x830)vGPNDATEQU(0xB2B08000+0x834)vGPNPUDEQU(0xB2B08000+0x838);vGPNCONEQU(0xB2B08830)vEINT0CON0EQU(0xB2B08900);VICVIC0INTENCLEAREQU(S3C6410_BASE_REG_PA_VIC0+0x14)VIC1INTENCLEAREQU(S3C6410_BASE_REG_PA_VIC1+0x14)vVIC0INTENABLEEQU(0xB0600010);VIC0vVIC0INTENCLEAREQU(0xB0600014);VIC0vVIC1INTENABLEEQU(0xB0700010);VIC1vVIC1INTENCLEAREQU(0xB0700014);VIC1NFDATAEQU0x70200010;NANDFlashdataregister;WatchDogTimerWTCONEQU(0x7e004000);SMCSMBIDCYR0EQU0x70000000SMBWSTRDR0EQU0x70000004SMBWSTWRR0EQU0x70000008SMBWSTOENR0EQU0x7000000cSMBWSTWENR0EQU0x70000010SMBCR0EQU0x70000014SMBSR0EQU0x70000018SMBWSTBRDR0EQU0x7000001cSMBIDCYR1EQU0x70000020SMBWSTRDR1EQU0x70000024SMBWSTWRR1EQU0x70000028SMBWSTOENR1EQU0x7000002cSMBWSTWENR1EQU0x70000030SMBCR1EQU0x70000034SMBSR1EQU0x70000038SMBWSTBRDR1EQU0x7000003cSMBIDCYR2EQU0x70000040SMBWSTRDR2EQU0x70000044SMBWSTWRR2EQU0x70000048SMBWSTOENR2EQU0x7000004cSMBWSTWENR2EQU0x70000050SMBCR2EQU0x70000054SMBSR2EQU0x70000058SMBWSTBRDR2EQU0x7000005cSMBIDCYR3EQU0x70000060SMBWSTRDR3EQU0x70000064SMBWSTWRR3EQU0x70000068SMBWSTOENR3EQU0x7000006cSMBWSTWENR3EQU0x70000070SMBCR3EQU0x70000074SMBSR3EQU0x70000078SMBWSTBRDR3EQU0x7000007cSMBIDCYR4EQU0x70000080SMBWSTRDR4EQU0x70000084SMBWSTWRR4EQU0x70000088SMBWSTOENR4EQU0x7000008cSMBWSTWENR4EQU0x70000090SMBCR4EQU0x70000094SMBSR4EQU0x70000098SMBWSTBRDR4EQU0x7000009cSMBIDCYR5EQU0x700000a0SMBWSTRDR5EQU0x700000a4SMBWSTWRR5EQU0x700000a8SMBWSTOENR5EQU0x700000acSMBWSTWENR5EQU0x700000b0SMBCR5EQU0x700000b4SMBSR5EQU0x700000b8SMBWSTBRDR5EQU0x700000bcSMBIDCYR6EQU0x700000c0SMBWSTRDR6EQU0x700000c4SMBWSTWRR6EQU0x700000c8SMBWSTOENR6EQU0x700000ccSMBWSTWENR6EQU0x700000d0SMBCR6EQU0x700000d4SMBSR6EQU0x700000d8SMBWSTBRDR6EQU0x700000dcSMBIDCYR7EQU0x700000e0SMBWSTRDR7EQU0x700000e4SMBWSTWRR7EQU0x700000e8SMBWSTOENR7EQU0x700000ecSMBWSTWENR7EQU0x700000f0SMBCR7EQU0x700000f4SMBSR7EQU0x700000f8SMBWSTBRDR7EQU0x700000fc;DMCDMC0_BASEEQU0x7e000000DMC1_BASEEQU0x7e001000INDEX_MEMSTATEQU0x0INDEX_MEMCCMDEQU0x4INDEX_DIRECTCMDEQU0x8INDEX_MEMCFGEQU0xcINDEX_REFRESHEQU0x10INDEX_CASLATEQU0x14INDEX_T_DQSSEQU0x18INDEX_T_MRDEQU0x1cINDEX_T_RASEQU0x20INDEX_T_RCEQU0x24INDEX_T_RCDEQU0x28INDEX_T_RFCEQU0x2cINDEX_T_RPEQU0x30INDEX_T_RRDEQU0x34INDEX_T_WREQU0x38INDEX_T_WTREQU0x3cINDEX_T_XPEQU0x40INDEX_T_XSREQU0x44INDEX_T_ESREQU0x48INDEX_MEMCFG2EQU0x4cINDEX_ID_0_CFGEQU0x100INDEX_ID_1_CFGEQU0x104INDEX_ID_2_CFGEQU0x108INDEX_ID_3_CFGEQU0x10cINDEX_ID_4_CFGEQU0x110INDEX_ID_5_CFGEQU0x114INDEX_ID_6_CFGEQU0x118INDEX_ID_7_CFGEQU0x11cINDEX_ID_8_CFGEQU0x120INDEX_ID_9_CFGEQU0x124INDEX_ID_10_CFGEQU0x128INDEX_ID_11_CFGEQU0x12cINDEX_ID_12_CFGEQU0x130INDEX_ID_13_CFGEQU0x134INDEX_ID_14_CFGEQU0x138INDEX_ID_15_CFGEQU0x13cINDEX_CHIP0_CFGEQU0x200INDEX_CHIP1_CFGEQU0x204INDEX_USER_STATEQU0x300INDEX_USER_CFGEQU0x304;MemoryChipdirectcommandDMC_NOP0EQU0x0c0000DMC_NOP1EQU0x1c0000DMC_PA0EQU0x000000;PrechargeallDMC_PA1EQU0x100000DMC_AR0EQU0x040000;AutorefreshDMC_AR1EQU0x140000DMC_SDR_MR0EQU0x080032;MRS,CAS3,BurstLength4DMC_SDR_MR1EQU0x180032DMC_DDR_MR0EQU0x080162DMC_DDR_MR1EQU0x180162DMC_mDDR_MR0EQU0x080032;CAS3,BurstLength4DMC_mDDR_MR1EQU0x180032DMC_mSDR_EMR0EQU0x0a0000;EMRS,DS:Full,PASR:FullArrayDMC_mSDR_EMR1EQU0x1a0000DMC_DDR_EMR0EQU0x090000DMC_DDR_EMR1EQU0x190000DMC_mDDR_EMR0EQU0x0a0000;DS:Full,PASR:FullArrayDMC_mDDR_EMR1EQU0x1a0000END//image_cfg.inc文件;//NAMINGCONVENTION;//TheIMAGE_namingconvention...;//IMAGE_<NAME>_<SECTION>_<MEMORY_DEVICE>_[OFFSET|SIZE|START|END];//<NAME>-WINCE,BOOT,SHARE;//<SECTION>-sectionname:userdefined;//<MEMORY_DEVICE>-thememorydevicetheblockresideson;//OFFSET-numberofbytesfrommemorydevicestartaddress;//SIZE-maximumsizeoftheblock;//START-startaddressofblock(deviceaddress+offset);//END-endaddressofblock(startaddress+size-1);//DRAMBaseAddressDRAM_BASE_PA_STARTEQU(0x50000000)DRAM_BASE_CA_STARTEQU(0x80000000)DRAM_BASE_UA_STARTEQU(0xA0000000)DRAM_SIZEEQU(0x08000000);//SteploaderAreaIMAGE_STEPLOADER_PA_STARTEQU(0x00000000)IMAGE_STEPLOADER_SIZEEQU(0x00001000);//EbootAreaIMAGE_EBOOT_OFFSETEQU(0x00030000)IMAGE_EBOOT_PA_STARTEQU(DRAM_BASE_PA_START+IMAGE_EBOOT_OFFSET)IMAGE_EBOOT_CA_STARTEQU(DRAM_BASE_CA_START+IMAGE_EBOOT_OFFSET)IMAGE_EBOOT_UA_STARTEQU(DRAM_BASE_UA_START+IMAGE_EBOOT_OFFSET)IMAGE_EBOOT_SIZEEQU(0x00080000)EBOOT_BINFS_BUFFER_OFFSETEQU(0x000C0000)EBOOT_BINFS_BUFFER_PA_STARTEQU(DRAM_BASE_PA_START+EBOOT_BINFS_BUFFER_OFFSET)EBOOT_BINFS_BUFFER_CA_STARTEQU(DRAM_BASE_CA_START+EBOOT_BINFS_BUFFER_OFFSET)EBOOT_BINFS_BUFFER_UA_STARTEQU(DRAM_BASE_UA_START+EBOOT_BINFS_BUFFER_OFFSET)EBOOT_BINFS_BUFFER_SIZEEQU(0x00030000)EBOOT_USB_BUFFER_OFFSETEQU(0x04000000)EBOOT_USB_BUFFER_PA_STARTEQU(DRAM_BASE_PA_START+EBOOT_USB_BUFFER_OFFSET)EBOOT_USB_BUFFER_CA_STARTEQU(DRAM_BASE_CA_START+EBOOT_USB_BUFFER_OFFSET)EBOOT_USB_BUFFER_UA_STARTEQU(DRAM_BASE_UA_START+EBOOT_USB_BUFFER_OFFSET);//NKAreaIMAGE_NK_OFFSETEQU(0x00100000)IMAGE_NK_PA_STARTEQU(DRAM_BASE_PA_START+IMAGE_NK_OFFSET)IMAGE_NK_CA_STARTEQU(DRAM_BASE_CA_START+IMAGE_NK_OFFSET)IMAGE_NK_UA_STARTEQU(DRAM_BASE_UA_START+IMAGE_NK_OFFSET);gao0129;IMAGE_NK_SIZEEQU(0x03F00000);SetMaxsize,Thiswillbetailoredautomatically.IMAGE_NK_SIZEEQU(0x02800000);//BSPARGsAreaIMAGE_SHARE_ARGS_OFFSETEQU(0x00020800)IMAGE_SHARE_ARGS_PA_STARTEQU(DRAM_BASE_PA_START+IMAGE_SHARE_ARGS_OFFSET)IMAGE_SHARE_ARGS_CA_STARTEQU(DRAM_BASE_CA_START+IMAGE_SHARE_ARGS_OFFSET)IMAGE_SHARE_ARGS_UA_STARTEQU(DRAM_BASE_UA_START+IMAGE_SHARE_ARGS_OFFSET)IMAGE_SHARE_ARGS_SIZEEQU(0x00000800);//SleepDataAreaIMAGE_SLEEP_DATA_OFFSETEQU(0x00028000)IMAGE_SLEEP_DATA_PA_STARTEQU(DRAM_BASE_PA_START+IMAGE_SLEEP_DATA_OFFSET)IMAGE_SLEEP_DATA_CA_STARTEQU(DRAM_BASE_CA_START+IMAGE_SLEEP_DATA_OFFSET)IMAGE_SLEEP_DATA_UA_STARTEQU(DRAM_BASE_UA_START+IMAGE_SLEEP_DATA_OFFSET)IMAGE_SLEEP_DATA_SIZEEQU(0x00002000);OEMStackLayout;EBOOT,STEPLOADERalsousethisvalueTOP_OF_STACKS_PHYSICALEQU(DRAM_BASE_PA_START+IMAGE_NK_OFFSET);StackTopisinfrontofNKImageTOP_OF_STACKS_VIRTUALEQU(DRAM_BASE_CA_START+IMAGE_NK_OFFSET);StackSizeofEachModeFIQStackSizeEQU256IRQStackSizeEQU256AbortStackSizeEQU256UndefStackSizeEQU256SVCStackSizeEQU1024;UserStackSizeEQU2048;StackLocationofEachMode(inPhysicalAddress)FIQStack_PAEQU(TOP_OF_STACKS_PHYSICAL-0x0)IRQStack_PAEQU(FIQStack_PA-FIQStackSize)AbortStack_PAEQU(IRQStack_PA-IRQStackSize)UndefStack_PAEQU(AbortStack_PA-AbortStackSize)SVCStack_PAEQU(UndefStack_PA-UndefStackSize)UserStack_PAEQU(SVCStack_PA-SVCStackSize);StackLocationofEachMode(inVirtualAddress)FIQStack_VAEQU(TOP_OF_STACKS_VIRTUAL-0x0)IRQStack_VAEQU(FIQStack_VA-FIQStackSize)AbortStack_VAEQU(IRQStack_VA-IRQStackSize)UndefStack_VAEQU(AbortStack_VA-AbortStackSize)SVCStack_VAEQU(UndefStack_VA-UndefStackSize)UserStack_VAEQU(SVCStack_VA-SVCStackSize);SleepDataLayoutSleepState_Data_StartEQU(0)SleepState_WakeAddrEQU(SleepState_Data_Start)SleepState_SYSCTLEQU(SleepState_WakeAddr+WORD_SIZE)SleepState_MMUTTB0EQU(SleepState_SYSCTL+WORD_SIZE)SleepState_MMUTTB1EQU(SleepState_MMUTTB0+WORD_SIZE)SleepState_MMUTTBCTLEQU(SleepState_MMUTTB1+WORD_SIZE)SleepState_MMUDOMAINEQU(SleepState_MMUTTBCTL+WORD_SIZE)SleepState_SVC_SPEQU(SleepState_MMUDOMAIN+WORD_SIZE)SleepState_SVC_SPSREQU(SleepState_SVC_SP+WORD_SIZE)SleepState_FIQ_SPSREQU(SleepState_SVC_SPSR+WORD_SIZE)SleepState_FIQ_R8EQU(SleepState_FIQ_SPSR+WORD_SIZE)SleepState_FIQ_R9EQU(SleepState_FIQ_R8+WORD_SIZE)SleepState_FIQ_R10EQU(SleepState_FIQ_R9+WORD_SIZE)SleepState_FIQ_R11EQU(SleepState_FIQ_R10+WORD_SIZE)SleepState_FIQ_R12EQU(SleepState_FIQ_R11+WORD_SIZE)SleepState_FIQ_SPEQU(SleepState_FIQ_R12+WORD_SIZE)SleepState_FIQ_LREQU(SleepState_FIQ_SP+WORD_SIZE)SleepState_ABT_SPSREQU(SleepState_FIQ_LR+WORD_SIZE)SleepState_ABT_SPEQU(SleepState_ABT_SPSR+WORD_SIZE)SleepState_ABT_LREQU(SleepState_ABT_SP+WORD_SIZE)SleepState_IRQ_SPSREQU(SleepState_ABT_LR+WORD_SIZE)SleepState_IRQ_SPEQU(SleepState_IRQ_SPSR+WORD_SIZE)SleepState_IRQ_LREQU(SleepState_IRQ_SP+WORD_SIZE)SleepState_UND_SPSREQU(SleepState_IRQ_LR+WORD_SIZE)SleepState_UND_SPEQU(SleepState_UND_SPSR+WORD_SIZE)SleepState_UND_LREQU(SleepState_UND_SP+WORD_SIZE)SleepState_SYS_SPEQU(SleepState_UND_LR+WORD_SIZE)SleepState_SYS_LREQU(SleepState_SYS_SP+WORD_SIZE)SleepState_VFP_FPSCREQU(SleepState_SYS_LR+WORD_SIZE)SleepState_VFP_FPEXCEQU(SleepState_VFP_FPSCR+WORD_SIZE)SleepState_VFP_FPINSTEQU(SleepState_VFP_FPEXC+WORD_SIZE)SleepState_VFP_FPINST2EQU(SleepState_VFP_FPINST+WORD_SIZE)SleepState_VFP_S0EQU(SleepState_VFP_FPINST2+WORD_SIZE)SleepState_VFP_S1EQU(SleepState_VFP_S0+WORD_SIZE)SleepState_VFP_S2EQU(SleepState_VFP_S1+WORD_SIZE)SleepState_VFP_S3EQU(SleepState_VFP_S2+WORD_SIZE)SleepState_VFP_S4EQU(SleepState_VFP_S3+WORD_SIZE)SleepState_VFP_S5EQU(SleepState_VFP_S4+WORD_SIZE)SleepState_VFP_S6EQU(SleepState_VFP_S5+WORD_SIZE)SleepState_VFP_S7EQU(SleepState_VFP_S6+WORD_SIZE)SleepState_VFP_S8EQU(SleepState_VFP_S7+WORD_SIZE)SleepState_VFP_S9EQU(SleepState_VFP_S8+WORD_SIZE)SleepState_VFP_S10EQU(SleepState_VFP_S9+WORD_SIZE)SleepState_VFP_S11EQU(SleepState_VFP_S10+WORD_SIZE)SleepState_VFP_S12EQU(SleepState_VFP_S11+WORD_SIZE)SleepState_VFP_S13EQU(SleepState_VFP_S12+WORD_SIZE)SleepState_VFP_S14EQU(SleepState_VFP_S13+WORD_SIZE)SleepState_VFP_S15EQU(SleepState_VFP_S14+WORD_SIZE)SleepState_VFP_S16EQU(SleepState_VFP_S15+WORD_SIZE)SleepState_VFP_S17EQU(SleepState_VFP_S16+WORD_SIZE)SleepState_VFP_S18EQU(SleepState_VFP_S17+WORD_SIZE)SleepState_VFP_S19EQU(SleepState_VFP_S18+WORD_SIZE)SleepState_VFP_S20EQU(SleepState_VFP_S19+WORD_SIZE)SleepState_VFP_S21EQU(SleepState_VFP_S20+WORD_SIZE)SleepState_VFP_S22EQU(SleepState_VFP_S21+WORD_SIZE)SleepState_VFP_S23EQU(SleepState_VFP_S22+WORD_SIZE)SleepState_VFP_S24EQU(SleepState_VFP_S23+WORD_SIZE)SleepState_VFP_S25EQU(SleepState_VFP_S24+WORD_SIZE)SleepState_VFP_S26EQU(SleepState_VFP_S25+WORD_SIZE)SleepState_VFP_S27EQU(SleepState_VFP_S26+WORD_SIZE)SleepState_VFP_S28EQU(SleepState_VFP_S27+WORD_SIZE)SleepState_VFP_S29EQU(SleepState_VFP_S28+WORD_SIZE)SleepState_VFP_S30EQU(Slee