HDL設計數(shù)字UART中英文翻譯1

/畢業(yè)設計(論文)英文翻譯題目:基于FPGA的串口控制器設計院、系(部):專業(yè)與班級:姓名:學號::日期:譯文基于FPGA的串口控制器設計簡介使用硬件描述語言(HDL)設計和開發(fā)驗證FPGA的成為當前的主流因素。使用行為級描述不只增加了產(chǎn)品的設計效率，也在設計中有獨特的驗證方式。目前最流行的HDL語言為Verilog和VHDL。這篇文章將會舉例說明用Verilog語言的設計和驗證數(shù)字異步串行收發(fā)器UART。UART介紹通用異步串行收發(fā)器UART中有二個獨立的VHDL模塊。一個模塊實現(xiàn)發(fā)射功能,當另一個實現(xiàn)接收功能，發(fā)射和接收功能模塊在頂端設計時組合到一起使用,接收和發(fā)射的組合是通信通道所必需的。數(shù)據(jù)寫入發(fā)射器，從接收器讀出，所有的數(shù)據(jù)是以二進制8字節(jié)的信號通過CPU接口。在頂端設計時，地址有發(fā)射器映射，而且接收器通道能容易地建立從兒進入接口，兩者工用一個稱為mclkx16主控時鐘，在每個模塊中mclkx16被分成獨立的波特率時鐘。UART的功能概況UART的基本功能概況見下表.在左邊顯示傳輸保持記錄，移位記錄，傳輸控制時鐘，全部集中在發(fā)射機的txmit端。在右邊的是顯示接收移位寄存器,接收記錄和控制邏輯時鐘，所有都包含在接收模塊的rxcver端，這兩個模組都單獨的投入與產(chǎn)出,大部分的控制線,只有雙向數(shù)據(jù)總線,主時鐘和復位線共享的模塊。頂層UART系統(tǒng)的I/O功能描述UART的標準數(shù)據(jù)格式圖3顯示了UART的串行數(shù)據(jù)格式，串行數(shù)據(jù)包含在幀8個數(shù)據(jù)字節(jié),以與編碼信息比特，在連續(xù)傳輸線路高通，在傳輸初始化時開始低一點.，接下來的低一點開始到8比特的數(shù)據(jù)信息,低位對于后邊高位有重要的作用。然后后邊的8bits數(shù)據(jù)進行奇偶校驗,反饋8位數(shù)據(jù)的結(jié)果。UART時序圖下面顯示怎么將從寄存器里出來的數(shù)據(jù)寫給移位寄存器，并在上升沿速率時鐘時,轉(zhuǎn)向tx輸出。發(fā)送時間如下表，如何得到數(shù)據(jù)從rx傳輸?shù)浇邮找莆患拇嫫魅缓蟠鎯Α０l(fā)送器主控時鐘稱為mclkx16，分頻成正確的等于mclkx16/16的txclk波特率。數(shù)據(jù)以平行的形式鎖存模塊，而轉(zhuǎn)向以串行格式的tx輸出波特率時鐘頻率。數(shù)據(jù)轉(zhuǎn)到tx輸出跟隨串行數(shù)據(jù)格式顯示在圖6。發(fā)送器行為描述發(fā)送器等待新的數(shù)據(jù)來寫入模塊，新的數(shù)據(jù)在發(fā)送器初始化后發(fā)送。數(shù)據(jù)以并行方式傳送串行數(shù)據(jù)幀的tx輸出.當沒有傳輸序列的地方,tx輸出是高通。發(fā)送器實現(xiàn)產(chǎn)生邏輯的Verilog始于模塊端口的聲明，這里定義的信號,是移植到從單元，沒有方向指明這一點。在下一個端口定義來自端口的方向，方向指定為輸入,輸出或(雙向),見表1。指明端口方向來聲明內(nèi)部信號，內(nèi)部信號的Verilog稱為wire和reg數(shù)據(jù)類型，WIRE被數(shù)字低音的分配，REG用在分配Verilog里的always時鐘，座,常常使用邏輯順序的分配,但不是一定的，進一步解釋見Verilog參考書，數(shù)據(jù)類型的內(nèi)部信號如表3。我們現(xiàn)在已經(jīng)通過了所有必要的聲明,并已作好準備,看看實際執(zhí)行，用硬件描述語言使我們描述的功能的發(fā)送器更加行為化,而不是把重點放在它門級。在軟件編程語言，職能和工作程序分成更具可讀性和易處理，一個Verilog的功能與任務是作為相當于復線Verilog代碼,如果某些輸入信號或某些影響產(chǎn)出或變數(shù).使用的職能和任務,通常發(fā)生在多行代碼都是重復使用的設計,從而使得設計易于閱讀和維護肯定，一個Verilog的功能,可以有多種輸入,但始終只有一個輸出,雖然Verilog任務可以兼得多投入,多產(chǎn)出,甚至在某些情況下,非取長補短，下面顯示了Verilog任務,即擁有所有必要的順序語句,用來描述發(fā)送器的轉(zhuǎn)移模式。我們可以看到在移位寄存器有2個標志位tag1和tag2，在描述空閑和置位模塊時產(chǎn)生相同的作用，使用這些Verilog工作,現(xiàn)在我們可以產(chǎn)生一個容易閱讀的行為模型的空穴傳輸過程。如果txdoneandtxdatardy都是正確的，進入發(fā)送器負荷模式.接下來的負載模式下,進入發(fā)送模式轉(zhuǎn)變.，在上升沿的速率時鐘,內(nèi)容tsr轉(zhuǎn)移到tx輸出.奇偶校驗過程產(chǎn)生于tsr變化中,如下所示。重要的一點,就是tsr為零發(fā)生在傳輸過程，在不同的數(shù)據(jù)傳輸時標志位tag和tsr賦零。傳輸序列的模擬在寫上升沿時數(shù)據(jù)總線容量被鎖存，在下一上升沿txclk，thr的容量載入tsr，低電平開始位進入tx，發(fā)送標志位顯示，thr再次等待新的數(shù)據(jù)的寫入。在每個發(fā)送時鐘上升沿，tsr的容量被送入tx，在數(shù)據(jù)傳輸過程中發(fā)生奇偶校驗，周期循環(huán)時奇偶校驗為高，tx產(chǎn)生奇偶檢驗結(jié)果。接收模塊主控時鐘mclkx16分頻到合適的波也率時鐘稱為rxclk，它等于mclkx16/16.串行數(shù)據(jù)為收到的rx輸入模塊，要按照UART的數(shù)據(jù)格式顯示為圖3，收到的數(shù)據(jù)格式以并行形式讀出,通過8位數(shù)據(jù)總線。接收模塊行為描述在連續(xù)發(fā)送時，發(fā)送保持高，根據(jù)標準異步串行UART，接收器在等待閑置模式的rx輸入要低，在rx下降沿接收進入保持模式，現(xiàn)在尋求一種有效的開始位等待新的數(shù)據(jù)幀的到來，當有效的開始位被檢測到時，接收器回到閑置模式，在接收一個數(shù)據(jù)幀,各種校驗和檢查錯誤，當一個完整的數(shù)據(jù)幀收到接收端返回待機模式.，接收器基本運作如下所示。接收頻率為mclkx16，和第一上升沿的rxclk常常發(fā)生在中心點開始位，如下圖顯示，對于中心點的起始位與后邊的數(shù)據(jù)字節(jié)，波特率時鐘是同步。接收器模塊的實現(xiàn)為了產(chǎn)生一個易讀易操作的接收器模塊，用兩中Verilog功能來描述不同的接收方式，當接收在空閑狀態(tài)時，其中一個Verilog稱為空閑復位，而它需要所有必要的順序語句來描述接收機復位條件。當接收器不在復位狀態(tài)，也不在空閑狀態(tài)下，rx輸入端的采樣數(shù)據(jù)，傳輸?shù)揭莆患拇嫫髦?，在進入的數(shù)據(jù)中產(chǎn)生奇偶校驗位，另外一個Verilog稱為數(shù)據(jù)移位，需要所有必要的順序語句來描述上述行為。利用兩個Verilog實現(xiàn)上述功能，現(xiàn)在在復位狀態(tài)，空閑狀態(tài)或者數(shù)據(jù)傳輸狀態(tài)，我們可以產(chǎn)生行為級描述的接收器，所有上述行為是和接收時鐘同步的，它們的實現(xiàn)如下所示。當?shù)碗娖介_始位到達rsr[0]時，一個完整的數(shù)據(jù)幀將會給接收到，在下一個接收時鐘上升沿到來是又回到空閑狀態(tài)，當返回空閑狀態(tài)時，接收器顯示數(shù)據(jù)接收準備，然后數(shù)據(jù)以并行方式讀出，錯誤的標識更新，并返回空閑狀態(tài)，在數(shù)據(jù)讀出后清除，在讀下降沿，rhr的容量鎖存在數(shù)據(jù)總線，表8所示接收器各種錯誤檢查。接收序列的模擬在連續(xù)傳輸時線路高通，在rx輸入下降沿，,內(nèi)部rxcnt開始計數(shù)，和mclkx16同步，如果rx輸入在mclkx16的8個周期循環(huán)，內(nèi)部空閑復位，接收時鐘產(chǎn)生使能，和中心低開始位同步，在接受時鐘上升沿，數(shù)據(jù)從RX傳輸?shù)絉SR，當?shù)烷_始位到底rsr[0]時，在下一個接收時鐘上升沿又被置空閑位，此時失效，在接收序列，剛好產(chǎn)生rxclk的11個周期，為采樣一位低開始位，一位數(shù)據(jù)位，一位奇偶位，一位置高停止位。在返回空閑狀態(tài)，rsr被置入rhr，內(nèi)部標志位更新，接收位產(chǎn)生,rhr容量給讀出，在讀下降沿，rhr應用到數(shù)據(jù)總線。硬件描述語言仿真我們現(xiàn)正研究如何HDL可用于行為級設計,實現(xiàn)了數(shù)字UART。在HDL進行設計的實施更容易閱讀,并希望能理解,它還規(guī)定,能夠方便的描述依存度之間的各種程序,通常是發(fā)生在這樣一個復雜事件驅(qū)動系統(tǒng)，例如UART，我們很快將看到這種依靠各種進程來描述的能力對于實現(xiàn)模擬是確實必須的。Verilog語言中的模擬激勵叫做測試工具，測試工具的Verilog模塊,擁有各線路的HDL代碼要生成仿真激勵,而在同一時間端口影射，這些產(chǎn)生的信號將會模擬。端口影射是完成了被異步通用步收發(fā)傳輸器的級層模塊實例化頂端水平進入測試工具，如下所示。這使得仿真激勵適用于輸入的設計，同時檢測輸出的設計，輸入激勵,可以有條件地反應與輸出，圖19顯示說明如何測試工具端口影射到UART的頂層。在測試工具的輸出的傳輸模塊又循環(huán)到接收器的輸入模塊，這使得發(fā)送器模塊用來作為測試信號發(fā)生器接收器模塊，數(shù)據(jù)可以并行的方式向發(fā)送器，同時回送到輸入的接收機模塊，收到的數(shù)據(jù)最終從接收器以并行格式讀出，為了盡可能實現(xiàn)UART的自動化測試，獨立書Verilog功能如下，發(fā)送寫入功能需要一切必要的聲明來產(chǎn)生一個并行的數(shù)據(jù)寫序的發(fā)送器，數(shù)據(jù)寫入發(fā)送器來完成寫入接收功能，鎖存內(nèi)部測試工具供以后的分析。接收讀出功能需要一切必要的聲明來產(chǎn)生一個并行的數(shù)據(jù)寫序的接收器，數(shù)據(jù)讀出接收器來完成讀出功能，鎖存內(nèi)部測試工具供以后的分析。數(shù)據(jù)比較功能需要一切必要的聲明來同先前寫入發(fā)送器，相應的最新接收數(shù)據(jù)和接收模塊讀出的數(shù)據(jù)比較，如果發(fā)生任何誤差，數(shù)據(jù)比較標志一個從發(fā)送器寫出的數(shù)據(jù)定義錯誤，相應的數(shù)據(jù)也從接收模塊接收和讀出，有任何誤差發(fā)生時，筆記比較數(shù)據(jù)功能將立即停止模擬仿真。綜合HDL作為設計方法比傳統(tǒng)的FPGA設計輸入方式如原理圖方式有若干優(yōu)勢，它同時規(guī)定了極大的靈活性以與高性能的目標裝置的綜合流程，UART綜合流程已針對兩個靈活和高性能的可編程邏輯器件FPGA系列，如pASIC-1和pASIC。UART設計和模擬的文件進入叫做使用HDL語言編輯器的SarosTechnologies的turbow軟件，HDL設計合成了快速高效的正確綜合工具，綜合以后，設計布局使用spde可編程邏輯工具，在布局之后,UART使用有標注的Verilog布局時序模塊，快速Verilog仿真為來自Simucad的SilosIII后布局仿真，所有使用過的工具中可用的工具來自于快速邏輯。TheserialcontrollerdesignbasedonFPGAIntroductionTheuseofhardwaredescriptionlanguage(HDL)isbecomingamoredominantfactor,whendesigningandverifyingFPGAdesigns.Theuseofbehaviorleveldescriptionnotonlyincreasesthedesignproductivity,butalsoprovidesuniqueadvantagesinthedesignverification.ThemostdominantHDLstodayarecalledVerilogandVHDL.ThisapplicationnotewillillustratetheuseofVerilogindesignandverificationofadigitalUART(UniversalAsynchronousReceiver&Transmitter).DefiningtheUART.TheUARTconsistsoftwoindependentHDLmodules.Onemoduleimplementsthetransmitter,whiletheothermoduleimplementsthereceiver.Thetransmitterandreceivermodulescanbecombinedatthetoplevelofthedesign,foranycombinationsoftransmitterandreceiverchannelsrequired.Datacanbewrittentothetransmitterandreadoutfromthereceiver,allthroughasingle8bitbi-directionalCPUinterface.Addressmappingforthetransmitterandreceiverchannelscaneasilybebuildintotheinterfaceatthetoplevelofthedesign.Bothmodulesshareacommonmasterclockcalledmclkx16.Withineachmodulemclkx16aredivideddowntoindependentbaudrateclocks.UARTfunctionaloverview.AbasicoverviewoftheUARTisshownbelow.Atthelefthandsideisshown“transmitholdregister”,“transmitshiftregister”andthetransmitter“controllogic”block,allcontainedwithinthetransmittermodulecalled“txmit”.Attherighthandsideisshownthe“receiveshiftregister”,“receiveholdregister”andthereceiver“controllogic”block,allcontainedwithinthereceivermodulecalled“rxcver”.Thetwomoduleshaveseparateinputsandoutputsformostoftheircontrollines,onlythebi-directionaldatabus,masterclockandresetlinesaresharedbybothmodules.TheUARTstandarddataformat.Infigure3isshowntheUARTserialdataformat.Serialdataarecontainedwithinframesof8databits,aswellascodedinformationbits.Betweensuccessivetransmissions,thetransmissionlineisheldhigh.Atransmissionisinitializedbyaleadinglowstartbit.Nexttotheleadinglowstartbitcomes8bitsofdatainformation,beginningwiththeLSBandafterwardsrepresentedatincreasingsignificanceorderuptotheMSB.Nexttothe8databitscomestheparitybit,representingtheparityresultofthe8databits.Theparitybitcanbeencodedtruebasedonevenparityoroddparitymode.Nexttotheparitybitcomesatrailinghighstopbitindicatingtheendofadataframe..UARTtimingdiagrams.Belowisshown,howdatawrittentothe“transmitholdregister”getsloadedintothe“transmitshiftregister”,andattherisingedgeofthebaudrateclock,shiftedtotxoutput.Belowisshown,howdatagetsshiftedfromrxinputtothe“receiveshiftregister”,andafterwardsloadedintothe“receiveholdregister”.Finallythereceiverraises“rxrdy”flag.TheTransmittermodule.Themasterclockcalledmclkx16aredivideddowntotheproperbaudratecalledtxclkandequalstomclkx16/16.Datawritteninparallelformattothemodulearelatchedinternally,andshiftedinserialformattothetxoutputatthefrequencyofthebaudrateclock.DatashiftedtothetxoutputfollowstheUARTdataformatshowninfig.3.Behavioraldescriptionofthetransmitter.Thetransmitterwaitsfornewdatatobewrittentothemodule.Whennewdataarewrittenatransmitsequenceisinitialized.Datathatwaswritteninparalleltothemodulegetstransmittedasserialdataframesatthetxoutput.Whennotransmitsequenceareinplace,thetxoutputisheldhigh.Implementationofthetransmittermodule.CreatinglogicinVerilogstartswiththemoduleportdeclaration.Heredefinessignals,thatareportedtoandfromthemodule.Nodirectionarespecifiedatthispoint.Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout(bidirectional),andcanbereferredtointable1.Nexttothespecificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenuseforsequentiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsustodescribethefunctionofthetransmitterinamorebehavioralmanner,ratherthanfocusonit’sactualimplementationatgatelevelInsoftwareprogramminglanguage,functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandtasksasconstructs,analogoustosoftwarefunctionsandprocedures.AVerilogfunctionandtaskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymaintain.AVerilogfunctioncanhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”mode.Wehereseethetwotagbitscalledtag1andtag2concatenatedtothe“transmitshiftregister.Similartaskswerecreatedtodescribethetransmitterin“idle”and“l(fā)oad”modes.ByusingtheseVerilogtasks,wecannowcreateavery“easytoread”behavioralmodeloftheholetransmitprocess.Iftxdoneandtxdatardybotharetrue,thetransmitterenterloadmode.Nexttotheloadmode,thetransmitterentersshiftmode.Attherisingedgeofthebaudrateclock,thecontentsoftsrareshiftedtothetxoutput.Paritygenerationtakesplaceduringshiftingofthetsr,asshownbelow.It’simportanttonote,thatthetsrarezerofilledduringtransmission.Thecombinationofthetwotrailingtagbitsandthezerofilledtsrindicatesthedifferentstatesduringshifting.Paritycycleishighoncyclenexttolastcycle,thatmeanswhentsr[1]getstag2.Txdoneishighwhenshiftingisover,thismeanswhentxgetstag2.Basedonthedifferentstatesduringthetransmissionsequence,“databits”,“paritybit”or“stopbit”areultiplexedtothetxoutput.SimulationofatransmitsequenceThecontentsofthedatabusarelatchedintothrattherisingedgeofwrite.Atthenextrisingedgeoftxclk,thecontentsofthrareloadedintotsr,theactivelowstartbitisassertedtotx,andthetxrdyflagindicates,thatthragainisreadyfornewdatatobewritten.Ateachrisingedgeoftxclk,thecontentsoftsrisshiftedtotx.Paritygenerationtakesplaceduringshiftingofdata.Paritycycleishighonecyclenexttolastcycle,andtxgetstheparityresult.Theinternaltxdoneishighwhenshiftingisover,andtheactivehighstopbitisassertedtotx.ForfurtherdetailsontheimplementationcanbereferredtointhedesignsourcefromTheReceivermodule.Themasterclockmclkx16aredivideddowntotheproperbaudrateclockcalledrxclk,andequalstomclkx16/16.Serialdatatobereceivedattherxinputofthemodule,mustfollowtheUARTdataformatshowninfig.3.Datareceivedinserialformatcanbereadoutinparallelformat,throughthe8bitdatabus.Behavioraldescriptionofthereceiver.Betweensuccessivetransmissions,thetransmissionlineisheldhigh,accordingtostandardUARTbehavior.Thereceiverwaitsin“idle”modefortherxinputtogolow.Atthefallingedgeofrxthereceiverenter“hunting”mode,nowsearchingforavalidstartbitofanewdataframetobereceived.Ifavalidstartbitisdetected,thereceiverenter“shiftdata”mode.Ifaninvalidstartbitisdetected,thereceiverreturnsto“idle”mode.Duringreceiveofadataframe,variousparityanderrorchecksareperformed.Whenacompletedataframehasbeenreceivedthereceiverreturnstoidlemode.Thebasicoperationofthereceiverworksasshownbelow,Thefrequencyofrxclkareequaltomclkx16/16,andthefirstrisingedgeoftherxclkwillalwaysoccuratthecenterpointofthestartbit.Belowisshown,howgenerationofthebaudrateclockrxclkaresynchronizedtothecenterpointsofthestartbitandthefollowingdatabits.Implementationofthereceivermodule.Inordertocreateaneasytoreadandeasytomaintainbehavioralmodelofthereceiver,twoVerilogtasksarewrittentodescribethedifferentmodesofthereceiver.TheVerilogtaskcalled“idle_reset”holdsallnecessarysequentialstatementstodescribethereceiveratresetcondition,andwhenthereceiverisinit’sidlemode.Whenthereceiverisnotatit’sresetcondition,andnotinit’sidlemode,thereceiversamplesdataattherxinput,shiftsthedatatothe“receiveshiftregister”,andgeneratesparitybasedontheincomingdata.TheVerilogtaskcalled“shift_data”holdsallnecessarysequentialstatementstodescribeallaboveactions.UsingthetwoVerilogtasksdescribedabove,wearenowabletocreatethebehavioralleveldescriptionofthereceiveratit’sresetcondition,idlemodeorwhenshiftingindata.Allaboveactionsissynchronoustothebaudrateclockcalledrxclk,andtheimplementationisshownbelow.Acompletedataframehasbeenreceived,whentheleadinglowstartbitreachesrsr[0],andthereceiverreturnstoidlemodeagainatthenextrisingedgeofrxclk.Atreturnto“idle”modethereceiverraisesthe“receivedataready”interrupttoindicate,thatthenewdatareceivednowcanbereadoutinparallelformat.Errorflagsareupdatedaswelluponreturnto“idle”mode,andclearedwhendataarereadoutofthereceiver.Atthefallingedgeofread,thecontentsoftherhrarelatchedtothedatabus.Intable8shownbelowarethevariouserrorcheckssupportedbythereceiver.Simulationofareceivesequence.Betweensuccessivetransmissions,thetransmissionlineisheldhigh.Atthefallingedgeofrxinput,theinternalrxcntstartscountingup,synchronoustomclkx16.Ifrxinputstayslowfor8cyclesofmclkx16,theinternalstatusbitidleisreset,andtherebyenablegenerationofrxclk.Rxclkisnowsynchronizedtothecenterpointofthelowstartbit.Attherisingedgeofrxclk,dataareshiftedfromtherxinputtorsr.Whentheleadinglowstartbitreachrsr[0],thenextrisingedgeofrxclkforcesidlehighagain,andtherebydisablegenerationofrxclk.Duringareceivesequence,exactly11cyclesofrxclkisgenerated,inordertosampleatotalof1leadinglowstartbit,8databits,1paritybitand1trailinghighstopbit.Atreturntoidlemode,thecontentsofrsrareloadedintorhr,thestatusflagsareupdated.Theflag“rxrdy”nowindicates,thatthecontentsofrhrcanbereadout.Atthefallingedgeofread,thecontentsofrhrareappliedtothedatabus.UsingHardwareDescriptionLanguageforSimulation.WehavenowstudiedhowHDLcanbeusedforthebehavioralleveldesignimplementationofadigitalUART.WhileHDLmakethedesignimplementationeasiertoreadandhopefullytounderstandaswell,italsoprovidestheabilitytoeasilydescribedependencyinbetweenvariousprocessesthatusuallyoccurinsuchacomplexeventdrivensystems,asforexampletheUART.Thisabilitytodescribedependencyinbetweenvariousprocessesisextremelyneedforsimulationpurposesaswewillseeverysoon.SimulationstimulusinVerilogHDLiscalleda“testfixture”.Atest-fixtureisaVerilogmodulethatholdsalllinesofHDLcodenecessarytogeneratethesimulationstimulus,whileitatthesametimeportmapsthesesignalstothedesignthataretobesimulated.TheportmappingisdonebyhierarchicalmoduleinstantiationoftheUARTtoplevelmoduleintothetest-fixture,asshownbelow.Thisallowssimulationstimulustobeappliedtotheinputsofthedesign,whilemonitoringtheoutputsofthedesign.Inputstimuluscanbemadeconditionallytotheresponseontheoutputsect.Infig.19shownbelowisillustrated,howthetest-fixtureportmapstothetopleveloftheUART.Withinthetest-fixturethetxoutputofthetransmittermoduleisloopedbacktotherxinputofthereceivermodule.Thisallowsthetransmittermoduletobeusedastestsignalgeneratorforthereceivermodule.Datacanbewritteninparallelformattothetransmittermoduleandloopedbackinserialformattotherxinputofthereceivermodule,anddatareceivedcanfinallybereadoutinparallelformatfromthereceivermodule.InordertoautomatethetestingoftheUARTasmuchaspossible,treeindependentVerilogtaskswerewrittenasfollows.TheVerilogtask“write_to_transmitter”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatawritesequencetothetransmittermodule.Datathatarewrittentothetransmitteruponexecutionofthe“write_to_transmitter”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“read_out_receiver”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatareadoutsequencefromthereceivermodule.Datathatarereadoutofthereceiveruponexecutionofthe“read_out_receiver”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“compare_data”holdsallnecessarystatementsrequiredtocomparethepreviousdatawrittentothetransmittermodule,tothecorrespondingandmostrecentdatareceivedandreadoutfromthereceivermodule.Ifanydiscrepancyoccurs,the“compare_data”taskflagsforanerrorbywritingoutthedatavaluesthatwerewrittentothetransmittermodule,aswellasthecorrespondingdatavaluesthatwerereceivedbyandreadoutfromthereceivermodule.Thesimulationisimmediatelystoppedbythe“compare_data”taskifanydiscrepancyoccurs.BesidesthetreeabovementionedVerilogtasks,thetest-fixtureholdsthestatementstogeneratethemclkx16,themasterresetsignalsaswellasthe“txtorx”loopbackfeature.Thestatementsareconsideredtrivial,andwillnotbeillustratedhere,butcanbereferredtowithinthetest-fixtureitself.Thecoreofthetest-fixtureisabehaviorallevel“forloop”thatexecutesthetreeabovementionedVerilogtasksinordertowriteallpossibledatacombinationstothetransmitterandverifythatsamedatagetsproperlyreceivedbythereceiver.Theforloopisshowedbelowinfigure21.TheaboveshownforloopusestheVerilog“wait”statement.The“wait”statementisaconcurrentprocessstatementthatwaitsforitconditionalexpressiontobecometrue,anhenceinthiscase,theforloopwaitsforthereceivertocompleteanycurrentreceivesequenceindicatedbythe“rxrdy”flagtogohigh.Conceptuallytheexecutionoftheforloopstopsuntil“rxrdy”goeshigh.When“rxrdy”goeshigh,theforloopimmediatelyexecutesthe“read_out_receiver”task,followedbythe“compare_data”task.AccordingtotheUARTdataformatshowedinfig.3,thetest-fixturehavetoprocess256differentdatacombinationtotheUARTinordertotestallpossibledatacombinations.Whentheforloophaveprocessedalldatacombinationswithoutanyerrorflagsfromthe“compare_data”task,thetest-fixturefinallycongratulatesandstops.Infigure22isshownasimulationsequenceusinga2MHzbaudratefrequency,andillustratestheexecutionoftheforloopfromfigure21.1.Dataarewrittentothetransmitteruponexecutionofthewrite_to_transmitter”task.2.Thedatawrittenareautomaticallylatchedintothesignalcalled“data_written[7:0]”attherisingedgeofthewritestrobe.3.Thetxrdyflagindicateswhenthetransmitterisreadyfornewdatatobewritten.4.Attheselectedbaudratethedatawritteninparallelformattothetransmitternowgetstransmittedinserialformatthroughthetxoutput.5.The