HDL設(shè)計(jì)數(shù)字UART中英文翻譯1

/畢業(yè)設(shè)計(jì)(論文)英文翻譯題目:基于FPGA的串口控制器設(shè)計(jì)院、系(部):專(zhuān)業(yè)與班級(jí):姓名:學(xué)號(hào)::日期:譯文基于FPGA的串口控制器設(shè)計(jì)簡(jiǎn)介使用硬件描述語(yǔ)言(HDL)設(shè)計(jì)和開(kāi)發(fā)驗(yàn)證FPGA的成為當(dāng)前的主流因素。使用行為級(jí)描述不只增加了產(chǎn)品的設(shè)計(jì)效率，也在設(shè)計(jì)中有獨(dú)特的驗(yàn)證方式。目前最流行的HDL語(yǔ)言為Verilog和VHDL。這篇文章將會(huì)舉例說(shuō)明用Verilog語(yǔ)言的設(shè)計(jì)和驗(yàn)證數(shù)字異步串行收發(fā)器UART。UART介紹通用異步串行收發(fā)器UART中有二個(gè)獨(dú)立的VHDL模塊。一個(gè)模塊實(shí)現(xiàn)發(fā)射功能,當(dāng)另一個(gè)實(shí)現(xiàn)接收功能，發(fā)射和接收功能模塊在頂端設(shè)計(jì)時(shí)組合到一起使用,接收和發(fā)射的組合是通信通道所必需的。數(shù)據(jù)寫(xiě)入發(fā)射器，從接收器讀出，所有的數(shù)據(jù)是以二進(jìn)制8字節(jié)的信號(hào)通過(guò)CPU接口。在頂端設(shè)計(jì)時(shí)，地址有發(fā)射器映射，而且接收器通道能容易地建立從兒進(jìn)入接口，兩者工用一個(gè)稱(chēng)為mclkx16主控時(shí)鐘，在每個(gè)模塊中mclkx16被分成獨(dú)立的波特率時(shí)鐘。UART的功能概況UART的基本功能概況見(jiàn)下表.在左邊顯示傳輸保持記錄，移位記錄，傳輸控制時(shí)鐘，全部集中在發(fā)射機(jī)的txmit端。在右邊的是顯示接收移位寄存器,接收記錄和控制邏輯時(shí)鐘，所有都包含在接收模塊的rxcver端，這兩個(gè)模組都單獨(dú)的投入與產(chǎn)出,大部分的控制線,只有雙向數(shù)據(jù)總線,主時(shí)鐘和復(fù)位線共享的模塊。頂層UART系統(tǒng)的I/O功能描述UART的標(biāo)準(zhǔn)數(shù)據(jù)格式圖3顯示了UART的串行數(shù)據(jù)格式，串行數(shù)據(jù)包含在幀8個(gè)數(shù)據(jù)字節(jié),以與編碼信息比特，在連續(xù)傳輸線路高通，在傳輸初始化時(shí)開(kāi)始低一點(diǎn).，接下來(lái)的低一點(diǎn)開(kāi)始到8比特的數(shù)據(jù)信息,低位對(duì)于后邊高位有重要的作用。然后后邊的8bits數(shù)據(jù)進(jìn)行奇偶校驗(yàn),反饋8位數(shù)據(jù)的結(jié)果。UART時(shí)序圖下面顯示怎么將從寄存器里出來(lái)的數(shù)據(jù)寫(xiě)給移位寄存器，并在上升沿速率時(shí)鐘時(shí),轉(zhuǎn)向tx輸出。發(fā)送時(shí)間如下表，如何得到數(shù)據(jù)從rx傳輸?shù)浇邮找莆患拇嫫魅缓蟠鎯?chǔ)。發(fā)送器主控時(shí)鐘稱(chēng)為mclkx16，分頻成正確的等于mclkx16/16的txclk波特率。數(shù)據(jù)以平行的形式鎖存模塊，而轉(zhuǎn)向以串行格式的tx輸出波特率時(shí)鐘頻率。數(shù)據(jù)轉(zhuǎn)到tx輸出跟隨串行數(shù)據(jù)格式顯示在圖6。發(fā)送器行為描述發(fā)送器等待新的數(shù)據(jù)來(lái)寫(xiě)入模塊，新的數(shù)據(jù)在發(fā)送器初始化后發(fā)送。數(shù)據(jù)以并行方式傳送串行數(shù)據(jù)幀的tx輸出.當(dāng)沒(méi)有傳輸序列的地方,tx輸出是高通。發(fā)送器實(shí)現(xiàn)產(chǎn)生邏輯的Verilog始于模塊端口的聲明，這里定義的信號(hào),是移植到從單元，沒(méi)有方向指明這一點(diǎn)。在下一個(gè)端口定義來(lái)自端口的方向，方向指定為輸入,輸出或(雙向),見(jiàn)表1。指明端口方向來(lái)聲明內(nèi)部信號(hào)，內(nèi)部信號(hào)的Verilog稱(chēng)為wire和reg數(shù)據(jù)類(lèi)型，WIRE被數(shù)字低音的分配，REG用在分配Verilog里的always時(shí)鐘，座,常常使用邏輯順序的分配,但不是一定的，進(jìn)一步解釋見(jiàn)Verilog參考書(shū)，數(shù)據(jù)類(lèi)型的內(nèi)部信號(hào)如表3。我們現(xiàn)在已經(jīng)通過(guò)了所有必要的聲明,并已作好準(zhǔn)備,看看實(shí)際執(zhí)行，用硬件描述語(yǔ)言使我們描述的功能的發(fā)送器更加行為化,而不是把重點(diǎn)放在它門(mén)級(jí)。在軟件編程語(yǔ)言，職能和工作程序分成更具可讀性和易處理，一個(gè)Verilog的功能與任務(wù)是作為相當(dāng)于復(fù)線Verilog代碼,如果某些輸入信號(hào)或某些影響產(chǎn)出或變數(shù).使用的職能和任務(wù),通常發(fā)生在多行代碼都是重復(fù)使用的設(shè)計(jì),從而使得設(shè)計(jì)易于閱讀和維護(hù)肯定，一個(gè)Verilog的功能,可以有多種輸入,但始終只有一個(gè)輸出,雖然Verilog任務(wù)可以兼得多投入,多產(chǎn)出,甚至在某些情況下,非取長(zhǎng)補(bǔ)短，下面顯示了Verilog任務(wù),即擁有所有必要的順序語(yǔ)句,用來(lái)描述發(fā)送器的轉(zhuǎn)移模式。我們可以看到在移位寄存器有2個(gè)標(biāo)志位tag1和tag2，在描述空閑和置位模塊時(shí)產(chǎn)生相同的作用，使用這些Verilog工作,現(xiàn)在我們可以產(chǎn)生一個(gè)容易閱讀的行為模型的空穴傳輸過(guò)程。如果txdoneandtxdatardy都是正確的，進(jìn)入發(fā)送器負(fù)荷模式.接下來(lái)的負(fù)載模式下,進(jìn)入發(fā)送模式轉(zhuǎn)變.，在上升沿的速率時(shí)鐘,內(nèi)容tsr轉(zhuǎn)移到tx輸出.奇偶校驗(yàn)過(guò)程產(chǎn)生于tsr變化中,如下所示。重要的一點(diǎn),就是tsr為零發(fā)生在傳輸過(guò)程，在不同的數(shù)據(jù)傳輸時(shí)標(biāo)志位tag和tsr賦零。傳輸序列的模擬在寫(xiě)上升沿時(shí)數(shù)據(jù)總線容量被鎖存，在下一上升沿txclk，thr的容量載入tsr，低電平開(kāi)始位進(jìn)入tx，發(fā)送標(biāo)志位顯示，thr再次等待新的數(shù)據(jù)的寫(xiě)入。在每個(gè)發(fā)送時(shí)鐘上升沿，tsr的容量被送入tx，在數(shù)據(jù)傳輸過(guò)程中發(fā)生奇偶校驗(yàn)，周期循環(huán)時(shí)奇偶校驗(yàn)為高，tx產(chǎn)生奇偶檢驗(yàn)結(jié)果。接收模塊主控時(shí)鐘mclkx16分頻到合適的波也率時(shí)鐘稱(chēng)為rxclk，它等于mclkx16/16.串行數(shù)據(jù)為收到的rx輸入模塊，要按照UART的數(shù)據(jù)格式顯示為圖3，收到的數(shù)據(jù)格式以并行形式讀出,通過(guò)8位數(shù)據(jù)總線。接收模塊行為描述在連續(xù)發(fā)送時(shí)，發(fā)送保持高，根據(jù)標(biāo)準(zhǔn)異步串行UART，接收器在等待閑置模式的rx輸入要低，在rx下降沿接收進(jìn)入保持模式，現(xiàn)在尋求一種有效的開(kāi)始位等待新的數(shù)據(jù)幀的到來(lái)，當(dāng)有效的開(kāi)始位被檢測(cè)到時(shí)，接收器回到閑置模式，在接收一個(gè)數(shù)據(jù)幀,各種校驗(yàn)和檢查錯(cuò)誤，當(dāng)一個(gè)完整的數(shù)據(jù)幀收到接收端返回待機(jī)模式.，接收器基本運(yùn)作如下所示。接收頻率為mclkx16，和第一上升沿的rxclk常常發(fā)生在中心點(diǎn)開(kāi)始位，如下圖顯示，對(duì)于中心點(diǎn)的起始位與后邊的數(shù)據(jù)字節(jié)，波特率時(shí)鐘是同步。接收器模塊的實(shí)現(xiàn)為了產(chǎn)生一個(gè)易讀易操作的接收器模塊，用兩中Verilog功能來(lái)描述不同的接收方式，當(dāng)接收在空閑狀態(tài)時(shí)，其中一個(gè)Verilog稱(chēng)為空閑復(fù)位，而它需要所有必要的順序語(yǔ)句來(lái)描述接收機(jī)復(fù)位條件。當(dāng)接收器不在復(fù)位狀態(tài)，也不在空閑狀態(tài)下，rx輸入端的采樣數(shù)據(jù)，傳輸?shù)揭莆患拇嫫髦?，在進(jìn)入的數(shù)據(jù)中產(chǎn)生奇偶校驗(yàn)位，另外一個(gè)Verilog稱(chēng)為數(shù)據(jù)移位，需要所有必要的順序語(yǔ)句來(lái)描述上述行為。利用兩個(gè)Verilog實(shí)現(xiàn)上述功能，現(xiàn)在在復(fù)位狀態(tài)，空閑狀態(tài)或者數(shù)據(jù)傳輸狀態(tài)，我們可以產(chǎn)生行為級(jí)描述的接收器，所有上述行為是和接收時(shí)鐘同步的，它們的實(shí)現(xiàn)如下所示。當(dāng)?shù)碗娖介_(kāi)始位到達(dá)rsr[0]時(shí)，一個(gè)完整的數(shù)據(jù)幀將會(huì)給接收到，在下一個(gè)接收時(shí)鐘上升沿到來(lái)是又回到空閑狀態(tài)，當(dāng)返回空閑狀態(tài)時(shí)，接收器顯示數(shù)據(jù)接收準(zhǔn)備，然后數(shù)據(jù)以并行方式讀出，錯(cuò)誤的標(biāo)識(shí)更新，并返回空閑狀態(tài)，在數(shù)據(jù)讀出后清除，在讀下降沿，rhr的容量鎖存在數(shù)據(jù)總線，表8所示接收器各種錯(cuò)誤檢查。接收序列的模擬在連續(xù)傳輸時(shí)線路高通，在rx輸入下降沿，,內(nèi)部rxcnt開(kāi)始計(jì)數(shù)，和mclkx16同步，如果rx輸入在mclkx16的8個(gè)周期循環(huán)，內(nèi)部空閑復(fù)位，接收時(shí)鐘產(chǎn)生使能，和中心低開(kāi)始位同步，在接受時(shí)鐘上升沿，數(shù)據(jù)從RX傳輸?shù)絉SR，當(dāng)?shù)烷_(kāi)始位到底rsr[0]時(shí)，在下一個(gè)接收時(shí)鐘上升沿又被置空閑位，此時(shí)失效，在接收序列，剛好產(chǎn)生rxclk的11個(gè)周期，為采樣一位低開(kāi)始位，一位數(shù)據(jù)位，一位奇偶位，一位置高停止位。在返回空閑狀態(tài)，rsr被置入rhr，內(nèi)部標(biāo)志位更新，接收位產(chǎn)生,rhr容量給讀出，在讀下降沿，rhr應(yīng)用到數(shù)據(jù)總線。硬件描述語(yǔ)言仿真我們現(xiàn)正研究如何HDL可用于行為級(jí)設(shè)計(jì),實(shí)現(xiàn)了數(shù)字UART。在HDL進(jìn)行設(shè)計(jì)的實(shí)施更容易閱讀,并希望能理解,它還規(guī)定,能夠方便的描述依存度之間的各種程序,通常是發(fā)生在這樣一個(gè)復(fù)雜事件驅(qū)動(dòng)系統(tǒng)，例如UART，我們很快將看到這種依靠各種進(jìn)程來(lái)描述的能力對(duì)于實(shí)現(xiàn)模擬是確實(shí)必須的。Verilog語(yǔ)言中的模擬激勵(lì)叫做測(cè)試工具，測(cè)試工具的Verilog模塊,擁有各線路的HDL代碼要生成仿真激勵(lì),而在同一時(shí)間端口影射，這些產(chǎn)生的信號(hào)將會(huì)模擬。端口影射是完成了被異步通用步收發(fā)傳輸器的級(jí)層模塊實(shí)例化頂端水平進(jìn)入測(cè)試工具，如下所示。這使得仿真激勵(lì)適用于輸入的設(shè)計(jì)，同時(shí)檢測(cè)輸出的設(shè)計(jì)，輸入激勵(lì),可以有條件地反應(yīng)與輸出，圖19顯示說(shuō)明如何測(cè)試工具端口影射到UART的頂層。在測(cè)試工具的輸出的傳輸模塊又循環(huán)到接收器的輸入模塊，這使得發(fā)送器模塊用來(lái)作為測(cè)試信號(hào)發(fā)生器接收器模塊，數(shù)據(jù)可以并行的方式向發(fā)送器，同時(shí)回送到輸入的接收機(jī)模塊，收到的數(shù)據(jù)最終從接收器以并行格式讀出，為了盡可能實(shí)現(xiàn)UART的自動(dòng)化測(cè)試，獨(dú)立書(shū)Verilog功能如下，發(fā)送寫(xiě)入功能需要一切必要的聲明來(lái)產(chǎn)生一個(gè)并行的數(shù)據(jù)寫(xiě)序的發(fā)送器，數(shù)據(jù)寫(xiě)入發(fā)送器來(lái)完成寫(xiě)入接收功能，鎖存內(nèi)部測(cè)試工具供以后的分析。接收讀出功能需要一切必要的聲明來(lái)產(chǎn)生一個(gè)并行的數(shù)據(jù)寫(xiě)序的接收器，數(shù)據(jù)讀出接收器來(lái)完成讀出功能，鎖存內(nèi)部測(cè)試工具供以后的分析。數(shù)據(jù)比較功能需要一切必要的聲明來(lái)同先前寫(xiě)入發(fā)送器，相應(yīng)的最新接收數(shù)據(jù)和接收模塊讀出的數(shù)據(jù)比較，如果發(fā)生任何誤差，數(shù)據(jù)比較標(biāo)志一個(gè)從發(fā)送器寫(xiě)出的數(shù)據(jù)定義錯(cuò)誤，相應(yīng)的數(shù)據(jù)也從接收模塊接收和讀出，有任何誤差發(fā)生時(shí)，筆記比較數(shù)據(jù)功能將立即停止模擬仿真。綜合HDL作為設(shè)計(jì)方法比傳統(tǒng)的FPGA設(shè)計(jì)輸入方式如原理圖方式有若干優(yōu)勢(shì)，它同時(shí)規(guī)定了極大的靈活性以與高性能的目標(biāo)裝置的綜合流程，UART綜合流程已針對(duì)兩個(gè)靈活和高性能的可編程邏輯器件FPGA系列，如pASIC-1和pASIC。UART設(shè)計(jì)和模擬的文件進(jìn)入叫做使用HDL語(yǔ)言編輯器的SarosTechnologies的turbow軟件，HDL設(shè)計(jì)合成了快速高效的正確綜合工具，綜合以后，設(shè)計(jì)布局使用spde可編程邏輯工具，在布局之后,UART使用有標(biāo)注的Verilog布局時(shí)序模塊，快速Verilog仿真為來(lái)自Simucad的SilosIII后布局仿真，所有使用過(guò)的工具中可用的工具來(lái)自于快速邏輯。TheserialcontrollerdesignbasedonFPGAIntroductionTheuseofhardwaredescriptionlanguage(HDL)isbecomingamoredominantfactor,whendesigningandverifyingFPGAdesigns.Theuseofbehaviorleveldescriptionnotonlyincreasesthedesignproductivity,butalsoprovidesuniqueadvantagesinthedesignverification.ThemostdominantHDLstodayarecalledVerilogandVHDL.ThisapplicationnotewillillustratetheuseofVerilogindesignandverificationofadigitalUART(UniversalAsynchronousReceiver&Transmitter).DefiningtheUART.TheUARTconsistsoftwoindependentHDLmodules.Onemoduleimplementsthetransmitter,whiletheothermoduleimplementsthereceiver.Thetransmitterandreceivermodulescanbecombinedatthetoplevelofthedesign,foranycombinationsoftransmitterandreceiverchannelsrequired.Datacanbewrittentothetransmitterandreadoutfromthereceiver,allthroughasingle8bitbi-directionalCPUinterface.Addressmappingforthetransmitterandreceiverchannelscaneasilybebuildintotheinterfaceatthetoplevelofthedesign.Bothmodulesshareacommonmasterclockcalledmclkx16.Withineachmodulemclkx16aredivideddowntoindependentbaudrateclocks.UARTfunctionaloverview.AbasicoverviewoftheUARTisshownbelow.Atthelefthandsideisshown“transmitholdregister”,“transmitshiftregister”andthetransmitter“controllogic”block,allcontainedwithinthetransmittermodulecalled“txmit”.Attherighthandsideisshownthe“receiveshiftregister”,“receiveholdregister”andthereceiver“controllogic”block,allcontainedwithinthereceivermodulecalled“rxcver”.Thetwomoduleshaveseparateinputsandoutputsformostoftheircontrollines,onlythebi-directionaldatabus,masterclockandresetlinesaresharedbybothmodules.TheUARTstandarddataformat.Infigure3isshowntheUARTserialdataformat.Serialdataarecontainedwithinframesof8databits,aswellascodedinformationbits.Betweensuccessivetransmissions,thetransmissionlineisheldhigh.Atransmissionisinitializedbyaleadinglowstartbit.Nexttotheleadinglowstartbitcomes8bitsofdatainformation,beginningwiththeLSBandafterwardsrepresentedatincreasingsignificanceorderuptotheMSB.Nexttothe8databitscomestheparitybit,representingtheparityresultofthe8databits.Theparitybitcanbeencodedtruebasedonevenparityoroddparitymode.Nexttotheparitybitcomesatrailinghighstopbitindicatingtheendofadataframe..UARTtimingdiagrams.Belowisshown,howdatawrittentothe“transmitholdregister”getsloadedintothe“transmitshiftregister”,andattherisingedgeofthebaudrateclock,shiftedtotxoutput.Belowisshown,howdatagetsshiftedfromrxinputtothe“receiveshiftregister”,andafterwardsloadedintothe“receiveholdregister”.Finallythereceiverraises“rxrdy”flag.TheTransmittermodule.Themasterclockcalledmclkx16aredivideddowntotheproperbaudratecalledtxclkandequalstomclkx16/16.Datawritteninparallelformattothemodulearelatchedinternally,andshiftedinserialformattothetxoutputatthefrequencyofthebaudrateclock.DatashiftedtothetxoutputfollowstheUARTdataformatshowninfig.3.Behavioraldescriptionofthetransmitter.Thetransmitterwaitsfornewdatatobewrittentothemodule.Whennewdataarewrittenatransmitsequenceisinitialized.Datathatwaswritteninparalleltothemodulegetstransmittedasserialdataframesatthetxoutput.Whennotransmitsequenceareinplace,thetxoutputisheldhigh.Implementationofthetransmittermodule.CreatinglogicinVerilogstartswiththemoduleportdeclaration.Heredefinessignals,thatareportedtoandfromthemodule.Nodirectionarespecifiedatthispoint.Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout(bidirectional),andcanbereferredtointable1.Nexttothespecificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenuseforsequentiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsustodescribethefunctionofthetransmitterinamorebehavioralmanner,ratherthanfocusonit’sactualimplementationatgatelevelInsoftwareprogramminglanguage,functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandtasksasconstructs,analogoustosoftwarefunctionsandprocedures.AVerilogfunctionandtaskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymaintain.AVerilogfunctioncanhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”mode.Wehereseethetwotagbitscalledtag1andtag2concatenatedtothe“transmitshiftregister.Similartaskswerecreatedtodescribethetransmitterin“idle”and“l(fā)oad”modes.ByusingtheseVerilogtasks,wecannowcreateavery“easytoread”behavioralmodeloftheholetransmitprocess.Iftxdoneandtxdatardybotharetrue,thetransmitterenterloadmode.Nexttotheloadmode,thetransmitterentersshiftmode.Attherisingedgeofthebaudrateclock,thecontentsoftsrareshiftedtothetxoutput.Paritygenerationtakesplaceduringshiftingofthetsr,asshownbelow.It’simportanttonote,thatthetsrarezerofilledduringtransmission.Thecombinationofthetwotrailingtagbitsandthezerofilledtsrindicatesthedifferentstatesduringshifting.Paritycycleishighoncyclenexttolastcycle,thatmeanswhentsr[1]getstag2.Txdoneishighwhenshiftingisover,thismeanswhentxgetstag2.Basedonthedifferentstatesduringthetransmissionsequence,“databits”,“paritybit”or“stopbit”areultiplexedtothetxoutput.SimulationofatransmitsequenceThecontentsofthedatabusarelatchedintothrattherisingedgeofwrite.Atthenextrisingedgeoftxclk,thecontentsofthrareloadedintotsr,theactivelowstartbitisassertedtotx,andthetxrdyflagindicates,thatthragainisreadyfornewdatatobewritten.Ateachrisingedgeoftxclk,thecontentsoftsrisshiftedtotx.Paritygenerationtakesplaceduringshiftingofdata.Paritycycleishighonecyclenexttolastcycle,andtxgetstheparityresult.Theinternaltxdoneishighwhenshiftingisover,andtheactivehighstopbitisassertedtotx.ForfurtherdetailsontheimplementationcanbereferredtointhedesignsourcefromTheReceivermodule.Themasterclockmclkx16aredivideddowntotheproperbaudrateclockcalledrxclk,andequalstomclkx16/16.Serialdatatobereceivedattherxinputofthemodule,mustfollowtheUARTdataformatshowninfig.3.Datareceivedinserialformatcanbereadoutinparallelformat,throughthe8bitdatabus.Behavioraldescriptionofthereceiver.Betweensuccessivetransmissions,thetransmissionlineisheldhigh,accordingtostandardUARTbehavior.Thereceiverwaitsin“idle”modefortherxinputtogolow.Atthefallingedgeofrxthereceiverenter“hunting”mode,nowsearchingforavalidstartbitofanewdataframetobereceived.Ifavalidstartbitisdetected,thereceiverenter“shiftdata”mode.Ifaninvalidstartbitisdetected,thereceiverreturnsto“idle”mode.Duringreceiveofadataframe,variousparityanderrorchecksareperformed.Whenacompletedataframehasbeenreceivedthereceiverreturnstoidlemode.Thebasicoperationofthereceiverworksasshownbelow,Thefrequencyofrxclkareequaltomclkx16/16,andthefirstrisingedgeoftherxclkwillalwaysoccuratthecenterpointofthestartbit.Belowisshown,howgenerationofthebaudrateclockrxclkaresynchronizedtothecenterpointsofthestartbitandthefollowingdatabits.Implementationofthereceivermodule.Inordertocreateaneasytoreadandeasytomaintainbehavioralmodelofthereceiver,twoVerilogtasksarewrittentodescribethedifferentmodesofthereceiver.TheVerilogtaskcalled“idle_reset”holdsallnecessarysequentialstatementstodescribethereceiveratresetcondition,andwhenthereceiverisinit’sidlemode.Whenthereceiverisnotatit’sresetcondition,andnotinit’sidlemode,thereceiversamplesdataattherxinput,shiftsthedatatothe“receiveshiftregister”,andgeneratesparitybasedontheincomingdata.TheVerilogtaskcalled“shift_data”holdsallnecessarysequentialstatementstodescribeallaboveactions.UsingthetwoVerilogtasksdescribedabove,wearenowabletocreatethebehavioralleveldescriptionofthereceiveratit’sresetcondition,idlemodeorwhenshiftingindata.Allaboveactionsissynchronoustothebaudrateclockcalledrxclk,andtheimplementationisshownbelow.Acompletedataframehasbeenreceived,whentheleadinglowstartbitreachesrsr[0],andthereceiverreturnstoidlemodeagainatthenextrisingedgeofrxclk.Atreturnto“idle”modethereceiverraisesthe“receivedataready”interrupttoindicate,thatthenewdatareceivednowcanbereadoutinparallelformat.Errorflagsareupdatedaswelluponreturnto“idle”mode,andclearedwhendataarereadoutofthereceiver.Atthefallingedgeofread,thecontentsoftherhrarelatchedtothedatabus.Intable8shownbelowarethevariouserrorcheckssupportedbythereceiver.Simulationofareceivesequence.Betweensuccessivetransmissions,thetransmissionlineisheldhigh.Atthefallingedgeofrxinput,theinternalrxcntstartscountingup,synchronoustomclkx16.Ifrxinputstayslowfor8cyclesofmclkx16,theinternalstatusbitidleisreset,andtherebyenablegenerationofrxclk.Rxclkisnowsynchronizedtothecenterpointofthelowstartbit.Attherisingedgeofrxclk,dataareshiftedfromtherxinputtorsr.Whentheleadinglowstartbitreachrsr[0],thenextrisingedgeofrxclkforcesidlehighagain,andtherebydisablegenerationofrxclk.Duringareceivesequence,exactly11cyclesofrxclkisgenerated,inordertosampleatotalof1leadinglowstartbit,8databits,1paritybitand1trailinghighstopbit.Atreturntoidlemode,thecontentsofrsrareloadedintorhr,thestatusflagsareupdated.Theflag“rxrdy”nowindicates,thatthecontentsofrhrcanbereadout.Atthefallingedgeofread,thecontentsofrhrareappliedtothedatabus.UsingHardwareDescriptionLanguageforSimulation.WehavenowstudiedhowHDLcanbeusedforthebehavioralleveldesignimplementationofadigitalUART.WhileHDLmakethedesignimplementationeasiertoreadandhopefullytounderstandaswell,italsoprovidestheabilitytoeasilydescribedependencyinbetweenvariousprocessesthatusuallyoccurinsuchacomplexeventdrivensystems,asforexampletheUART.Thisabilitytodescribedependencyinbetweenvariousprocessesisextremelyneedforsimulationpurposesaswewillseeverysoon.SimulationstimulusinVerilogHDLiscalleda“testfixture”.Atest-fixtureisaVerilogmodulethatholdsalllinesofHDLcodenecessarytogeneratethesimulationstimulus,whileitatthesametimeportmapsthesesignalstothedesignthataretobesimulated.TheportmappingisdonebyhierarchicalmoduleinstantiationoftheUARTtoplevelmoduleintothetest-fixture,asshownbelow.Thisallowssimulationstimulustobeappliedtotheinputsofthedesign,whilemonitoringtheoutputsofthedesign.Inputstimuluscanbemadeconditionallytotheresponseontheoutputsect.Infig.19shownbelowisillustrated,howthetest-fixtureportmapstothetopleveloftheUART.Withinthetest-fixturethetxoutputofthetransmittermoduleisloopedbacktotherxinputofthereceivermodule.Thisallowsthetransmittermoduletobeusedastestsignalgeneratorforthereceivermodule.Datacanbewritteninparallelformattothetransmittermoduleandloopedbackinserialformattotherxinputofthereceivermodule,anddatareceivedcanfinallybereadoutinparallelformatfromthereceivermodule.InordertoautomatethetestingoftheUARTasmuchaspossible,treeindependentVerilogtaskswerewrittenasfollows.TheVerilogtask“write_to_transmitter”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatawritesequencetothetransmittermodule.Datathatarewrittentothetransmitteruponexecutionofthe“write_to_transmitter”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“read_out_receiver”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatareadoutsequencefromthereceivermodule.Datathatarereadoutofthereceiveruponexecutionofthe“read_out_receiver”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“compare_data”holdsallnecessarystatementsrequiredtocomparethepreviousdatawrittentothetransmittermodule,tothecorrespondingandmostrecentdatareceivedandreadoutfromthereceivermodule.Ifanydiscrepancyoccurs,the“compare_data”taskflagsforanerrorbywritingoutthedatavaluesthatwerewrittentothetransmittermodule,aswellasthecorrespondingdatavaluesthatwerereceivedbyandreadoutfromthereceivermodule.Thesimulationisimmediatelystoppedbythe“compare_data”taskifanydiscrepancyoccurs.BesidesthetreeabovementionedVerilogtasks,thetest-fixtureholdsthestatementstogeneratethemclkx16,themasterresetsignalsaswellasthe“txtorx”loopbackfeature.Thestatementsareconsideredtrivial,andwillnotbeillustratedhere,butcanbereferredtowithinthetest-fixtureitself.Thecoreofthetest-fixtureisabehaviorallevel“forloop”thatexecutesthetreeabovementionedVerilogtasksinordertowriteallpossibledatacombinationstothetransmitterandverifythatsamedatagetsproperlyreceivedbythereceiver.Theforloopisshowedbelowinfigure21.TheaboveshownforloopusestheVerilog“wait”statement.The“wait”statementisaconcurrentprocessstatementthatwaitsforitconditionalexpressiontobecometrue,anhenceinthiscase,theforloopwaitsforthereceivertocompleteanycurrentreceivesequenceindicatedbythe“rxrdy”flagtogohigh.Conceptuallytheexecutionoftheforloopstopsuntil“rxrdy”goeshigh.When“rxrdy”goeshigh,theforloopimmediatelyexecutesthe“read_out_receiver”task,followedbythe“compare_data”task.AccordingtotheUARTdataformatshowedinfig.3,thetest-fixturehavetoprocess256differentdatacombinationtotheUARTinordertotestallpossibledatacombinations.Whentheforloophaveprocessedalldatacombinationswithoutanyerrorflagsfromthe“compare_data”task,thetest-fixturefinallycongratulatesandstops.Infigure22isshownasimulationsequenceusinga2MHzbaudratefrequency,andillustratestheexecutionoftheforloopfromfigure21.1.Dataarewrittentothetransmitteruponexecutionofthewrite_to_transmitter”task.2.Thedatawrittenareautomaticallylatchedintothesignalcalled“data_written[7:0]”attherisingedgeofthewritestrobe.3.Thetxrdyflagindicateswhenthetransmitterisreadyfornewdatatobewritten.4.Attheselectedbaudratethedatawritteninparallelformattothetransmitternowgetstransmittedinserialformatthroughthetxoutput.5.The