AT89C52_外文翻譯.doc

本科畢業(yè)設計（論文）外文翻譯姓 名: 張曉帥 學 號： 200622070230 專 業(yè): 電子信息工程 指導教師: 郭曉東 職 稱: 講師 日 期: 6/16/2010 電子信息工程學院外文資料翻譯譯文AT89S52主要性能l 與MCS-51單片機產品兼容l 8K字節(jié)在系統(tǒng)可編程Flash存儲器l 1000次擦寫周期l 全靜態(tài)操作：0Hz33Hzl 三級加密程序存儲器l 32個可編程I/O口線l 三個16位定時器/計數(shù)器l 八個中斷源l 全雙工UART串行通道l 低功耗空閑和掉電模式l 掉電后中斷可喚醒l 看門狗定時器l 雙數(shù)據(jù)指針l 掉電標識符功能特性描述AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K在系統(tǒng)可編程Flash 存儲器。使用Atmel公司高密度非易失性存儲器技術制造，與工業(yè)80C51產品指令和引腳完全兼容。片上Flash允許程序存儲器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8位CPU和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應用系統(tǒng)提供高靈活、超有效的解決方案。AT89S52具有以下標準功能：8k字節(jié)Flash，256字節(jié)RAM，32位I/O口線，看門狗定時器，2個數(shù)據(jù)指針，三個16位定時器/計數(shù)器，一個6向量2級中斷結構，全雙工串行口，片內晶振及時鐘電路。另外，AT89S52可降至0Hz靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式。空閑模式下，CPU停止工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內容被保存，振蕩器被凍結，單片機一切工作停止，直到下一個中斷或硬件復位為止。引腳結構方框圖VCC : 電源GND : 地P0口：P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅動8個TTL邏輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。當訪問外部程序和數(shù)據(jù)存儲器時，P0口也被作為低8位地址/數(shù)據(jù)復用。在這種模式下，P0具有內部上拉電阻。在flash編程時，P0口也用來接收指令字節(jié)；在程序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。P1口：P1 口是一個具有內部上拉電阻的8位雙向I/O 口，p1 輸出緩沖器能驅動4個TTL 邏輯電平。對P1端口寫“1”時，內部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/計數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。在flash編程和校驗時，P1口接收低8位地址字節(jié)。引腳號第二功能P1.0T2（定時器/計數(shù)器T2的外部計數(shù)輸入），時鐘輸出P1.1T2EX（定時器/計數(shù)器T2的捕捉/重載觸發(fā)信號和方向控制）P1.5MOSI（在系統(tǒng)編程用）P1.6MISO（在系統(tǒng)編程用）P1.7SCK（在系統(tǒng)編程用）P2 口：P2 口是一個具有內部上拉電阻的8 位雙向I/O 口，P2輸出緩沖器能驅動4個TTL 邏輯電平。對P2端口寫“1”時，內部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲器或用16位地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX DPTR）時，P2口送出高八位地址。在這種應用中，P2口使用很強的內部上拉發(fā)送1。在使用8位地址（如MOVX RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器的內容。在flash編程和校驗時，P2口也接收高8位地址字節(jié)和一些控制信號。P3 口：P3口是一個具有內部上拉電阻的8 位雙向I/O 口，p2輸出緩沖器能驅動4個TTL 邏輯電平。對P3端口寫“1”時，內部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內部電阻的原因，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗時，P3口也接收一些控制信號。引腳號第二功能P3.0RXD （串行輸入）P3.1TXD （串行輸出）P3.2(外部中斷0)P3.3 (外部中斷0)P3.4T0 （定時器0外部輸入）P3.5T1 （定時器1外部輸入）P3.6(外部數(shù)據(jù)存儲器寫選通)P3.7(外部數(shù)據(jù)存儲器寫選通)RST: 復位輸入。晶振工作時，RST腳持續(xù)2個機器周期高電平將使單片機復位。看門狗計時完成后，RST腳輸出96個晶振周期的高電平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認狀態(tài)下，復位高電平有效。ALE/：地址鎖存控制信號（ALE）是訪問外部程序存儲器時，鎖存低8位地址的輸出脈沖。在flash編程時，此引腳（）也用作編程輸入脈沖。在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。如果需要，通過將地址為8EH的SFR的第0位置“1”，ALE操作將無效。這一位置“1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時有效。否則，ALE 將被微弱拉高。這個ALE 使能標志位（地址為8EH的SFR的第0位）的設置對微控制器處于外部執(zhí)行模式下無效。:外部程序存儲器選通信號（）是外部程序存儲器選通信號。當 AT89S52從外部程序存儲器執(zhí)行外部代碼時，在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，將不被激活。/VPP:訪問外部程序存儲器控制信號。為使能從0000H 到FFFFH的外部程序存儲器讀取指令，必須接GND。為了執(zhí)行內部程序指令，應該接VCC。在flash編程期間，也接收12伏VPP電壓。XTAL1:振蕩器反相放大器和內部時鐘發(fā)生電路的輸入端。XTAL2:振蕩器反相放大器的輸出端。存儲器結構MCS-51器件有單獨的程序存儲器和數(shù)據(jù)存儲器。外部程序存儲器和數(shù)據(jù)存儲器都可以64K尋址。程序存儲器：如果引腳接地，程序讀取只從外部存儲器開始。對于89S52，如果接VCC，程序讀寫先從內部存儲器（地址為0000H1FFFH）開始，接著從外部尋址，尋址地址為：2000HFFFFH。中斷AT89S52有6個中斷源：兩個外部中斷（和），三個定時中斷（定時器0、1、2）和一個串行中斷。這些中斷每個中斷源都可以通過置位或清除特殊寄存器IE中的相關中斷允許控制位分別使得中斷源有效或無效。IE還包括一個中斷允許總控制位EA，它能一次禁止所有中斷。IE.6位是不可用的。對于AT89S52，IE.5位也是不能用的。用戶軟件不應給這些位寫1。它們?yōu)锳T89系列新產品預留。定時器2可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。程序進入中斷服務后，這些標志位都可以由硬件清0。實際上，中斷服務程序必須判定是否是TF2 或EXF2激活中斷，標志位也必須由軟件清0。定時器0和定時器1標志位TF0 和TF1在計數(shù)溢出的那個周期的S5P2被置位。它們的值一直到下一個周期被電路捕捉下來。然而，定時器2的標志位TF2在計數(shù)溢出的那個周期的S2P2被置位，在同一個周期被電路捕捉下來。參考資料：1ATMEL公司AT89S52的技術手冊2深圳市中源單片機發(fā)展有限公司AT89C52 Datasheets3復旦大學出版社單片微型機原理、應用和實驗張友德等外文原文AT89S52Features Compatible with MCS-51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory 1000 Write/Erase Cycles Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off FlagDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in system programmable Flash on a monolithicchip, the Atmel AT89S52 is a powerful icrocontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following tandard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur -ing program verification.External pullups are required during program veri- fication.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port PinAlternate FunctionsP1.0T2 (external count input to Timer/Counter 2),clock-outP1.1T2EX (Timer/Counter 2 capture/reload trigger and direction control)P1.5MOSI (used for In-System Programming)P1.6MISO (used for In-System Programming)P1.7SCK (used for In-System Programming)Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.Port PinAlternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2(external interrupt 0)P3.3 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)P3.6(external data memory write strobe)P3.7(external data memory read strobe)RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input () during Flash programming.In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in external execution mode.Program Store Enable () is the read strobe to external program memory.When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory./VPP External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be ternally latched on reset. should be strapped to VCC for internal rogram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the nternal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Timer 2 Operating ModesRCLK+TCLKCP/RL2TR2MODE00116-bit Auto-reload01116-bit Capture11Baud Rate Generator0(Off)In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To nsure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port int