EDA技術與VHDL(第2版)習題解答.doc

第3章 VHDL基礎3-1 如圖所示3-2 程序：IF_THEN語句LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux21 S PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( s0,s1,a,b,c,d ) BEGIN IF s1=0 AND s0=0 THEN y=a ; ELSIF s1=0 AND s0=1 THEN y=b ; ELSIF s1=1 AND s0=0 THEN y=c ; ELSIF s1=1 AND s0=1 THEN y=d ; ELSE y=NULL ; END IF ; END PROCESS ; END ARCHITECTURE one ;CASE 語句LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux21 IS PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE two OF mux21 IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;BEGIN s y y y y NULL ; END CASE ; END PROCESS ; END ARCHITECTURE two ;3-3 程序：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MUXK IS PORT ( s0,s1 : IN STD_LOGIC ; a1,a2,a3 : IN STD_LOGIC ; outy : OUT STD_LOGIC ) ; END ENTITY MUXK ; ARCHITECTURE double OF MUXK IS SIGNAL tmp : STD_LOGIC ; -內部連接線 SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ; SIGNAL u2_s, u2_a, u2_b, u2_y : STD_LOGIC ;BEGIN p_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y ) BEGIN CASE u1_s ISWHEN 0 = u1_y u1_y NULL ; END CASE ; END PROCESS p_ MUX21A_u1 ; p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y ) BEGIN CASE u2_s ISWHEN 0 = u2_y u2_y NULL ; END CASE ; END PROCESS p_ MUX21A_u2 ; u1_s= s0 ; u1_a= a2 ; u1_b= a3 ; tmp= u1_y ; u2_s=s1 ; u2_a= a1 ; u2_b= tmp; outy = u2_y ; END ARCHITECTURE double ;3-4 程序：（1）1位半減器1位半減器的設計選用（2）圖，兩種表達方式：一、 LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ; ARCHITECTURE fhd1 OF h_suber ISBEGIN diff=x XOR y ; s_out= ( NOT a ) AND b ; END ARCHITECTURE fhd1 ;二、 LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ; ARCHITECTURE fhd1 OF h_suber IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;BEGIN s s_out =0 ; diff s_out =1 ; diff s_out =0 ; diff s_out =0 ; diff NULL ; END CASE ; END PROCESS ;END ARCHITECTURE fhd1 ;或門邏輯描述：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY or IS PORT ( a,b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY or ; ARCHITECTURE one OF or IS BEGIN cx, y=y, diff=d, s_out=e ) ; u2 : h_suber PORT MAP ( x=d, y=sub_in, diff=diffr, s_out=f ) ; u3 : or PORT MAP ( a=f, b=e, c=sub_out ) ; END ARCHITECTURE fhd1 ;（2）8位減法器：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY 8f_suber IS PORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ;y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ;sub_in : IN STD_LOGIC ; sub_out : OUT STD_LOGIC ;diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ;diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGIC ) ; END ENTITY 8f_suber ;ARCHITECTURE 8fhd1 OF 8f_suber IS COMPONENT f_suber IS PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END COMPONENT f_suber ; SIGNAL a,b,c,d,e,f,g : STD_LOGIC ;BEGIN u0 : f_suber PORT MAP ( x=x0, y=y0, sub_in=, sub_out=a, diff=diff0 ) ; u1 : f_suber PORT MAP ( x=x1, y=y1, sub_in=a, sub_out=b, diff=diff1 ) ; u2 : f_suber PORT MAP (x=x2, y=y2, sub_in=b, sub_out=c, diff=diff2 ) ;u3 : f_suber PORT MAP (x=x3, y=y3, sub_in=c, sub_out=d, diff=diff3 ) ;u4 : f_suber PORT MAP (x=x4, y=y4, sub_in=d, sub_out=e, diff=diff4 ) ;u5 : f_suber PORT MAP (x=x5, y=y5, sub_in=e, sub_out=f, diff=diff5 ) ;u6 : f_suber PORT MAP (x=x6, y=y6, sub_in=f, sub_out=g, diff=diff6 ) ;u7 : f_suber PORT MAP (x=x7, y=y7, sub_in=g, sub_out= sub_out, diff=diff7 ) ; END ARCHITECTURE 8fhd1 ;3-5 程序：或非門邏輯描述：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY nor ISPORT ( d, e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END ENTITY nor ;ARCHITECTURE one OF nor IS BEGIN f b, e=CL, f=a ) ;u1 : DFF1 PORT MAP ( CLK=CLK0, D=a, Q=b ) ;u2 : not PORT MAP ( g=b, h=OUT1 ) ;END ARCHITECTURE one ;3-6 LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MX3256 IS PORT( INA,INB,INCK,INC: IN STD_LOGIC ; E,OUT1: OUT STD_LOGIC) ; END ENTITY MX3256;ARCHITECTURE one OF MX3256 IS COMPONENT LK35 IS PORT ( A1,A2,CLK: IN STD_LOGIC ; O1,O2: OUT STD_LOGIC) ; END COMPONENT LK35; BEGIN3-7LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_unsigned.ALL ;ENTITY CNT IS PORT( CLK,EN,RST,opcode: IN STD_LOGIC ; CQ: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; COUT: OUT STD_LOGIC) ;END ENTITY CNT; ARCHITECTURE behav1 OF CNT IS BEGIN PROCESS( RST,EN,CLK,opcode ) VARIABLE CQI: STD_LOGIC_VECTOR( 15 DOWNTO 0) ; begin IF RST=1 THEN CQI:=( OTHERS=0) ; ELSIF EN=1 THEN IF CLKEVENT AND CLK=1 THEN CASE opcode IS WHEN 0 =CQI:=CQI+1; WHEN 1 =CQI:=CQI-1; WHEN OTHERS =NULL; END CASE; END IF; END IF; CASE opcode IS WHEN 0 = IF CQI=65535 THEN COUT=1; ELSE COUT IF CQI=0 THEN COUT=1; ELSE COUTNULL; END CASE; CQ=CQI; END PROCESS;END behav1;3-83-93-103-113-123-133-14程序1： SIGNAL A,EN : STD_LOGIC ; PROCESS ( A, EN ) VARIABLE B : STD_LOGIC ; BEGIN IF EN = 1 THEN B := A ; END IF ; END PROCESS ;程序2：ARCHITECTURE one OF sample ISBEGINPROCESS ( ) VARIABLE a,b,c : integer range;BEGIN c := a+b ;END PROCESS;END ARCHITECTURE one ;程序3：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux21 IS PORT ( a,b : IN STD_LOGIC ; sel : IN STD_LOGIC ; c : OUT STD_LOGIC ) ;END ENTITY mux21 ;ARCHITECTURE one OF mux21 ISBEGINPROCESS ( ) BEGIN IF sel = 0 THEN c=a ; ELSE c=b ; END IF ;END PROCESS;END ARCHITECTURE one ;第4章 Quartus II使用方法習題4-1 第5章 VHDL狀態(tài)機習題5-1 例5-4（兩個進程）：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MOORE1 IS PORT ( DATAIN : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; CLK,RST : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ; END ENTITY MOORE1 ;ARCHITECTURE behav OF MOORE1 IS TYPE ST_TYPE IS ( ST0,ST1,ST2,ST3,ST4 ) ; SIGNAL C_ST ,N_ST : ST_TYPE ; BEGINREG : PROCESS ( RST ,CLK ) BEGINIF RST=1 THEN C_ST=ST0; Q=”0000”;ELSIF CLK EVENT AND CLK=1 THEN C_ST IF DATAIN = “10” THEN N_ST = ST1 ; ELSE N_ST = ST0 ; END IF ; Q IF DATAIN = “11” THEN N_ST = ST2 ; ELSE N_ST = ST1 ; END IF ; Q IF DATAIN = “01” THEN N_ST = ST3 ; ELSE N_ST = ST0 ; END IF ; Q IF DATAIN = “00” THEN N_ST = ST4 ; ELSE N_ST = ST2 ; END IF ; Q IF DATAIN = “11” THEN N_ST = ST0 ; ELSE N_ST = ST3 ; END IF ; Q N_ST = ST0 ;END CASE ;END PROCESS ;END ARCHITECTURE behav ;5-2 例5-5（單進程）：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MEALY1 IS PORT ( CLK, DATAIN ,RESET : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) ) ; END ENTITY MEALY1 ;ARCHITECTURE behav OF MEALY1 IS TYPE states IS ( st0,st1,st2,st3,st4 ) ; SIGNAL STX : states ; BEGIN PROCESS ( CLK, RESET )BEGIN IF RESET = 1 THEN STX IF DATAIN = 1 THEN STX= st1; Q=”10000” ; ELSE Q IF DATAIN = 0 THEN STX= st2; Q=”10111” ; ELSE QIF DATAIN = 1 THEN STX= st3; Q=”10101” ; ELSE QIF DATAIN = 0 THEN STX= st4; Q=”11011” ; ELSE QIF DATAIN = 1 THEN STX= st0; Q=”11101” ; ELSE Q STX=st0; Q=”00000” ; END CASE ; END PROCESS ;END ARCHITECTURE behav ;5-3 序列檢測器：要求1： 要求2：要求3：5-4 5-5 第6章 16位CISC CPU設計習題6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 第7章 VHDL語句習題7-1 7-2 7-3 7-4 因為每條并行賦值語句在結構體中是同時執(zhí)行的，所以每條并行賦值語句都相當于一條縮寫的進程語句，這條語句的所有輸入信號都被隱性地列入此縮寫進程的敏感信號表中。7-5 7-6 CASE語句、WITH_SELECT語句 ： 共同點：執(zhí)行依賴敏感信號的變化，子句條件選擇值同時測試，因此不允許條件重疊，也不允許條件涵蓋不全； 異同點：CASE語句是順序語句，僅在進程中使用； WITH_SELECT語句是并行語句；7-7 程序：ENTITY - ISPORT ( a, b : IN STD_LOGIC ; c, d : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; next1 : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ;ENTITY - ; ARCHITECTURE behav OF - IS BEGIN Next1 = “1101” WHEN a=0 AND b=1 ELSE d WHEN a=0 ELSE c WHEN b=1 ELSE “1011” ; END ARCHITECTURE behav ; 7-8 程序1：x是信號；程序2：x是變量；第8章 VHDL結構習題8-1 設計實體：獨立的電路功能結構； 實體：設計實體的表層設計單元，是對設計實體與外部電路進行接口描述，是設計實體對外的一個通信界面。8-2 【例7-18】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY andn ISGENERIC ( n : INTEGER ); -定義類屬參量及其數(shù)據類型PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);-用類屬參量限制矢量長度c : OUT STD_LOGIC);END;ARCHITECTURE behav OF andn ISBEGINPROCESS (a)VARIABLE int : STD_LOGIC;BEGINint := 1;FOR i IN aLENGTH - 1 DOWNTO 0 LOOP -循環(huán)語句IF a(i)=0 THEN int := 0;END IF;END LOOP;c 2) -參數(shù)傳遞映射語句，定義類屬變量，n賦值為2PORT MAP (a(0)=d1,a(1)=d2,c=q1);u2: andn GENERIC MAP (n =5) -定義類屬變量，n賦值為5PORT MAP (a(0)=d3,a(1)=d4,a(2)=d5,a(3)=d6,a(4)=d7, c=q2);END;GENERIC說明語句和GENERIC MAP映射語句：便捷、迅速地從外部端口改變元件電路內部參數(shù)或結構規(guī)模。8-3 INOUT ：輸入輸出雙向端口；半雙工； BUFFER ：緩沖端口； 區(qū)別：允許反饋，即，與INOUT模式相比，BUFFER回讀的信號不是由外部輸入的，而是由內部產生、向外輸出的信號。 結論：當前時鐘周期的輸入值來自于上一時鐘周期的輸出值。8-4 重載 ：重名，參數(shù)（返回值）數(shù)據類型不同； 重載函數(shù) ：函數(shù)名相同，參數(shù)的數(shù)據類型不同； 作用：同樣名稱的函數(shù)可以用不同數(shù)據類型的參數(shù)，以便調用時分辨不同功能的同名函數(shù)； 運算符重載函數(shù)： 作用 ：通過重新定義運算符，允許被重載的運算符能夠對新的數(shù)據類型進行操作，或者允許不同的數(shù)據類型之間用此運算符進行運算。8-5 VHDL綜合器支持的類型：STRING、BIT；8-6 【例8-28】LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY decoder3t08 IS port ( input: IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; output: OUT BIT_VECTOR ( 7 DOWNTO 0 ) ) ;END ENTITY decoder3t08 ;ARCHITECTURE behave OF decoder3t08 ISBEGINoutput C,然后再用conv_std_logic_vector( )將C轉換成std_logic_vector類型。LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; PACKAGE STD_LOGIC_UNSIGNED ISFUNCTION “+”( L,R: STD_LOGIC_VECTOR )RETURN STD_LOGIC_VECTOR; END STD_LOGIC_UNSIGNED; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; PACKAGE BODY STD_LOGIC_UNSIGNED ISFUNCTION “+”(L,R: STD_LOGIC_VECTOR; )RETURN STD_LOGIC_VECTOR ISVARIABLE result: INTEGER RANGE 255 TO +255; BEGIN result:=CONV_INTEGER( L ) + CONV_INTEGER( R ); RETURN CONV_STD_LOGIC_VECTOR( result, Llength);END;END STD_LOGIC_UNSIGNED; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE. STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER ISPORT( A,B: IN STD_LOGIC_VECTOR; C: OUT STD_LOGIC_VECTOR); END ENTITY ADDER; ARCHITECTURE behav OF ADDER ISBEGIN C顯式表達； STD ：STANDARD、TEXTIO 無須顯式表達； WORK ：無須顯式表達，總是可見；8-12 8-13 （1）BIT ：枚舉型，值 ：0/1，數(shù)據對象 ：變量、信號， 參與邏輯運算，參與關系運算（=，=/）； BOOLEAN ：枚舉型，值 ：FALSE/TRUE，關系運算符、邏輯運算符獲得； （2）都可以，邏輯操作的基本數(shù)據類型 ：BIT、BOOLEAN、STD_LOGIC及BIT、STD_LOGIC所對應的等長的一維矢量； （3）BOOLEAN類型； （4）BOOLEAN類型；8-14 程序 ：LIBRARY IEEE ; USE - ; USE IEEE.STD_LOGIC_ARITH.ALL ; PACKAGE STD_LOGIC_UNSIGNED ISFUNCTION “ + ” ( L : AGE ; R : INTEGER ) RETURN AGE ; END STD_LOGIC_UNSIGNED ; LIBRARY IEEE ; USE - ; USE IEEE.STD_LOGIC_ARITH.ALL ; PACKAGE BODY STD_LOGIC_UNSIGNED ISFUNCTION “ + ” ( L : AGE