at89c51外文翻譯 外文文獻(xiàn) 英文文獻(xiàn)

AT89C51外文翻譯DESCRIPTIONTHEAT89C51ISALOWPOWER,HIGHPERFORMANCECMOS8BITMICROCOMPUTERWITH4KBYTESOFFLASHPROGRAMMABLEANDERASABLEREADONLYMEMORYPEROMTHEDEVICEISMANUFACTUREDUSINGATMELSHIGHDENSITYNONVOLATILEMEMORYTECHNOLOGYANDISCOMPATIBLEWITHTHEINDUSTRYSTANDARDMCS51INSTRUCTIONSETANDPINOUTTHEONCHIPFLASHALLOWSTHEPROGRAMMEMORYTOBEREPROGRAMMEDINSYSTEMORBYACONVENTIONALNONVOLATILEMEMORYPROGRAMMERBYCOMBININGAVERSATILE8BITCPUWITHFLASHONAMONOLITHICCHIP,THEATMELAT89C51ISAPOWERFULMICROCOMPUTERWHICHPROVIDESAHIGHLYFLEXIBLEANDCOSTEFFECTIVESOLUTIONTOMANYEMBEDDEDCONTROLAPPLICATIONSFEATURESCOMPATIBLEWITHMCS51PRODUCTS4KBYTESOFINSYSTEMREPROGRAMMABLEFLASHMEMORYENDURANCE1,000WRITE/ERASECYCLESFULLYSTATICOPERATION0HZTO24MHZTHREELEVELPROGRAMMEMORYLOCK128X8BITINTERNALRAM32PROGRAMMABLEI/OLINESTWO16BITTIMER/COUNTERSSIXINTERRUPTSOURCESPROGRAMMABLESERIALCHANNELLOWPOWERIDLEANDPOWERDOWNMODESTHEAT89C51PROVIDESTHEFOLLOWINGSTANDARDFEATURES4KBYTESOFFLASH,128BYTESOFRAM,32I/OLINES,TWO16BITTIMER/COUNTERS,AFIVEVECTORTWOLEVELINTERRUPTARCHITECTURE,AFULLDUPLEXSERIALPORT,ONCHIPOSCILLATORANDCLOCKCIRCUITRYINADDITION,THEAT89C51ISDESIGNEDWITHSTATICLOGICFOROPERATIONDOWNTOZEROFREQUENCYANDSUPPORTSTWOSOFTWARESELECTABLEPOWERSAVINGMODESTHEIDLEMODESTOPSTHECPUWHILEALLOWINGTHERAM,TIMER/COUNTERS,SERIALPORTANDINTERRUPTSYSTEMTOCONTINUEFUNCTIONINGTHEPOWERDOWNMODESAVESTHERAMCONTENTSBUTFREEZESTHEOSCILLATORDISABLINGALLOTHERCHIPFUNCTIONSUNTILTHENEXTHARDWARERESETVCCSUPPLYVOLTAGEGNDGROUNDPORT0PORT0ISAN8BITOPENDRAINBIDIRECTIONALI/OPORTASANOUTPUTPORT,EACHPINCANSINKEIGHTTTLINPUTSWHEN1SAREWRITTENTOPORT0PINS,THEPINSCANBEUSEDASHIGHIMPEDANCEINPUTSPORT0MAYALSOBECONFIGUREDTOBETHEMULTIPLEXEDLOWORDERADDRESS/DATABUSDURINGACCESSESTOEXTERNALPROGRAMANDDATAMEMORYINTHISMODEP0HASINTERNALPULLUPSPORT0ALSORECEIVESTHECODEBYTESDURINGFLASHPROGRAMMING,ANDOUTPUTSTHECODEBYTESDURINGPROGRAMVERIFICATIONEXTERNALPULLUPSAREREQUIREDDURINGPROGRAMVERIFICATIONPORT1PORT1ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT1OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT1PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT1PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEINTERNALPULLUPSPORT1ALSORECEIVESTHELOWORDERADDRESSBYTESDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT2PORT2ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT2OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT2PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT2PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEINTERNALPULLUPSPORT2EMITSTHEHIGHORDERADDRESSBYTEDURINGFETCHESFROMEXTERNALPROGRAMMEMORYANDDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE16BITADDRESSESMOVXDPTRINTHISAPPLICATION,ITUSESSTRONGINTERNALPULLUPSWHENEMITTING1SDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE8BITADDRESSESMOVXRI,PORT2EMITSTHECONTENTSOFTHEP2SPECIALFUNCTIONREGISTERPORT2ALSORECEIVESTHEHIGHORDERADDRESSBITSANDSOMECONTROLSIGNALSDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT3PORT3ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT3OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT3PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT3PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEPULLUPSPORT3ALSOSERVESTHEFUNCTIONSOFVARIOUSSPECIALFEATURESOFTHEAT89C51ASLISTEDBELOWPORT3ALSORECEIVESSOMECONTROLSIGNALSFORFLASHPROGRAMMINGANDVERIFICATIONRSTRESETINPUTAHIGHONTHISPINFORTWOMACHINECYCLESWHILETHEOSCILLATORISRUNNINGRESETSTHEDEVICEALE/PROGADDRESSLATCHENABLEOUTPUTPULSEFORLATCHINGTHELOWBYTEOFTHEADDRESSDURINGACCESSESTOEXTERNALMEMORYTHISPINISALSOTHEPROGRAMPULSEINPUTPROGDURINGFLASHPROGRAMMINGINNORMALOPERATIONALEISEMITTEDATACONSTANTRATEOF1/6THEOSCILLATORFREQUENCY,ANDMAYBEUSEDFOREXTERNALTIMINGORCLOCKINGPURPOSESNOTE,HOWEVER,THATONEALEPULSEISSKIPPEDDURINGEACHACCESSTOEXTERNALDATAMEMORYIFDESIRED,ALEOPERATIONCANBEDISABLEDBYSETTINGBIT0OFSFRLOCATION8EHWITHTHEBITSET,ALEISACTIVEONLYDURINGAMOVXORMOVCINSTRUCTIONOTHERWISE,THEPINISWEAKLYPULLEDHIGHSETTINGTHEALEDISABLEBITHASNOEFFECTIFTHEMICROCONTROLLERISINEXTERNALEXECUTIONMODEPSENPROGRAMSTOREENABLEISTHEREADSTROBETOEXTERNALPROGRAMMEMORYWHENTHEAT89C51ISEXECUTINGCODEFROMEXTERNALPROGRAMMEMORY,PSENISACTIVATEDTWICEEACHMACHINECYCLE,EXCEPTTHATTWOPSENACTIVATIONSARESKIPPEDDURINGEACHACCESSTOEXTERNALDATAMEMORYEA/VPPEXTERNALACCESSENABLEEAMUSTBESTRAPPEDTOGNDINORDERTOENABLETHEDEVICETOFETCHCODEFROMEXTERNALPROGRAMMEMORYLOCATIONSSTARTINGAT0000HUPTOFFFFHNOTE,HOWEVER,THATIFLOCKBIT1ISPROGRAMMED,EAWILLBEINTERNALLYLATCHEDONRESETEASHOULDBESTRAPPEDTOVCCFORINTERNALPROGRAMEXECUTIONSTHISPINALSORECEIVESTHE12VOLTPROGRAMMINGENABLEVOLTAGEVPPDURINGFLASHPROGRAMMING,FORPARTSTHATREQUIRE12VOLTVPPXTAL1INPUTTOTHEINVERTINGOSCILLATORAMPLIFIERANDINPUTTOTHEINTERNALCLOCKOPERATINGCIRCUITXTAL2OUTPUTFROMTHEINVERTINGOSCILLATORAMPLIFIEROSCILLATORCHARACTERISTICSXTAL1ANDXTAL2ARETHEINPUTANDOUTPUT,RESPECTIVELY,OFANINVERTINGAMPLIFIERWHICHCANBECONFIGUREDFORUSEASANONCHIPOSCILLATOR,ASSHOWNINFIGURE1EITHERAQUARTZCRYSTALORCERAMICRESONATORMAYBEUSEDTODRIVETHEDEVICEFROMANEXTERNALCLOCKSOURCE,XTAL2SHOULDBELEFTUNCONNECTEDWHILEXTAL1ISDRIVENASSHOWNINFIGURE2THEREARENOREQUIREMENTSONTHEDUTYCYCLEOFTHEEXTERNALCLOCKSIGNAL,SINCETHEINPUTTOTHEINTERNALCLOCKINGCIRCUITRYISTHROUGHADIVIDEBYTWOFLIPFLOP,BUTMINIMUMANDMAXIMUMVOLTAGEHIGHANDLOWTIMESPECIFICATIONSMUSTBEOBSERVEDIDLEMODEINIDLEMODE,THECPUPUTSITSELFTOSLEEPWHILEALLTHEONCHIPPERIPHERALSREMAINACTIVETHEMODEISINVOKEDBYSOFTWARETHECONTENTOFTHEONCHIPRAMANDALLTHESPECIALFUNCTIONSREGISTERSREMAINUNCHANGEDDURINGTHISMODETHEIDLEMODECANBETERMINATEDBYANYENABLEDINTERRUPTORBYAHARDWARERESETITSHOULDBENOTEDTHATWHENIDLEISTERMINATEDBYAHARDWARERESET,THEDEVICENORMALLYRESUMESPROGRAMEXECUTION,FROMWHEREITLEFTOFF,UPTOTWOMACHINECYCLESBEFORETHEINTERNALRESETALGORITHMTAKESCONTROLONCHIPHARDWAREINHIBITSACCESSTOINTERNALRAMINTHISEVENT,BUTACCESSTOTHEPORTPINSISNOTINHIBITEDTOELIMINATETHEPOSSIBILITYOFANUNEXPECTEDWRITETOAPORTPINWHENIDLEISTERMINATEDBYRESET,THEINSTRUCTIONFOLLOWINGTHEONETHATINVOKESIDLESHOULDNOTBEONETHATWRITESTOAPORTPINORTOEXTERNALMEMORYFIGURE1OSCILLATORCONNECTIONSNOTEC1,C230PF10PFFORCRYSTALS40PF10PFFORCERAMICRESONATORSFIGURE2EXTERNALCLOCKDRIVECONFIGURATIONPOWERDOWNMODEINTHEPOWERDOWNMODE,THEOSCILLATORISSTOPPED,ANDTHEINSTRUCTIONTHATINVOKESPOWERDOWNISTHELASTINSTRUCTIONEXECUTEDTHEONCHIPRAMANDSPECIALFUNCTIONREGISTERSRETAINTHEIRVALUESUNTILTHEPOWERDOWNMODEISTERMINATEDTHEONLYEXITFROMPOWERDOWNISAHARDWARERESETRESETREDEFINESTHESFRSBUTDOESNOTCHANGETHEONCHIPRAMTHERESETSHOULDNOTBEACTIVATEDBEFOREVCCISRESTOREDTOITSNORMALOPERATINGLEVELANDMUSTBEHELDACTIVELONGENOUGHTOALLOWTHEOSCILLATORTORESTARTANDSTABILIZEPROGRAMMEMORYLOCKBITSONTHECHIPARETHREELOCKBITSWHICHCANBELEFTUNPROGRAMMEDUORCANBEPROGRAMMEDPTOOBTAINTHEADDITIONALFEATURESLISTEDINTHETABLEBELOWWHENLOCKBIT1ISPROGRAMMED,THELOGICLEVELATTHEEAPINISSAMPLEDANDLATCHEDDURINGRESETIFTHEDEVICEISPOWEREDUPWITHOUTARESET,THELATCHINITIALIZESTOARANDOMVALUE,ANDHOLDSTHATVALUEUNTILRESETISACTIVATEDITISNECESSARYTHATTHELATCHEDVALUEOFEABEINAGREEMENTWITHTHECURRENTLOGICLEVELATTHATPININORDERFORTHEDEVICETOFUNCTIONPROPERLYPROGRAMMINGTHEFLASHTHEAT89C51ISNORMALLYSHIPPEDWITHTHEONCHIPFLASHMEMORYARRAYINTHEERASEDSTATETHATIS,CONTENTSFFHANDREADYTOBEPROGRAMMEDTHEPROGRAMMINGINTERFACEACCEPTSEITHERAHIGHVOLTAGE12VOLTORALOWVOLTAGEVCCPROGRAMENABLESIGNALTHELOWVOLTAGEPROGRAMMINGMODEPROVIDESACONVENIENTWAYTOPROGRAMTHEAT89C51INSIDETHEUSERSSYSTEM,WHILETHEHIGHVOLTAGEPROGRAMMINGMODEISCOMPATIBLEWITHCONVENTIONALTHIRDPARTYFLASHOREPROMPROGRAMMERSTHEAT89C51ISSHIPPEDWITHEITHERTHEHIGHVOLTAGEORLOWVOLTAGEPROGRAMMINGMODEENABLEDTHERESPECTIVETOPSIDEMARKINGANDDEVICESIGNATURECODESARELISTEDINTHEFOLLOWINGTABLETHEAT89C51CODEMEMORYARRAYISPROGRAMMEDBYTEBYBYTEINEITHERPROGRAMMINGMODETOPROGRAMANYNONBLANKBYTEINTHEONCHIPFLASHMEMORY,THEENTIREMEMORYMUSTBEERASEDUSINGTHECHIPERASEMODEPROGRAMMINGALGORITHMBEFOREPROGRAMMINGTHEAT89C51,THEADDRESS,DATAANDCONTROLSIGNALSSHOULDBESETUPACCORDINGTOTHEFLASHPROGRAMMINGMODETABLEANDFIGURES3AND4TOPROGRAMTHEAT89C51,TAKETHEFOLLOWINGSTEPS1INPUTTHEDESIREDMEMORYLOCATIONONTHEADDRESSLINES2INPUTTHEAPPROPRIATEDATABYTEONTHEDATALINES3ACTIVATETHECORRECTCOMBINATIONOFCONTROLSIGNALS4RAISEEA/VPPTO12VFORTHEHIGHVOLTAGEPROGRAMMINGMODE5PULSEALE/PROGONCETOPROGRAMABYTEINTHEFLASHARRAYORTHELOCKBITSTHEBYTEWRITECYCLEISSELFTIMEDANDTYPICALLYTAKESNOMORETHAN15MSREPEATSTEPS1THROUGH5,CHANGINGTHEADDRESSANDDATAFORTHEENTIREARRAYORUNTILTHEENDOFTHEOBJECTFILEISREACHEDDATAPOLLINGTHEAT89C51FEATURESDATAPOLLINGTOINDICATETHEENDOFAWRITECYCLEDURINGAWRITECYCLE,ANATTEMPTEDREADOFTHELASTBYTEWRITTENWILLRESULTINTHECOMPLEMENTOFTHEWRITTENDATUMONPO7ONCETHEWRITECYCLEHASBEENCOMPLETED,TRUEDATAAREVALIDONALLOUTPUTS,ANDTHENEXTCYCLEMAYBEGINDATAPOLLINGMAYBEGINANYTIMEAFTERAWRITECYCLEHASBEENINITIATEDREADY/BUSYTHEPROGRESSOFBYTEPROGRAMMINGCANALSOBEMONITOREDBYTHERDY/BSYOUTPUTSIGNALP34ISPULLEDLOWAFTERALEGOESHIGHDURINGPROGRAMMINGTOINDICATEBUSYP34ISPULLEDHIGHAGAINWHENPROGRAMMINGISDONETOINDICATEREADYPROGRAMVERIFYIFLOCKBITSLB1ANDLB2HAVENOTBEENPROGRAMMED,THEPROGRAMMEDCODEDATACANBEREADBACKVIATHEADDRESSANDDATALINESFORVERIFICATIONTHELOCKBITSCANNOTBEVERIFIEDDIRECTLYVERIFICATIONOFTHELOCKBITSISACHIEVEDBYOBSERVINGTHATTHEIRFEATURESAREENABLEDCHIPERASETHEENTIREFLASHARRAYISERASEDELECTRICALLYBYUSINGTHEPROPERCOMBINATIONOFCONTROLSIGNALSANDBYHOLDINGALE/PROGLOWFOR10MSTHECODEARRAYISWRITTENWITHALL“1”STHECHIPERASEOPERATIONMUSTBEEXECUTEDBEFORETHECODEMEMORYCANBEREPROGRAMMEDREADINGTHESIGNATUREBYTESTHESIGNATUREBYTESAREREADBYTHESAMEPROCEDUREASANORMALVERIFICATIONOFLOCATIONS030H,031H,AND032H,EXCEPTTHATP36ANDP37MUSTBEPULLEDTOALOGICLOWTHEVALUESRETURNEDAREASFOLLOWS030H1EHINDICATESMANUFACTUREDBYATMEL031H51HINDICATES89C51032HFFHINDICATES12VPROGRAMMING032H05HINDICATES5VPROGRAMMINGPROGRAMMINGINTERFACEEVERYCODEBYTEINTHEFLASHARRAYCANBEWRITTENANDTHEENTIREARRAYCANBEERASEDBYUSINGTHEAPPROPRIATECOMBINATIONOFCONTROLSIGNALSTHEWRITEOPERATIONCYCLEISSELFTIMEDANDONCEINITIATED,WILLAUTOMATICALLYTIMEITSELFTOCOMPLETIONALLMAJORPROGRAMMINGVENDORSOFFERWORLDWIDESUPPORTFORTHEATMELMICROCONTROLLERSERIESPLEASECONTACTYOURLOCALPROGRAMMINGVENDORFORTHEAPPROPRIATESOFTWAREREVISIONFLASHPROGRAMMINGANDVERIFICATIONWAVEFORMSHIGHVOLTAGEMODEVPP12VFLASHPROGRAMMINGANDVERIFICATIONWAVEFORMSLOWVOLTAGEMODEVPP5VFLASHPROGRAMMINGANDVERIFICATIONCHARACTERISTICSTA0CTO70C,VCC5010ABSOLUTEMAXIMUMRATINGSNOTICESTRESSESBEYONDTHOSELISTEDUNDER“ABSOLUTEMAXIMUMRATINGS”MAYCAUSEPERMANENTDAMAGETOTHEDEVICETHISISASTRESSRATINGONLYANDFUNCTIONALOPERATIONOFTHEDEVICEATTHESEORANYOTHERCONDITIONSBEYONDTHOSEINDICATEDINTHEOPERATIONALSECTIONSOFTHISSPECIFICATIONISNOTIMPLIEDEXPOSURETOABSOLUTEMAXIMUMRATINGCONDITIONSFOREXTENDEDPERIODSMAYAFFECTDEVICERELIABILITYDCCHARACTERISTICSTA40CTO85C,VCC50V20UNLESSOTHERWISENOTEDNOTES1UNDERSTEADYSTATENONTRANSIENTCONDITIONS,IOLMUSTBEEXTERNALLYLIMITEDASFOLLOWSMAXIMUMIOLPERPORTPIN10MAMAXIMUMIOLPER8BITPORTPORT026MAPORTS1,2,315MAMAXIMUMTOTALIOLFORALLOUTPUTPINS71MAIFIOLEXCEEDSTHETESTCONDITION,VOLMAYEXCEEDTHERELATEDSPECIFICATIONPINSARENOTGUARANTEEDTOSINKCURRENTGREATERTHANTHELISTEDTESTCONDITIONS2MINIMUMVCCFORPOWERDOWNIS2VACCHARACTERISTICSUNDEROPERATINGCONDITIONS,LOADCAPACITANCEFORPORT0,ALE/PROG,ANDPSEN100PFLOADCAPACITANCEFORALLOTHEROUTPUTS80PFEXTERNALPROGRAMANDDATAMEMORYCHARACTERISTICSEXTERNALPROGRAMMEMORYREADCYCLEEXTERNALDATAMEMORYREADCYCLEEXTERNALDATAMEMORYWRITECYCLEEXTERNALCLOCKDRIVEWAVEFORMSEXTERNALCLOCKDRIVESERIALPORTTIMINGSHIFTREGISTERMODETESTCONDITIONSVCC50V20LOADCAPACITANCE80PFSHIFTREGISTERMODETIMINGWAVEFORMSACTESTINGINPUT/OUTPUTWAVEFORMS1NOTE1ACINPUTSDURINGTESTINGAREDRIVENATVCC05VFORALOGIC1AND045VFORALOGIC0TIMINGMEASUREMENTSAREMADEATVIHMINFORALOGIC1ANDVILMAXFORALOGIC0FLOATWAVEFORMS1NOTE1FORTIMINGPURPOSES,APORTPINISNOLONGERFLOATINGWHENA100MVCHANGEFROMLOADVOLTAGEOCCURSAPORTPINBEGINSTOFLOATWHEN100MVCHANGEFROMTHELOADEDVOH/VOLLEVELOCCURSAT89C51中文原文AT89C51是美國ATMEL公司生產(chǎn)的低電壓，高性能CMOS8位單片機(jī)，片內(nèi)含4KBYTES的可反復(fù)擦寫的只讀程序存儲(chǔ)器（PEROM）和128BYTES的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（RAM），器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS51指令系統(tǒng)，片內(nèi)置通用8位中央處理器（CPU）和FLASH存儲(chǔ)單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)合，可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù)與MCS51產(chǎn)品指令系統(tǒng)完全兼容4K字節(jié)可重擦寫FLASH閃速存儲(chǔ)器1000次擦寫周期全靜態(tài)操作0HZ24MHZ三級(jí)加密程序存儲(chǔ)器1288字節(jié)內(nèi)部RAM32個(gè)可編程IO口線2個(gè)16位定時(shí)計(jì)數(shù)器6個(gè)中斷源可編程串行UART通道低功耗空閑和掉電模式功能特性概述AT89C51提供以下標(biāo)準(zhǔn)功能4K字節(jié)FLASH閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32個(gè)IO口線，兩個(gè)16位定時(shí)計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C51可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。引腳功能說明VCC電源電壓GND地P0口P0口是一組8位漏極開路型雙向IO口，也即地址數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。在FIASH編程時(shí)，P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。P1口P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向IO口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。FIASH編程和程序校驗(yàn)期間，P1接收低8位地址。P2口P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向IO口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVXDPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVXRI指令）時(shí)，P2口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的內(nèi)容），在整個(gè)訪問期間不改變。FLASH編程或校驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào)。P3口P3口是一組帶有內(nèi)部上拉電阻的8位雙向IO口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)P3口寫入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí)，被外部拉低的P3口將用上拉電阻輸出電流（IIL）。P3口除了作為一般的IO口線外，更重要的用途是它的第二功能，如下表所示P3口還接收一些用于FLASH閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。RST復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。ALEPROG當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE仍以時(shí)鐘振蕩頻率的L6輸出固定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖。對(duì)FLASH存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的DO位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。PSEN程序儲(chǔ)存允許（PSEN）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器，這兩次有效的PSEN信號(hào)不出現(xiàn)。EAVPP外部訪問允許。欲使CPU僅訪問外部程序存儲(chǔ)器（地址為0000HFFFFH），EA端必須保持低電平（接地）。需注意的是如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。FLASH存儲(chǔ)器編程時(shí)，該引腳加上12V的編程允許電源VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。XTAL1振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸入端。XTAL2振蕩器反相放大器的輸出端。時(shí)鐘振蕩器AT89C5L中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體（或陶瓷諧振器）及電容C1、C2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對(duì)外接電容C1、C2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30PF10PF，而如使用陶瓷諧振器建議選擇40PF10F。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖5右圖所示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。由于外部時(shí)鐘信號(hào)是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求?？臻e節(jié)電模式AT89C51有兩種可用軟件編程的省電模式，它們是空閑模式和掉電工作模式。這兩種方式是控制專用寄存器PCON（即電源控制寄存器）中的PD（PCON1）和IDL（PCON0）位來實(shí)現(xiàn)的。PD是掉電模式，當(dāng)PD1時(shí)，激活掉電工作模式，單片機(jī)進(jìn)入掉電工作狀態(tài)。IDL是空閑等待方式，當(dāng)IDL1，激活空閑工作模式，單片機(jī)進(jìn)入睡眠狀態(tài)。如需同時(shí)進(jìn)入兩種工作模式，即PD和IDL同時(shí)為1，則先激活掉電模式。在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激活，IDL（PCON0）被硬件清除，即刻終止空閑工作模式。程序會(huì)首先響應(yīng)中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序并緊隨RETI（中斷返回）指令后，下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入空閑模式那條指令后面的一條指令。其二是通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是，當(dāng)由硬件復(fù)位來終止空閑工作模式時(shí)，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期（24個(gè)時(shí)鐘周期）有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM，而允許訪問其它端口。為了避免可能對(duì)端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對(duì)端口或外部存儲(chǔ)器的寫入指令。掉電模式在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。空閑和掉電模式外部引腳狀態(tài)程序存儲(chǔ)器的加密AT89C51可使用對(duì)芯片上的3個(gè)加密位LB1、LB2、LB3進(jìn)行編程（P）或不編程（U）來得到如下表所示的功能加密位保護(hù)功能表注表中的U表示未編程，P表示編程當(dāng)加密位LB1被編程時(shí)，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒有復(fù)位，則鎖存起的初始值是一個(gè)隨機(jī)數(shù)，且這個(gè)隨機(jī)數(shù)會(huì)一直保存到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。FLASH閃速存儲(chǔ)器的編程AT89C51單片機(jī)內(nèi)部有4K字節(jié)的FLASHPEROM，這個(gè)FLASH存儲(chǔ)陣列出廠時(shí)已處于擦除狀態(tài)（即所有存儲(chǔ)單元的內(nèi)容均為FFH），用戶隨時(shí)可對(duì)其進(jìn)行編程。編程接口可接收高電壓（12V）或低電壓（VCC）的允許編程信號(hào)。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。AT89C51單片機(jī)中，有些屬于低電壓編程方式，而有些則是高電壓編程方式，用戶可從芯片上的型號(hào)和讀取芯片內(nèi)的名字節(jié)獲得該信息，見下表。AT89C51的程序存儲(chǔ)器陣列是采用字節(jié)寫入方式編程的，每次寫入一個(gè)字節(jié)，要對(duì)整個(gè)芯片內(nèi)的PEROM程序存儲(chǔ)器寫入一個(gè)非空字節(jié)，必須使用片擦除的方式將整個(gè)存儲(chǔ)器的內(nèi)容清除。編程方法編程前，須按表6和圖6所示設(shè)置好地址、數(shù)據(jù)及控制信號(hào)。編程單元的地址加在P1口和P2口的P20P23（11位地址范圍為0000H0FFFH），數(shù)據(jù)從P0口