仿真設(shè)計舉例

1、1. 4位加法器的ModelSim 仿真設(shè)計新建一個名為adder4,v的源文件，源代碼如下：module adder4(COUT,SUM,A,B,CIN);input3:0 A,B;input CIN;output3:0 SUM;output COUT;assign COUT,SUM=A+B+CIN;endmodule接下來需要編寫4位加法器的測試文件test_adder4.v 源代碼如下：/timescale 1ns/1nsmodule test_adder4;wire3:0 SUM;wire COUT;reg3:0 A,B;reg CIN;initial begin A=4; B=2;

2、CIN=1; #100 A=12; B=8; CIN=0; #100 A=10; B=8; CIN=0;endadder4 m( .COUT(COUT), .SUM(SUM), .A(A), .B(B), .CIN(CIN);endmodule2. 十進制計數(shù)器的ModelSim 仿真設(shè)計counter_10源代碼如下：module counter_10(clk,clr,c,out);input clk,clr;output c;output 3:0 out;reg c;reg 3:0 out;always(posedge clk or negedge clr) begin if(!clr)

3、begin out3:0=0; c=0; end else begin if(out3:0= =9) begin c=1; out3:0=0; end else begin out3:0= out3:0+1; c=0; end endendendmodulecounter_10_tp.v是testbench文件，用來測試驗證十進制計數(shù)器，代碼如下：timescale 1ns/1nsmodule counter_10_tp;reg clk,clr;wire cout;wire 3:0 cnterout;counter_10 counter10(. clk(clk), . clr(clr) , .

4、 c(cout), . out(cnterout);always #5 clk=clk; initial begin clk=0; clr=0;#10 clr=1;#30 clr=0;#40 clr=1;#2000 $stop;endendmodule3. Quartus 8.0新建一個工程， 然后編寫兩個文件如下： 頂層文件 “count4.v”源碼為：module count4(clk,reset,out); /4位計數(shù)器模塊 input clk,reset; output3:0 out; reg3:0 out; always (posedge clk) begin if (reset)

5、out=0; else out=out+1; endendmoduleModelSim仿真用到的測試文件“count_tp.v”源碼為：（注意，該文件不加入工程中）timescale 1ns/1ns /定義時延單位1ns和時延精度為1ns（即精確到1ns）module count_tp; /測試模塊 reg clk,reset; /輸入激勵信號定義為reg型 wire3:0 out; /輸出信號定義為wire型 parameter DELY=100; count4 mycount(.clk(clk),.reset(reset),.out(out); /調(diào)用測試對象count4 always #

6、(DELY/2) clk=clk; /產(chǎn)生時鐘波形 initial /激勵波形定義 begin clk=0; reset=0; #DELY reset=1; #DELY reset=0; #(DELY*20) $finish; end initial $monitor($time,clk=%d reset=%d out=%d,clk,reset,out);/結(jié)果顯示endmodule4. 簡單的測試設(shè)計實例化用戶設(shè)計，然后提供相應(yīng)的激勵。測試輸出被圖形化顯示在仿真器的波形窗口里或者作為文本發(fā)送到用戶的終端或者是管道輸出文本。以下是一個簡單的用Verilog實現(xiàn)的設(shè)計，它實現(xiàn)了一個移位寄存器的功

7、能。module shift_reg (clock, reset, load, sel, data, shiftreg);input clock;input reset;input load;input 1:0 sel;input 4:0 data;output 4:0 shiftreg;reg 4:0 shiftreg;always (posedge clock)beginif (reset)shiftreg = 0;else if (load)shiftreg = data;elsecase (sel)2b00 : shiftreg = shiftreg;2b01 : shiftreg =

8、 shiftreg 1;default : shiftreg = shiftreg;endcaseendendmodule 以下是簡單的測試設(shè)計示例移位寄存器設(shè)計的例子,verilog描述。 module testbench; / declare testbench namereg clock;reg load;reg reset; / declaration of signalswire 4:0 shiftreg;reg 4:0 data;reg 1:0 sel;/ instantiation of the shift_reg design belowshift_reg dut(.clock

9、 (clock),.load (load),.reset (reset),.shiftreg (shiftreg),.data (data),.sel (sel);/this process block sets up the free running clockinitial beginclock = 0;forever #50 clock = clock;endinitial begin/ this process block specifies the stimulus.reset = 1;data = 5b00000;load = 0;sel = 2b00;#200reset = 0;

10、load = 1;#200data = 5b00001;#100sel = 2b01;load = 0;#200sel = 2b10;#1000 $stop;endinitial begin/ this process block pipes the ASCII results to the/terminal or text editor$timeformat(-9,1,ns,12);$display( Time Clk Rst Ld SftRg Data Sel);$monitor(%t %b %b %b %b %b %b, $realtime,clock, reset, load, shiftreg, data, sel);endendmodule以上的測試設(shè)計實例化設(shè)計，設(shè)置時鐘，提供激勵信號。所有的進程塊在