數(shù)字集成電路英文課件：Chapter 2 MOS Transistors

1、Faculty of Materials and Energy, Guangdong University of Technology Chapter 2: MOS Transistors 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 2 Outline v Introduction v Structure and Operation of the MOS Transistor v Threshold voltage of the MOS transistor v First-order

2、Current-Voltage Characteristics v Derivation of Velocity-Saturated Current Equations v Subthreshold Condition v Capacitance of the MOS transistor 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 3 2.1 Introduction v As the transistor scaling, MOS VLSI circuits make up a do

3、minant percentage of the total market for digital ICs. v Years- v PMOS- NMOS- CMOS v The great advantage of CMOS digital circuits is that they maybe designed with low static power consumption in the steady stage condition, but it also increase in fabrication complexity and chip area compared to basi

4、c NMOS. v The contents in this chapter: Structure and operation of the MOS transistor Calculation of threshold voltage Current equation Capacitance of the MOS transistor 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 4 2.2 Structure and Operation of the MOS Transistor -1

5、 v The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a voltage controlled device. This means that a voltage at the gate control the current flows from the drain to the source. v Four terminals: gate/G, drain/D, source/S, bulk/B (body or substrate) G: metal (early technology) or ploy-

6、Si (heavily doped to keep its resistance low), controlled the formation of a conducting channel D/S: heavily doped to achieve Ohmic contact within metal electrode. The structure is symmetrical, one cannot distinguish between the source and drain of an unbiased device. B (NMOS): connected to the lowe

7、st potential, typically GND, to keep the BD/BS pn+ junction reverse-biased. 2021-5-15 Digital Integrated Circuits 5 2.2 Structure and Operation of the MOS Transistor -2 v Two Simple operation modes: On and Off. Determined by the gate voltage v In the off condition, no current flows in the device v I

8、n the on condition, electron current flows from source to drain A voltage is applied to the gate node to set up an electric field that creates a conductive channel between source and drain regions, and current flows when a potential difference exists between two nodes. Faculty of Materials and Energ

9、y, GDUT 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 6 2.2 Structure and Operation of the MOS Transistor -3 v Important device dimension parameters: Channel length/L: typically in the range of 350nm and 22nm, this dimension will continue to scale according to Moores la

10、w Channel width/W: typically much larger than the minimum length, depending on the desired current handling capability Gate oxide thickness/Tox: typically less than 5nm, it determines the vertical electrical field and hence the device currents, but limited by the device reliability, e.g. breakdown v

11、oltage Junction depth/xj: 70- 150nm, to calculate the junction capacitance Thickness of the depletion layer thickness/xd: to calculate the threshold voltage 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 7 2.2 Structure and Operation of the MOS Transistor -4 v The silico

12、n surface is comprised of active and field regions. Active region: device (or transistor). It should be defined in the layout design. Field region: it serves to isolate transistors. A thick layer of silicon dioxide over the field regions is to minimize unwanted capacitance from interconnecting metal

13、 to the body and limit the current of parasitic transistors. 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 2.3 Threshold voltage of the MOS transistor -1 v Definition of threshold voltage: v VT is defined as the applied gate voltage required to create the inversion laye

14、r charge. (The electron concentration at the surface is the same as the hole concentration in the bulk material) v VT is defined as the applied gate voltage required to achieve the threshold inversion point. The threshold inversion point is defined as the condition when the surface potential is ?s=2

15、?fp for p-type semiconductor and ?s=2?fn for n-type semiconductor. 8 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 9 2.3 Threshold voltage of the MOS transistor -2 v The three main terms of threshold voltage are: The difference in work functions between the gate materia

16、l and the silicon substrate on the channel side. The positive charge Qox present in the oxide and the interface between the oxide and the bulk silicon. It contributes a negative quantity to the threshold voltage of Qox/Cox. v The flat-band voltage: A voltage at the gate produces flat energy bands in

17、 the MOS system. GCG gateC substrate / fbGCoxox VQC 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 10 2.3 Threshold voltage of the MOS transistor -3 v The three main terms of threshold voltage are: A gate voltage (-2F-QB/Cox) is needed to change the surface potential to

18、the strong inversion condition and to offset the induced depletion- layer charge QB. v The threshold voltage can be calculated by: v Where: 0 2/2/ TGCFBoxoxoxGCFBoxoxox VQCQCQCQC 1/2 2 2 sisF BAdAAsisF A QqN XqNqN qN 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 11 2.3

19、Threshold voltage of the MOS transistor -4 v As Vb becomes more negative, more holes are attracted to the substrate connection, leaving a larger negative charge behind. v The threshold voltage is a function of the total charge in the depletion region because the gate charge must mirror QB before an

20、inversion layer is formed. Thus, as VB drops and QB increase, VT also increases. This is the body effect or the back gate effect. 0 2/ TGCFBoxoxox VQCQC 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 12 2.3 Threshold voltage of the MOS transistor -5 v For body effect to

21、manifest itself, the bulk potential need not change; if the source voltage varies with respect to bulk potential, the same phenomenon occurs. 0 00 00 0 0 22 22 2/ 2/ 2222/ 22 1 2 BAsiF BAsiSBF TGCFBoxoxox TGCFBoxoxox TBB TAsiSBFAsiFox TSBFF Asi ox QqN QqNV VQCQC VQCQC VQQ VqNVqNC VV qN C 2021-5-15 D

22、igital Integrated Circuits Faculty of Materials and Energy, GDUT 13 2.3 Threshold voltage of the MOS transistor -6 v Problem: A 130nm technology employs carrier concentrations in the p-well in the range of 31017cm-3. Estimate the degree of band-bending required for strong inversion at room temperatu

23、re, relative to the flat-band condition. 10 17 21.45 10 2ln2 0.026ln0.88 3 10 i FP nKT V qp 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 14 2.3 Threshold voltage of the MOS transistor -7 v Problem: A P-type well in a 130nm technology has NA= 31017cm-3. Find the limitin

24、g value of depletion-layer width and the total charge contained in the depletion region. 10 17 1/2 14 6 1917 1917672 21.45 10 22ln2 0.026ln0.88 3 10 2 2 11.7 8.85 100.88 6 1060 1.6 103 10 21.6 103 106 103 10/ i sFFPFP sisF d A BAd AsisF nKT V qp X qN cmnm QqN X qNcmC cm 2021-5-15 Digital Integrated

25、Circuits Faculty of Materials and Energy, GDUT 15 2.3 Threshold voltage of the MOS transistor -8 v Problem: Determine values of Cox and , if tox=2.2nm and NA= 31017cm-3. 14 62 1917146 1/2 4 4 8.85 10/ 1.6 10/ 2.2 2/ 2 1.6 103 1011.78.85 10/1.6 10 0.2 oxo ox ox ox siAox F cm CF cm tnm qNC V 2021-5-15

26、 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 16 2.3 Threshold voltage of the MOS transistor -9 v Problem: Calculate the zero-bias threshold voltage for an NMOS silicon- gate transistor that has well doping NA= 31017cm-3, gate doping ND= 1020cm-3, gate oxide thickness tox=2.2nm,

27、 and 21010cm-2 singly charged positive ions per unit area at the oxide silicon interface. 00 10 17 () 1362 72 0 76 0 2/ 1.45 10 ln0.026ln0.44 3 10 0.440.550.99 43.5 10/, 1.6 10/ 223 10/ /3 10/ 1.6 100.1 TGCFBoxoxox i FP GCFPG gate oxoox BAsiF Box VQCQC nKT V qp V F cmCF cm QqNC cm QC 10196 00 88 /2

28、101.6 10/ 1.6 100.002 2/ 0.990.880.1880.0020.08 oxox TGCFBoxoxox V QCV VQCQC V 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 17 2.3 Threshold voltage of the MOS transistor -10 v The breakdown voltage and junction capacitance maybe affected by the variation of doping con

29、centration in the gate and oxide capacitance. v The value of threshold voltage is determined by ion implanting dopant atoms into the channel region. A p-type threshold implant (boron) will make the threshold voltage more positive. A N-type threshold implant (phosphorus) will make the threshold volta

30、ge more negative. v Problem: Calculation of threshold voltage implant dosage. 12 192 0.40.08 3.2 10 1.6 10 ox iox i CQCVions N qqcm 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 18 2.4 First-order Current-Voltage Characteristics-1 Digital Integrated Circuits Faculty of

31、Materials and Energy, GDUT 18 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 19 2.4 First-order Current-Voltage Characteristics-2 v The current flows through a semiconductor bar can be described as : v Qn: charge density along the direction of current v V: velocity of th

32、e charge n IQv W 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 20 2.4 First-order Current-Voltage Characteristics-3 v The charge density can be calculated by: v Cox: Capacitance of gate oxide per unit area v Tox: thickness of gate oxide v V(y): channel potential at y no

33、xGST QyCVVV y / oxoxox Ct / ds V yVy L 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 21 2.4 First-order Current-Voltage Characteristics-4 v If VdsVgs-VT, the device is operated in the triode region. v Vgs-VT: overdrive voltage W/L: aspect ratio / n noxGST nn IQv W QyCVV

34、V y vEdV ydy / DSoxGST oxGSTn IWCVVV yv WCVVV ydV ydy 00 ds DSoxGSTn LV DSoxGSTn IdyWCVVV ydV y IdyWCVVV ydV y 2 2 1 2 1 2 DSnoxGSTdsds GSTdsds W ICVVVV L kVVVV 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 22 2.4 First-order Current-Voltage Characteristics-5 2 1 2 dsno

35、xGSTdsds W ICVVVV L dsnoxGSTds W ICVVV L 1 ds on ds noxGST V R W I CVV L If Vds2(Vgs-VT), then The MOSFET is operated as a resistor whose value is controlled by the overdrive voltage. With the condition VdsVgs-VT, Ids becomes relatively constant and we define the device is operated in the saturation

36、 region. v Why? v The density of inversion layer charge is proportional to Vgs-V(y)-VT. If channel potential V(y) approaches Vgs-VT, then Qn(y) drops to zero and the channel is pinch off. As Vds increase further, the point at which Qn equals to zero gradually moves toward the source. 2021-5-15 Digit

37、al Integrated Circuits Faculty of Materials and Energy, GDUT 24 2.4 First-order Current-Voltage Characteristics-7 v The I-V equation of MOSFET in the saturation region can be derived as: 00 ds LV dsoxGSTn I dyWCVVV ydV y 000 0 0 0 ds gsth ds gsth gsth LLLL dsdsdsds L V oxGSTn VV oxGSTn V oxGSTn VV V

38、V oxGSTn I dyI dyI dyI dy WCVVV ydV y WCVVV ydV y WCVVV ydV y WCVVV ydV y 2 1 2 dsnoxGST W ICVV L In the long channel devices, the saturated MOSFET can be used as a current source connected between the drain and source. The current is controlled by the overdrive voltage. 2021-5-15 Digital Integrated

39、 Circuits Faculty of Materials and Energy, GDUT 25 Design of Analog CMOS Integrated Circuits DME, GDUT 25 2.4 First-order Current-Voltage Characteristics-8 As the device is operated in the saturation region, the actual length of the inverted channel gradually decreases as the potential difference be

40、tween the gate and the drain increases. In other words, L is in fact as a function of Vds. This effect is defined as channel length modulation. Channel length modulation is more significant in the short channel devices and can be ignored in the long channel devices. 22 2 2 111/ / 1 2 1 1 2 ds dsnoxG

41、Sth noxGSthds LLL LLL L LLLLLL L LV W ICVV L W CVVV L 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 26 2.5 Velocity-Saturated Current Equations-1 v In the long channel devices, saturation occurs when Vds=Vgs-VT v In the deep submicron devices, saturation occurs when the

42、 carriers reach velocity saturationthat is, when they reach the speed limit of the carriers in silicon. v Velocity saturation is due to the high horizontal and vertical fields. n IQv W n vE 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 27 2.5 Velocity-Saturated Current

43、Equations-2 v The vertical field can be approximated as Ex=VGS-VT/tox. v For high gate voltages, a large number of mobile carriers are induced in the inversion layer near the interface. The mobility of these carriers decreases due primarily to electron scattering caused by dangling bonds at the Si-S

44、iO2 interface. The effect of the vertical field on mobility can be modeled as: 0 1 e GST ox VV t v The vertical field (5.5106V/cm) is very large than the horizontal field (1.2105V/cm), and the effective mobility is reduced by a factor of 2 relative to the nominal mobility in the presence of low fiel

45、ds. (NMOS:540-270cm2/V-s) 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 28 2.5 Velocity-Saturated Current Equations-3 v The horizontal field is given by Ey=VDS/L v The horizontal field acts to push the carriers to their velocity limit and this cause early saturation. v

46、The horizontal field acts to reduce the mobility. As Ey goes up, the carriers continue to increase in speed. Actually their velocity saturates a limit at approximately vsat=107cm/s. 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 29 2.5 Velocity-Saturated Current Equation

47、s-4 initially, as Ey increase, the carrier velocity also increases, the mobility is keep constant. The field increase beyond a certain critical electrical field, EC, the carrier velocity saturates at its limit in silicon. The horizontal fields are so high in DSM devices that they tend to saturate ve

48、ry quickly as VDS increases. v The horizontal field is given by Ey=VDS/L v The horizontal field acts to push the carriers to their velocity limit and this cause early saturation. v The horizontal field acts to reduce the mobility. As Ey goes up, the carriers continue to increase in speed. Actually t

49、heir velocity saturates a limit at approximately vsat=107cm/s. 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 30 2.5 Velocity-Saturated Current Equations-5 v The saturation velocity for both electrons and holes is 8106cm/s at T=400K. The critical field values are: v T=30

50、0K, vsat=107cm/s 4 4 6 10/ Electrons 24 10/ Holes cn cp EV cm EV cm 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 31 2.5 Velocity-Saturated Current Equations-6 v The horizontal electric field, Ey, can be expressed as: 1/ y eyc yc satyc E vEE EE vvEE 21/1/ 2 y cec satee

51、ycyc sat c e E EE v EEEE v E 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 32 2.5 Velocity-Saturated Current Equations-7 v Current equations for velocity-saturated devices (linear region): 1/ ( ) , 1/ ( ) 2 1 DSn ey oxGST yc oxGSTeyy yc DS DSeoxGST ec eoxDS DSGSTDS DS c

52、 IQv W E WCVVV y EE WdV y CVVV yEE dyEE I IdyWCVVV ydV y WE WCV IVVV LV E L ? 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 33 2.5 Velocity-Saturated Current Equations-8 v Current equations for velocity-saturated devices (saturation region): v For long channel devices,

53、ECLVGS-VT, v For short channel devices, ECLVGS-VT 2 2 1 () () DSnsatoxGSTDSsat eoxDS DSGSTDS DS c GST GSTc DsatDSsatox GSTcGSTc IQvWWCVVVv WCV IVVV LV E L VVVVE L VIWv C VVE LVVE L 22 2 2 GSTGST DSsatoxsatoxeoxGST GSTcc VVVVW IWv CWv CCVV VVE LE LL 2 GST DSsatoxsatoxGST GSTc VV IWv CWv CVV VVE L 202

54、1-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 34 2.6 Subthreshold Condition () (1) GSToffset DS q VVV qV nkTkT subs II ee 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 35 2.7 Capacitance of the MOS transistor-1 v The switching speed of MOS dig

55、ital circuits is limited by the time required to charge and discharge the capacitances at internal node, which must be calculated from device dimensions and dielectric constants. v Two nonlinear or voltage dependent capacitances: Thin oxide capacitances: Cgs, Cgd, Cgb Junction capacitances: Csb, Cdb

56、 v Linear and voltage independent capacitance Overlap capacitance: Col 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 36 2.7 Capacitance of the MOS transistor-2 v The two plates of the thin oxide capacitance are defined as the gate and the channel. The dielectric materia

57、l is the oxide sandwiched between these two plates. The total capacitance of the thin oxide is: v Cox is the capacitance per unit area of the gate dielectric. v Cg has remained constant for over 25 years. The reason is that both L and tox are scaled at the same rate. / Goxoxoxg CWLCWLtWC 14 14 14 /

58、48.85 105/ 1101.6/ 48.85 100.35/ 7.5 1.6/ 48.85 100.1/ 2.2 1.6/ goxoxox g g CC LL t mnmfFm Cmnm fFm Cmnm fFm 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 37 2.7 Capacitance of the MOS transistor-3 v When the device is cutoff, the channel is not existed between the drai

59、n and source. The gate-to-drain and gate-to-source capacitance is zero, that is, Cgs=Cgd=0. the gate-to-bulk capacitance is approximated to: Cgb=WLCox. v In the linear region, Cgs and Cgd are approximately equal to (1/2) Cg since the channel extends from source to drain. v In the saturation region,

60、the channel extends most of the way from source to drain, so most of the gate capacitance can be attributed to the source node, and a negligible amount to the drain node. Cgs=(2/3) Cg and Cgd=0. 2021-5-15 Digital Integrated Circuits Faculty of Materials and Energy, GDUT 38 2.7 Capacitance of the MOS