北理工VHDL實(shí)驗(yàn)報(bào)告綜述

1、北京理兀尢爭(zhēng)Beijing institute oj Technology本科實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)名稱： VHDL語言及集成電路設(shè)計(jì)實(shí)驗(yàn)課程名稱：VHDL語言及集成電路設(shè)計(jì)實(shí)驗(yàn)時(shí)間：2014.5任課教師：桂小琰實(shí)驗(yàn)地點(diǎn)：4-427實(shí)驗(yàn)教師：任仕偉實(shí)驗(yàn)類型：原理驗(yàn)證綜合設(shè)計(jì)自主創(chuàng)新學(xué)生姓名：學(xué)號(hào)/救：組號(hào)：學(xué)院：信息與電子學(xué)院同組搭檔：專業(yè)：電子科學(xué)與技術(shù)成績(jī)：信息與電子學(xué)院8CHOOI. OF INFORMATION AMD ELECTRONIC實(shí)驗(yàn)一：帶有異步復(fù)位端的D觸發(fā)器一、實(shí)驗(yàn)?zāi)康模?）熟悉linux操作環(huán)境和modelsim軟件環(huán)境（2）理解時(shí)序邏輯和組合邏輯電路的區(qū)別（3）理解并行語句和順

2、序語句（4）用VHDL語言編寫一個(gè)帶有異步復(fù)位端的D觸發(fā)器及其測(cè)試文件二. 實(shí)驗(yàn)原理（1）組合邏輯和時(shí)序邏輯 組合邏輯電路當(dāng)前輸出的值僅取決于當(dāng)前的輸入，不需要觸發(fā)器等具有存儲(chǔ)能力 的邏輯單元，僅僅使用組合邏輯門時(shí)序邏輯電路的當(dāng)前輸出不僅取決于當(dāng)前的輸入，還與以前的輸入有關(guān)，這類電 路中包括寄存器等元件，也包括組合邏輯電路，寄存器通過一個(gè)反饋環(huán)和組合邏輯 模塊相連。觸發(fā)器便是屬于時(shí)序邏輯電路輸入A組合邏輯輸出(a)（a）組合邏輯電路;（b）時(shí)序邏輯電路（2）并行和順序代碼從本質(zhì)上講，VHDL代碼是并發(fā)執(zhí)行的。只有PROCESS, FUNCTION或 PROCEDURE內(nèi)的代碼才是順序執(zhí)行的。當(dāng)

3、它們作為一個(gè)整體時(shí)，與其他模塊之間 又是并發(fā)執(zhí)行的。以下是3個(gè)并發(fā)描述語句（statl,stat2和stat3）的代碼，會(huì)產(chǎn)生同樣的電路結(jié)構(gòu)。stat 1stat3stat 1stat2=stat2=stat3=其他排列順序stat3stat 1stat2（3）并行語句進(jìn)程（PROCESS） 語法結(jié)構(gòu)：進(jìn)程名：JPROCESS （敬感信號(hào)列表）變量說明語句 BEGIN （順序執(zhí)行的代碼） END PROCESS 進(jìn)程名; PROCESS的特點(diǎn)1多進(jìn)程之間是并行執(zhí)行的；2進(jìn)程結(jié)構(gòu)內(nèi)部的所有語句都是順序執(zhí)行的；3進(jìn)程中可訪問結(jié)構(gòu)體或?qū)嶓w中所定義的信號(hào)；4進(jìn)程的啟動(dòng)是山敬感信號(hào)列表所標(biāo)明的信號(hào)來觸發(fā)

4、，也可以用WAIT語句等待一 個(gè)觸發(fā)條件的成立。5各進(jìn)程之間的通信是山信號(hào)來傳遞的。（4）帶有異步復(fù)位端的D觸發(fā)器電路符號(hào)RDCPQ0XX01X0保持1X1保持10上升沿011上升沿1三、實(shí)驗(yàn)代碼LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff ISPORT(d,clk,rst:IN STD_LOGIC; q:OUT STD_LOGIC);END dff;ARCHITECTURE behavior OF dff ISBEGINPROCESS(rst,clk)BEGINIF(rst 二 T) THEN qd,clk=clk,rst=rst,q

5、=q);clk_gen:processbeginclk=0;wait for clk_period/2: cik=r；wait for clk_period/2; end process;d_gen: processbeginwait for 100 ns; dv 二 T;wait for 100 ns; d=0,;end process;rst_gen: processbeginrstv二T;wait for 150 ns;rst=,0;wait for 500 ns; rstv=T;wait for 150 ns;wait;end process;end tb_behavior;四、仿真結(jié)

6、果ii wave default前為$迪esn/ciff tb/d/dOb/ciK巾心呦/ciff tb/rst實(shí)驗(yàn)二步進(jìn)電機(jī)控制器一、實(shí)驗(yàn)?zāi)康?1) 理解兩種狀態(tài)機(jī)的區(qū)別(2) 熟悉兩種編程風(fēng)格(3) 編寫B(tài)CD計(jì)數(shù)器和步進(jìn)電機(jī)二、實(shí)驗(yàn)原理(1)米里型狀態(tài)機(jī)和摩爾型狀態(tài)機(jī)米里(Mealy)型狀態(tài)機(jī):狀態(tài)機(jī)的輸出信號(hào)不僅與電路的當(dāng)前狀態(tài)有關(guān)，還與當(dāng)前 的輸入有關(guān)輸入1次態(tài)次態(tài)狀態(tài)現(xiàn)態(tài)J輸出邏耕1邏輯輸出時(shí)鐘信號(hào)復(fù)位信號(hào)摩爾(Moore)型狀態(tài)機(jī)：狀態(tài)機(jī)的當(dāng)前輸出僅僅山當(dāng)前狀態(tài)決定狀態(tài)寄存器時(shí)鐘信號(hào)復(fù)位信弓（2）有限狀態(tài)機(jī)設(shè)計(jì)流程:1理解問題背景。2邏輯抽象，得出狀態(tài)轉(zhuǎn)移圖。3狀態(tài)簡(jiǎn)化。4狀態(tài)分

7、配。5用VHDL來描述有限狀態(tài)機(jī)。（3） BCD計(jì)數(shù)器 原理圖（4）步進(jìn)電機(jī)控制器 原理圖步進(jìn)電機(jī)狀態(tài)與輸出信號(hào)的對(duì)應(yīng)關(guān)系狀態(tài)輸出狀態(tài)so0001S10010S20100S31000三、實(shí)驗(yàn)代碼(1) BCD計(jì)數(shù)器library ieee;use ieee.std_logic_l 164.all;entity counter isport(clk.rst:in std_Iogic;count:out std_logic_vector(3 downto 0); end counter;architecture state_machine of counter istype state is(ze

8、ro,one,twojhree,four,five,six,seven,eight,nine);signal pr_state,nx_state:state;beginprocess (rst.clk)beginif(rst=*r)thenpr_state count =H0000n;nx_state count =H0001H;nxstate count =H0010n;nx_state count =H0011M;nx_state count =H0100n;nxstate count =H0101n;nxstate count v二”0110”；nx_state count =H0111

9、H;nx.state count =H1000n;nx_state count =H1001H;nx_state = zero;end case;end process;end state_machine;(2)步進(jìn)電機(jī)控制器library ieee;use ieee.std_logic_l 164.all;entity stepmotor isport(clk,rst,x:in std_logic;output:out std.logic_vector(3 downto 0); end stepmotor;architecture state_machine of stepmotor ist

10、ype state is(s0,sl,s2,s3);signal pr_state,nx_state:state;beginprocess (clkjst)beginif(rst=*r)thenpr_state=sO;elsif(clk event and elk = r)thenpr_state output =H0001H; nxstate output =M0010n;nxstate output =H0100;nxstate output =H1000;nx_state output =H0001H; nx_state output =H0010H; nx_state output =

11、H0100H; nx_state output =H1000H; nx_state = sO;end case;end if;end process;end stat jmachine;四、仿真結(jié)果BCD 11-數(shù)器步進(jìn)電機(jī)控制器實(shí)驗(yàn)三十六位加法器設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康模?）掌握元件例化的方法（2）理解for/generate語句的用法（3）編程完成4位加法器和16位加法器的設(shè)計(jì)二、實(shí)驗(yàn)原理（1）元件的例化元件聲明是對(duì)VHDL模塊（即底層設(shè)計(jì)，也是完整的VHDL設(shè)計(jì)）的說明，使 之可在其他被調(diào)用，元件聲明可放在程序包中，也可在某個(gè)設(shè)訃的構(gòu)造體中聲明。元件例化指元件的調(diào)用。元件聲明及元件例化的語法分別

12、如下：元件聲明：component元件實(shí)體名prot （元件端口信息，同該元件實(shí)現(xiàn)時(shí)的實(shí)體的port部分）；end compnent:元件例化：例化名：實(shí)體名，即元件名port map （ 端口列表）；（2）生成語句（GENERATE）GENERATE語句用于循環(huán)執(zhí)行某項(xiàng)操作。FOR模式的生成語句主要用于相同結(jié)構(gòu)的描述中；FOR模式語法結(jié)構(gòu)：FOR/GENERATE:標(biāo)號(hào)：FOR變量IN離散區(qū)間GENERATE（并行處理語句）；END GENERATE；（3） 16位加法器的設(shè)計(jì)A(15:12)B(15:12)A(15:12)B(1512)A15:12)B(15:12)A(15:12)5(15

13、:12)S(15;12)S :8)S(7;4)S(3;0”三、實(shí)驗(yàn)代碼4位加法器：library ieee;use ieee.std_logic_l 164.all;entity adder4 isport(a,b:in std_Iogic_vector(3 downto 0);cin:in stdogic;s:out std_logic_vector(3 downto 0); cout:out stdogic);end adder4;architecture behav of adder4 issignal c: std_logic_vector(4 downto 0);signal p:

14、std_Iogic_vector(3 downto 0);signal g: std_logic_vector(3 downto 0);beginG1:for i in 0 to 3 generatep(i)=a(i) xor b(i);g(i)=a(i) and b(i);s(i)=p(i) xor c(i);end generate;c(0)=cin;c(l )=(cin and p(0) or g(0);c(2)=(cin and p(0) and P(l) or (g(0) and p( 1) or g(l);c(3)=(cin and p(0) and P( 1 )and P(2)

15、or (g(0) and p(l) and P(2) or (g(l) and P(2) or g(2);c(4)=(cin and p(0) and P( 1 )and P(2) and P(3) or (g(0) and p(l) and P(2) and P(3) or (g(l) and P(2) and P(3) or (g(2) and P(3) or g(3);couta,b=b,s=s,cin=cin,cout=cout)； processbegina=x,0000n;b=x0000;cin=T;wait for 100ns;a=0000100000000001b=010000

16、00000001ir,; cin=0;wait for 100ns;a=xHllir,;b=x,mr,；cinv=T;wait for 100ns;a=H0000100000000001n; b=Hl110000000000111n; cin33 VHDL Hantwre Oescnpbcci LanjPP)P6)P4)（3）乘法器部分釆用并行乘法器并型乘法器top_rowa(0)mid rowmid rowmid rowlower_rowb(3)b(2)bl)M)A*2)3)PP3)(4) 加法器：8位加法器的設(shè)計(jì)和上一個(gè)試驗(yàn)類似，先設(shè)計(jì)一個(gè)4位加法器，進(jìn)而 編譯8位加法器。三、實(shí)驗(yàn)代碼與門

17、：library ieee;use ieee.std_logic_l 164.all;entity and_2 isport(a,b:in stdjogic;y:out std_logic);end and_2;architecture behav of and_2 isbeginy= a and b;end behav;全加器：library ieee;use ieee.std_logic_l 164.all;entity fau isport(a,b,cin:in std_logic;s,cout:out std_logic);end fau;architecture behav of f

18、au isbegins=a xor b xor cin;cout=(a and b)or(a and cin)or(b and cin);end behav;頂層：library ieee;use ieee.std_logic_1164.all;use work.mycomponents.all;entity top_row isport(a:in std_logic;b:in std_logic_vector(7 downto 0);sout,cout:out std_logic_vector(6 downto 0);p:out stdogic);end top_row;architectu

19、re behav of top_row isbeginu 1:component and_2 port map(a,b(7),soiit(6);u2:component and_2 port map(a,b(6),soiit(5);u3:component and_2 port map(a,b(5),sout(4);u4:component and_2 port map(a,b(4),sout(3);u5:component and_2 port map(a,b(3),sout(2);u6:component and_2 port map(a,b(2),sout( 1);u7:conipone

20、nt and_2 port map(久b(l),sout(0);u8:component and_2 port map(a,b(0),p);u9:for i in 0 to 6 generatecout(i)=,0,;end generate;end behav;中層：library ieee;use ieee.std_logic_1164.all;use work.mycomponents.all;entity mid_row isport(a:in std_logic;b:in std_logic_vector(7 downto 0); sin,cin:in std_logic_vecto

21、r(6 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out stdogic);end mid_row;architecture behav of mid_row issignal and_out:std_logic_vector(6 downto 0);beginul:component and_2 port map(a,b(7),sout(6);u2:component and_2 port map(久b(6),and_out(6);u3:component and_2 port map(久b(5),and_out(5);

22、u4:component and_2 port map(a,b(4),and_out(4);u5:component and_2 port map(a,b(3),and_out(3);u6:component and_2 port map(a,b(2),and_out(2);u7component and_2 port map(a,b( 1 ),and_out( 1);u8component and_2 port map(a,b(0),and_out(0);u9:coniponent fau port map(sin(6),cin(6),and_out(6),sout(5),cout(6);

23、ul0:coniponent fau port map(sin(5),cin(5),and_out(5),sout(4)5cout(5);u 11:component fau port map(sin(4),cin(4),and_out(4),sout(3),cout(4); u!2:coniponent fau port map(sin(3),cin(3),and_out(3),sout(2),cout(3); ul3:coniponent fau port map(sin(2),cin(2),and_out(2),sout(l),cout(2); ul4:component fau por

24、t map(sin( 1 ),cin( 1 ),and_out( 1 ),sout(0),cout( 1); ul5:component fau port map(sin(0),cin(0),and_out(0),p,cout(0); end behav;底層：library ieee;use ieec.std_logic_l 164.all;use work.my_components.all;entity lower_row isport(sin,cin:in stdjogic_vector(6 downto 0); p:out std_logic_vector(7 downto 0);

25、end lower_row;architecture behav of lower_row issignal local:stdogic_vector(6 downto 0);beginlocal(0)=0;u 1:component fau port map(sin(0),cin(0)Jocal(0),p(0)Jocal( 1); u2:component fau port map(sin( 1 ),cin( 1),local( 1 ),p( 1)Jocal(2); u3component fau port map(sin(2),cin(2)Jocal(2),p(2)Jocal(3); u4

26、:coniponent fau port map(sin(3),cin(3)Jocal(3),p(3)Jocal(4); u5component fau port map(sin(4),cin(4)Jocal(4),p(4)Jocal(5); u6:coniponent fau port map(sin(5),cin(5)Jocal(5),p(5)JocaI(6); u7component fau port map(sin(6),cin(6),local(6),p(6),p(7); end behav;乘法器用到的的元件聲明：library ieee;use ieee.std_logic_11

27、64.all;package my_components iscomponent and_2 isport(a,b:in stdjogic;y:out stdjogic);end component;component fau isport(a5b,cin:in std_logic;s,cout:out stdogic);end component;component top_row isport(a:in std_logic;b:in std_logic_vector(7 downto 0);sout,cout:out std_logic_vector(6 downto 0); p:out

28、stdogic);end component;component mid_row isport(a:in stdogic;b:in std_logic_vector(7 downto 0);sin,cin:in std_logic_vector(6 downto 0); sout,cout:out std_logic_vector(6 downto 0);p:out stdogic);end component;component lower_row isport(sin,cin:in stdogic_vector(6 downto 0); p:out std_logic_vector(7 d

29、ownto 0);end component;end my_components;乘法器：library ieee;use ieee.std_logic_l 164.all;use work.mycomponents.all;entity multiplier isport(a,b:in std_logic_vector(7 downto 0);prod:out std_logic_vector( 15 downto 0);end multiplier;architecture behav of multiplier istype matrix is array (0 to 7) of std

30、_logic_vector(6 downto 0);signal s,c:matrix;beginul:component top_row port map(a(0),b,s(0),c(0),prod(0);u2:coniponent mid_row port map(a( 1 ),b,s(0),c(0),s( 1 ),c( 1 ),prod( 1); u3component mid_row port map(a(2),b,s( 1 ),c( 1 ),s(2),c(2),prod(2); u4:coniponent mid_row port map(a(3)bs(2),c(2),s(3),c(

31、3),piod(3); u5:coniponent mid_row port map(a(4),b,s(3),c(3),s(4),c(4),piod(4); u6:coniponent mid_row port map(a(5),b,s(4),c(4),s(5),c(5),prod(5); u7:component mid_row port map(a(6),b,s(5),c(5),s(6),c(6)，prod(6);u8:coniponent mid_row port map(a(7),b,s(6),c(6),s(7),c(7),prod(7);u9:coniponent lower_row

32、 port map(s(7),c(7),prod( 15 downto 8);end behav;4位加法器：library ieee;use ieec.std_logic_l 164.all;entity adder4 isport(a,b:in std_logic_vector(3 downto 0);cin:in stdogic;s:out std_logic_vector(3 downto 0);cout:out stdogic);end adder4;architecture behav of adder4 issignal c: std_logic_vector(4 downto

33、0);signal p: std_logic_vector(3 downto 0);signal g: std_logic_vector(3 downto 0);beginG1:for i in 0 to 3 generatep(i)=a(i) xor b(i);g(i)=a(i) and b(i);s(i)=p(i) xor c(i);end generate;c(0)=cin;c( 1 )=(cin and p(0) or g(0);c(2)=(cin and p(0) and P(l) or (g(0) and p( 1) or g(l);c(3)=(cin and p(0) and P( 1 )and P(2) or (g(0) and p(l) and P(2) or (g(l) and P(2) or g(2);c(4)=(cin and p(0) and P( 1 )and P(2) and P(3) or (g(0) and p(l) a