湘潭大學(xué)計(jì)算機(jī)原理試驗(yàn)四多周期MIPSCPU存儲(chǔ)器試驗(yàn)預(yù)習(xí)報(bào)告解析

1、實(shí)驗(yàn)四 多周期 MIPS CPU + 存儲(chǔ)器實(shí)驗(yàn)一實(shí)驗(yàn)?zāi)康?、深入理解 MIPS CPU 指令系統(tǒng)的功能和工作原理；2、掌握多周期 CPU 的工作原理和邏輯功能實(shí)現(xiàn)；3、熟練掌握用 Verilog HDL 語(yǔ)言設(shè)計(jì)多周期存儲(chǔ)器的方法；4、熟練掌握對(duì)多周期存儲(chǔ)器的仿真實(shí)驗(yàn)驗(yàn)證和硬件測(cè)試兩種調(diào)試方法；5、通過(guò)對(duì)多周期 CPU 的運(yùn)行情況進(jìn)行觀察和分析，進(jìn)一步加深理解。二實(shí)驗(yàn)設(shè)備硬件： 現(xiàn)代計(jì)算機(jī)組成原理實(shí)驗(yàn)系統(tǒng)（兼）Nios 32 位嵌入式系統(tǒng)實(shí)驗(yàn)開(kāi)發(fā)平臺(tái)EP1C12Q240Core（TM）i3-3240 CPU3.40GHz 3.39GHz 1.91GB的內(nèi)存軟件： QuartusII 13.0

2、sp1Microsoft Windows xp三實(shí)驗(yàn)內(nèi)容1、設(shè)計(jì)一個(gè) 32 位 MIPS 多周期 CPU : 至少運(yùn)行下列的 6 類(lèi) 32 條 MIPS 指令。（1）and、 sub、addi（2and、 0r、xor、 andi、 ori 、xori（3sll 、srl 、sra（4）beq、 bne、（5）j、 jr（6）lw 、 sw2.設(shè)計(jì)一個(gè)存儲(chǔ)器四實(shí)驗(yàn)原理與步驟實(shí)現(xiàn)上述原理框圖根據(jù)功能將其分劃分為控制單元(cunit) 、執(zhí)行單元 (eunit) 、指令單元 (iunit)以及存儲(chǔ)單元 (munit) 四大模塊。(1) .控制單元 (cunit)行等工作。主要由指令譯碼器控制器 (

3、outputs control) 、算術(shù)邏輯運(yùn)算控制器 (ALU control) 兩 個(gè)子模塊組成。(2) .執(zhí)行單元 (eunit) 主要由寄存器堆 (registers)和算術(shù)邏輯單元 (ALU) 兩個(gè)子模塊組成。其 MIPS 系統(tǒng)的寄存器堆由 32 個(gè) 32ALU 等邏輯運(yùn)算。指令單元 (iunit) 的作用是決定下一條指令的地址 PC(3) .存儲(chǔ)單元 (munit)由存儲(chǔ)器 (memory) 、指令寄存器 (instruction register) 和存儲(chǔ)數(shù)據(jù)寄存 器 (memory data register) 組成。五實(shí)驗(yàn)源代碼寄存器元件代碼：module regfile (

4、rna,rnb,d,wn,we,clk,clrn,qa,qb);input4:0rna,rnb,wn;input31:0d;inputwe,clk,clrn;output31:0qa,qb;reg31:0register 1:31;/r1-r31assignqa = (rna =0) ? 0 :registerrna;/readassignqb = (rnb =0) ? 0 :registerrnb;/readalways (posedge clk or negedge clrn) beginif (clrn = 0) begin/resetinteger i;for (i=1; i32; i

5、=i+1) registeri = 0;endelse beginif (wn != 0) & (we = 1)/writeregisterwn = d;end end endmodule32 位四選一選擇器：module mux4x32 (a0,a1,a2,a3,s,y);input 31:0a0,a1,a2,a3;input 1:0s;output 31:0y;function 31:0select;input 31:0a0,a1,a2,a3;input 1:0s;case (s)2b00:select= a0;2b01:select= a1;2b10:select= a2;2b11:se

6、lect= a3;endcase endfunctionassign endmoduleselect (a0,a1,a2,a3,s);5 位二選一選擇器： module mux2x5 (a0,a1,s,y);input 4:0 a0,a1;inputs;output4:0 y;assigny = s ? a1 : a0;endmodule32 位二選一選擇器： module mux2x32 (a0,a1,s,y);input31:0a0,a1;inputs;output31:0y;assigny = s ? a1 : a0;endmodule存儲(chǔ)器元件：module mcmem (clk, d

7、ataout, datain, addr, we, inclk, outclk);input31:0datain;input31:0addr;inputclk, we, inclk, outclk;output31:0dataout;wirewrite_enable = we & clk;lpm_ramdqram(.data(datain),.address(addr7:2),.we(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout);defparamram.lpm_width= 32;defparamram.lpm_widt

8、had= 6;defparamram.lpm_indata= registered;defparamram.lpm_outdata= registered;defparamram.lpm_file= mcmem.mif;defparamram.lpm_address_control= registered;endmodule控制部件：module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca, alusrcb, pcsource, jal, sex

9、t, state);input5:0 op, func;inputz, clock, resetn;output regwpc, wir, wmem, wreg, iord, regrt, m2reg;output reg3:0 aluc;output reg1:0 alusrcb, pcsource;output regshift, alusrca, jal, sext;output reg2:0 state;reg 2:0 next_state;parameter2:0 sif =3b000,/ IF statesid =3b001,/ ID statesexe =3b010,/ EXE

10、statesmem= 3b011,/ MEM stateswb =3b100;/ WB statewire r_type,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr;wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal; and(r_type,op5,op4,op3,op2,op1,op0); and(i_add,r_type, func5,func4,func3,func2,func1,func0); and(i_sub,r_type, func5

11、,func4,func3,func2, func1,func0); and(i_and,r_type, func5,func4,func3, func2,func1,func0); and(i_or, r_type, func5,func4,func3, func2,func1, func0); and(i_xor,r_type, func5,func4,func3, func2, func1,func0); and(i_sll,r_type,func5,func4,func3,func2,func1,func0); and(i_srl,r_type,func5,func4,func3,fun

12、c2, func1,func0); and(i_sra,r_type,func5,func4,func3,func2, func1, func0); and(i_jr, r_type,func5,func4, func3,func2,func1,func0); and(i_addi,op5,op4, op3,op2,op1,op0); and(i_andi,op5,op4, op3, op2,op1,op0); and(i_ori, op5,op4, op3, op2,op1, op0); and(i_xori,op5,op4, op3, op2, op1,op0); and(i_lw, op

13、5,op4,op3,op2, op1, op0); and(i_sw, op5,op4, op3,op2, op1, op0); and(i_beq, op5,op4,op3, op2,op1, op0); and(i_bne, op5,op4,op3, op2,op1, op0); and(i_lui, op5,op4, op3, op2, op1, op0); and(i_j, op5,op4,op3,op2, op1,op0); and(i_jal, op5,op4,op3,op2, op1, op0);wire i_shift;or (i_shift,i_sll,i_srl,i_sra

14、);always * begin/ control signals dfault outputs:wpc =0;/ do not write pcwir =0;/ do not write irwmem= 0;/ do not write memorywreg =0;/ do not write register fileiord =0;/ select pc as memory addressaluc =4bx000;/ ALU operation: addalusrca =0;/ ALU input a: reg a or saalusrcb =2h0;/ ALU input b: reg

15、 bregrt =0;/ reg dest no: rdm2reg= 0;/ select reg cshift =0;/ select reg apcsource =2h0;/ select alu outputjal = 0;/ not a jalsext= 1;/ sign extendcase (state)/- IF:sif: begin/ IF statewpc =1;/ write pcwir =1;/ write IRalusrca =1;/ PCalusrcb =2h1;/ 4next_state =sid;/ next state: IDend/- ID:sid:begin

16、/ ID stateif (i_j) begin/ j instructionpcsource= 2h3;/ jump addresswpc= 1;/ write PCnext_state= sif;/ next state: IFendelse if (i_jal) begin/ jal instructionpcsource= 2h3;/ jump addresswpc= 1;/ write PCjal= 1;/ reg no = 31wreg= 1;/ save PC+4next_state= sif;/ next state: IFendelse if (i_jr) begin/ jr

17、 instructionpcsource= 2h2;/ jump registerwpc= 1;/ write PCnext_state= sif;/ next state: IFendelse begin/ other instructionaluc= 4bx000;/ addalusrca= 1;/ PCalusrcb= 2h3;/ branch offsetnext_state= sexe;/ next state: EXEendend/ EXE:sexe: begin/ EXE statealuc3 = i_sra;aluc2 = i_sub | i_or | i_srl | i_sr

18、a | i_ori | i_lui ;aluc1i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne |i_lui ;| i_srl | i_sra | i_andi | i_ori ; / beq or bne instruction / branch address/ next state: IF/ other instruction/ lw or sw instruction/ select offset/ next state: MEM/ other instruction/ shift instructionaluc0 = i_

19、and | i_or| i_sllif (i_beq | i_bne) beginpcsource = 2h1;wpc = i_beq & z | i_bne & z; / write PC next_state = sif;endelse beginif(i_lw | i_sw) beginalusrcb= 2h2;next_state= smem;endelse beginif (i_shift)shift = 1;if (i_addi | i_andi | i_ori | i_xori | i_lui)alusrcb =2h2;/ select immediateif (i_andi |

20、 i_ori |i_xori)sext =0;/ 0-extendnext_state =swb;/ next state: WBend end end/ MEM:smem: begin/ MEM stateiord = 1;/ memory address = Cif (i_lw) beginnext_state = swb;/ next state: WBendelse begin / store wmem = 1; / write memory next_state= sif; / next state: IFendend/ WB:swb: begin/ WB stateif (i_lw

21、)m2reg = 1; / select memory dataif (i_lw | i_addi | i_andi | i_ori | i_xori | i_lui)regrt=1;/ reg dest no: rtwreg=1;/ write register filenext_state=sif;/ next state: IFend/ENDsif;/default statedefault: begin next_state endendcaseend/ state registersalways (posedge clock or negedge resetn) begin if (

22、resetn = 0) begin state = sif;endelse beginstate = next_state;endendendmodule32 位帶使能端觸發(fā)器： module dffe32 (d,clk,clrn,e,q);input 31:0 d;input clk,clrn,e;output 31:0 q;reg 31:0 q;always (negedge clrn or posedge clk)if (clrn = 0) beginq = 0;endelse beginif(e = 1) q = d;endendmodule32 位觸發(fā)器：module dff32 (

23、d,clk,clrn,q);input 31:0 d;input clk,clrn;output 31:0 q;reg 31:0 q;always (negedge clrn or posedge clk)if (clrn = 0) beginq = 0;end else begin q = d;endendmoduleALU 計(jì)算部件： module alu (a,b,aluc,r,z);input 31:0 a,b; input 3:0 aluc; output 31:0 r; output z;assign r = cal(a,b,aluc);assign z = |r; functio

24、n 31:0 cal;input 31:0 a,b;input 3:0 aluc;casex (aluc)4bx000: cal=a+b; 4bx100: cal=a-b; 4bx001: cal=a&b; 4bx101: cal=a|b; 4bx010: cal=ab; 4bx110: cal=b15:0,16h0; 4bx011: cal=ba4:0;4b1111: cal=$signed(b)a4:0;endcaseendfunction endmodule其他部件： module f (reg_dest,jal,wn);input4:0reg_dest;inputjal;output4

25、:0wn;assignwn =reg_dest | 5jal;endmodulemodule sa (di,dot); input 4:0 di; output 31:0 dot; assign dot = 27b0,di;endmodulemodule out4 (out); output 31:0 out; assign out = 32h4;endmodulemodule e (immin,sext,immediate,offset);input15:0immin;inputsext;output31:0immediate,offset;wiree =sext & immin15;wir

26、e15:0imm =16e;assignoffset =imm13:0,immin15:0,1b0,1b0;assignimmediate =imm,immin15:0;endmodulemodule combine (address,pc,add);input25:0address;input3:0pc;output31:0add;assignadd =pc3:0,address25:0,1b0,1b0;endmodulemodule convert1 (dain,sain,op,func,rs,rt,rd,imm,addr);input31:0 dain;output4:0sain,rs,

27、rt,rd;output5:0op,func;output15:0imm;output25:0addr;assignsain =dain10:6;assignop= dain31:26;assignfunc =dain5:0;assignrs= dain25:21;assignrt= dain20:16;assignrd= dain15:11;assignimm =dain15:0;assignaddr =dain25:0;endmodulemodule convert2 (pc,pcout); input31:0pc;output 3:0pcout;pc31:28;assign pcout

28、endmodule存儲(chǔ)器內(nèi)的測(cè)試數(shù)據(jù)：- Copyright (C) 1991-2013 Altera Corporation- Your use of Altera Corporations design tools, logic functions- and other software and tools, and its AMPP partner logic- functions, and any output files from any of the foregoing- (including device programming or simulation files), and

29、 any- associated documentation or information are expressly subject - to the terms and conditions of the Altera Program License - Subscription Agreement, Altera MegaCore Function License - Agreement, or other applicable license agreement, including, - without limitation, that your use is for the sol

30、e purpose of- programming logic devices manufactured by Altera and sold by - Altera or its authorized distributors. Please refer to the - applicable agreement for further details.DEPTH = 64;- Quartus II generated Memory Initialization File (.mif)%Memory depth and width are required%WIDTH = 32;%Enter

31、 a decimal numberADDRESS_RADIX = HEX; DA TA_RADIX = HEX;%Address and value radixes are optional %Enter BIN, DEC, HEX, or OCT; unless %otherwise specified, radixes = HEXCONTENT BEGIN0.3F : 00000000; % Range-Every address from 0 to 3F =00000000%0 :3c010000; % (00)main:luir1,0# address of data0%1 :3424

32、0080; % (04)orir4,r1, 0x80# address of data0%2 :20050004; % (08)addi r5,r0,4# counter%3 :0c000018; % (0c)call:jal sum# call function%4 :ac820000; % (10)sw r2,0(r4)# store result%5 :8c890000; % (14)lw r9,0(r4)# check sw%6 :01244022; % (18)sub r8,r9,r4# sub: r8 - r9 - r4%7 :20050003; % (1c)addi r5,r0,

33、3# counter%8 :20a5ffff; % (20)loop2:addi r5,r5,-1# counter - 1%9 :34a8ffff; % (24)ori r8,r5,0xffff# zero-extend: 0000ffff%A: 39085555; % (28)xori r8,r8,0x5555# zero-extend: 0000aaaa%B: 2009ffff; % (2c)addi r9,r0,-1# sign-extend: ffffffff%C: 312affff; % (30)andi r10,r9,0xffff# zero-extend: 0000ffff%D

34、: 01493025; % (34)orr6,r10,r9# or: ffffffff%E: 01494026; % (38)xorr8,r10,r9# xor: ffff0000%F: 01463824; % (3c)andr7,r10,r6# and: 0000ffff%10 : 10a00001;% (40)beqr5,r0, shift # if r5 = 0, goto shift%11: 08000008;% (44)jloop2# jump loop2%12 : 2005ffff; % (48)shift:addi r5,r0,-1# r5 = ffffffff%13 :000543c