綜合電子系統(tǒng)設(shè)計(jì)報(bào)告(基于vhdl的dds信號發(fā)生器)

1、綜合電子系統(tǒng)設(shè)計(jì)課程設(shè)計(jì)報(bào)告 （實(shí)驗(yàn)一：基于FPGA的DDS信號發(fā)生器）姓名：徐久赟學(xué)號：041401012班級：0414103班1、 實(shí)驗(yàn)要求1) 目的：掌握FPGA設(shè)計(jì)流程和HDL；掌握DDS原理及其FPGA的實(shí)現(xiàn)方法。(2) 實(shí)驗(yàn)設(shè)備：PC機(jī)、Quartus II軟件、DE2開發(fā)板。(3) 實(shí)驗(yàn)內(nèi)容及說明：要求DDS輸出的正弦波頻率可變，頻率變化范圍5Hz-100kHz，頻率步進(jìn)值小于1Hz。2、 設(shè)計(jì)原理 DDS系統(tǒng)的核心是相位累加器，它由一個累加器和一個N位相位寄存器組成。每來一個時鐘脈沖，相位寄存器以步長M增加。相位寄存器的輸出與相位控制字相加，其結(jié)果作為正弦查找表的地址。正弦查找

2、表由ROM構(gòu)成，內(nèi)部存有一個完整周期正弦波的數(shù)字幅度信息，每個查找表的地址對應(yīng)正弦波中0360范圍內(nèi)的一個相位點(diǎn)。查找表把輸入的地址信息映射成正弦波的數(shù)字幅度信號，加到DAC的輸入端，DAC輸出的模擬信號經(jīng)過低通濾波器(LPF)，可得到一個頻譜純凈的正弦波。3、 方案論證及詳細(xì)設(shè)計(jì)1.系統(tǒng)設(shè)計(jì)圖1：系統(tǒng)框圖整個系統(tǒng)由五個模塊構(gòu)成：（1）接口模塊，如圖2所示。圖2：接口模塊接口模塊提供了方便的操作接口：reset:復(fù)位clk:系統(tǒng)時鐘（50MHz）clk_en:時鐘使能address:地址總線（控制數(shù)據(jù)總線向?qū)?yīng)的寄存器輸入數(shù)據(jù)）見表1address(2位)寄存器00div_reg（時鐘分頻數(shù)）

3、01M_reg10phase_reg11ddsen_reg表1：地址總線表dataBus:數(shù)據(jù)總線（8位）說明：在接口模塊中，內(nèi)嵌了一個分頻器，來控制輸出的fclk。通過判斷div_reg中的值，分頻值從21000000，通過控制fclk進(jìn)而提高fout，使foutSIN_ROM.mif”。再在文件中加入了頭部說明。最后在Quartus中調(diào)用了LPM庫，生成了sin幅度查詢模塊。2.系統(tǒng)的頂層邏輯圖及DDS的頻率精度與頻率控制字之間的關(guān)系圖6：系統(tǒng)頂層邏輯圖在DDS原理中，將一個正弦函數(shù)用其相位表示，即2pi。同時將其離散化，分成2N個，M為頻率控制字，即為每個fclk時鐘，將初始相位與其相加

4、，得到下一個相位，進(jìn)而得到對應(yīng)幅度值。由fout=M/2N fclk得，M值越大時，此時fout值越大。但是同時，由于M值越大，每次相位累加時，相位值改變的越大，導(dǎo)致幅度值改變的越大。最終生成的正弦函數(shù)失真現(xiàn)象越加嚴(yán)重，即頻率精度越差。所以，頻率精度與頻率控制字成反比關(guān)系。4、 系統(tǒng)調(diào)試及仿真波形圖7：FPGA資源利用圖8：接口模塊仿真圖圖9：同步模塊仿真圖圖10：相位累加器仿真圖圖11: 10位加法器5、 系統(tǒng)實(shí)現(xiàn)功能輸出了一個頻率和相位可以調(diào)控的正弦波。頻率變化范圍：1Hz-5MHz,步進(jìn)值1Hz.6、 設(shè)計(jì)調(diào)試過程中的問題及解決辦法由于整個系統(tǒng)由模塊化組成，每個模塊在設(shè)計(jì)的過程中都通過波

5、形仿真驗(yàn)證其功能的正確性，使得最終的頂層設(shè)計(jì)時，沒有出現(xiàn)太大的問題。但在整個設(shè)計(jì)過程中出現(xiàn)了一些軟件操作和系統(tǒng)設(shè)計(jì)的問題。1. 系統(tǒng)編譯后無法生成SOF文件。 解決：經(jīng)查閱資料后了解到，Quartus在沒有破解的情況下，不生成SOF文件，最終按照教程破解了軟件，成功生成SOF文件。2.DE2開發(fā)板上的擴(kuò)展IO口按鍵過少，不足以滿足整個系統(tǒng)所需。解決：通過增加接口模塊，同時增加address控制數(shù)據(jù)的輸入。3. DE2中的DAC芯片為10bit，這樣就使得輸入的幅度值為10bit，進(jìn)而使得N只能是10位，導(dǎo)致步進(jìn)值和輸出頻率無法同時滿足設(shè)計(jì)需要。 解決：由于DE2的限制，N只能選擇10位，所以在

6、接口模塊，設(shè)計(jì)了分頻計(jì)，這樣就可以通過改變fclk減小步進(jìn)值，使其符合要求。7、 收獲、體會及改進(jìn)設(shè)想1. 通過這次的課程設(shè)計(jì)，重新學(xué)習(xí)了對Quartus軟件的使用，熟練度得到了極大的提高。2. 復(fù)習(xí)了VHDL語言，對VHDL有了更多的認(rèn)識，對其使用更加的得心應(yīng)手。3. 從整體系統(tǒng)的設(shè)計(jì)到底層各個模塊的設(shè)計(jì)與完善，這種層次化，模塊化設(shè)計(jì)，使得整個系統(tǒng)設(shè)計(jì)顯得更加的科學(xué)，極大的降低了系統(tǒng)的出錯率。同時對系統(tǒng)各個模塊的把握，可以更好的調(diào)試與改善整個系統(tǒng)。4. 這樣的設(shè)計(jì)方式，也使得整個系統(tǒng)擴(kuò)展性得到一定的提高。5. 電子系統(tǒng)的設(shè)計(jì)應(yīng)當(dāng)是層次化，模塊化，可調(diào)試性強(qiáng)，可擴(kuò)展性高。優(yōu)秀的設(shè)計(jì)思路可以極大

7、的提高整個設(shè)計(jì)過程的效率。改進(jìn)設(shè)想：1. 頻率精度：隨著M值的增加會導(dǎo)致波形失真，可以試著給每個M值對應(yīng)的N值。2. 可擴(kuò)展性：通過接口模塊，可以控制整個系統(tǒng)輸出不同的波形。8、 參考文獻(xiàn)1 張洪潤，張亞凡FPGA/CPLD應(yīng)用設(shè)計(jì)200例.上冊北京航空航天大學(xué)出版社2009.19、 附錄1. 接口模塊：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity interface is port(reset:in std_logic ;

8、clk:in std_logic;clk_en:in std_logic;address:in std_logic_vector(1 downto 0);dataBus:in std_logic_vector(9 downto 0);fclk:out std_logic;M:out std_logic_vector(9 downto 0);phase:out std_logic_vector(9 downto 0);error:out std_logic;ddsen:out std_logic);end interface;architecture behave of interface is

9、 signal div_reg: std_logic_vector(2 downto 0); signal temp :std_logic; signal m_reg: std_logic_vector(9 downto 0); signal phase_reg: std_logic_vector(9 downto 0); signal ddsen_reg: std_logic :=0; signal error_reg: std_logic;begin p1:process(clk)beginif(reset=0)thendiv_reg=000;m_reg=0000000000;phase_

10、regdiv_regm_regphase_regddsen_regerror_reg=1;end case;end if;end process p1;div_frequency:process(clk,clk_en)variable count :integer range 0 to 9999;variable flag :integer;begin if(clk_en=0)thentempflag:=2;when 001=flag:=5;when 010=flag:=10;when 011=flag:=20;when 100=flag:=50;when 101=flag:=100;when

11、 110=flag:=200;when 111=flag:=500;end case;if(count=flag)thencount:=0;temp=not temp;else count:=count+1;end if;end if;end process div_frequency; fclk=temp;M=m_reg;phase=phase_reg;ddsen=ddsen_reg;error=error_reg;end behave;2. 同步模塊library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;u

12、se IEEE.STD_LOGIC_UNSIGNED.ALL;entity synchronization is port(flck_in:in std_logic ;m_in:in std_logic_vector(9 downto 0);phase_in:in std_logic_vector(9 downto 0);ddsen:in std_logic;fclk:out std_logic;m:out std_logic_vector(9 downto 0);phase:out std_logic_vector(9 downto 0);end synchronization;archit

13、ecture behave of synchronization issignal fclk_reg:std_logic;signal m_reg:std_logic_vector(9 downto 0);signal phase_reg:std_logic_vector(9 downto 0);begin process(ddsen)beginif(ddsen=0)thenfclk_reg=0;m_reg=0000000000;phase_reg=0000000000;elsefclk_reg=flck_in;m_reg=m_in;phase_reg=phase_in;end if;end

14、process;fclk=fclk_reg;m=m_reg;phase=phase_reg;end behave;3. 相位累加器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity phase_sum is generic(m_width:integer :=10);port(fclk:in std_logic; m:in std_logic_vector(m_width-1 downto 0); rest:in std_logi

15、c; phase_out:out std_logic_vector(m_width-1 downto 0);end phase_sum;architecture behave of phase_sum is signal phase_reg: std_logic_vector(m_width-1 downto 0);signal m_reg: std_logic_vector(m_width-1 downto 0);begin process (fclk)begin if rest=0 then phase_reg=0000000000; elsif (fclkEVENT AND fclk=1

16、) thenphase_reg=phase_reg+m_reg; end if;end process;m_reg=m;phase_out=phase_reg;end behave;4. 10位加法器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity add10 is port(phase_sum_in:in std_logic_vector (9 downto 0);phase_control:in std_logic_vect

17、or(9 downto 0);address:out std_logic_vector(9 downto 0);end add10;architecture behave of add10 issignal address_reg:std_logic_vector(10 downto 0);signal phase_sum_reg:std_logic_vector(10 downto 0);signal phase_control_reg:std_logic_vector(10 downto 0);begin phase_sum_reg=0&phase_sum_in;phase_control

18、_reg=0&phase_control;address_reg=phase_sum_reg+phase_control_reg;address=address_reg(9 downto 0);end behave;5. data_rom(調(diào)用LPM庫生成)- megafunction wizard: %ROM: 1-PORT%- GENERATION: STANDARD- VERSION: WM1.0- MODULE: altsyncram - =- File Name: data_rom.vhd- Megafunction Name(s):- altsyncram- Simulation

19、Library Files(s):- altera_mf- =- *- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!- 7.2 Build 151 09/26/2007 SJ Full Version- *-Copyright (C) 1991-2007 Altera Corporation-Your use of Altera Corporations design tools, logic functions -and other software and tools, and its AMPP partner logic

20、-functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License

21、-Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details.LIBRARY ieee

22、;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY data_rom ISPORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END data_rom;ARCHITECTURE SYN OF data_rom ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);COMPONENT altsyncram

23、GENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;ram_block_type: STRING;widthad_a: NATURAL;width_a: NATURAL;wi

24、dth_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = SIN_ROM.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = al

25、tsyncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,ram_block_type = M4K,widthad_a = 10,width_a = 10,width_byteena_a = 1)PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0);END SYN;- =- CNX file retrieval info- =- Retrieval info: PRIVATE: ADDR

26、ESSSTALL_A NUMERIC 0- Retrieval info: PRIVATE: AclrAddr NUMERIC 0- Retrieval info: PRIVATE: AclrByte NUMERIC 0- Retrieval info: PRIVATE: AclrOutput NUMERIC 0- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC 0- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC 8- Retrieval info: PRIVATE: BlankMemory NUMERIC 0-

27、 Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC 0- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC 0- Retrieval info: PRIVATE: Clken NUMERIC 0- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC 0- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING PORT_A- Retrieval info: PRIVATE: INIT_TO

28、_SIM_X NUMERIC 0- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING Cyclone II- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC 0- Retrieval info: PRIVATE: JTAG_ID STRING NONE- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC 0- Retrieval info: PRIVATE: MIFfilename STRING SIN_ROM.mif- Retrieval inf

29、o: PRIVATE: NUMWORDS_A NUMERIC 1024- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC 2- Retrieval info: PRIVATE: RegAddr NUMERIC 1- Retrieval info: PRIVATE: RegOutput NUMERIC 0- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING 0- Retrieval info: PRIVATE: SingleClock NUMERIC 1- Retrieval inf

30、o: PRIVATE: UseDQRAM NUMERIC 0- Retrieval info: PRIVATE: WidthAddr NUMERIC 10- Retrieval info: PRIVATE: WidthData NUMERIC 10- Retrieval info: PRIVATE: rden NUMERIC 0- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING BYPASS- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING BYPASS- Retrieva

31、l info: CONSTANT: INIT_FILE STRING SIN_ROM.mif- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING Cyclone II- Retrieval info: CONSTANT: LPM_HINT STRING ENABLE_RUNTIME_MOD=NO- Retrieval info: CONSTANT: LPM_TYPE STRING altsyncram- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC 1024- Retrieval info: CONSTANT: OPERATION_MODE STRING ROM- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING NONE- Retrieval info: CONSTANT: OUTDATA_REG_A STRING UNREGISTERED- Retrieval info: CONSTANT: RAM_BLOCK_TYPE