單片機(jī)-溫度控制系統(tǒng)-外文翻譯-外文文獻(xiàn)-英文文獻(xiàn)-中英翻譯.doc

1、。DesignoftheTemperatureControlSystemBasedonAT89C51ABSTRACTThe principle and functions of the temperature control system basedon micro controller AT89C51are studied, and thetemperature measurementunit consists of the 1-Wire bus digital temperature sensor DS18B20. Thesystem can be expectedto detectthe

2、presettemperature,displaytime andsave monitoringdata.An alarmwillbe givenby system ifthe temperatureexceeds the upper and lower limit value of the temperature which can beset discretionarily and then automatic control is achieved, thus thetemperature isachieved monitoringintelligentlywithina certain

3、range.Basing on principle of the system, it is easy to make a variety of othernon-linear control systems so long as the software design is reasonablychanged. The system has been proved to be accurate,reliable and satisfiedthrough field practice.KEYWORDS: AT89C51; micro controller; DS18B20; temperatu

4、re1 INTRODUCTIONTemperature is a very important parameter in human life. In themodern society, temperature control (TC) is not only used in industrialproduction, but also widely used in other fields. With the improvementof the life quality, we can find the TC appliance in hotels, factoriesand homeas

5、 well.And the trend thatTC willbetterserve the whole society,so it is of great significance to measure and control the temperature.Based on the AT89C51and temperaturesensor DS18B20, thissystem controlstheconditiontemperatureintelligently.Thetemperaturecan besetdiscretionarily within a certain range.

6、 The system can show the time onLCD, and save monitoringdata; and automaticallycontrolthetemperaturewhen the condition temperature exceeds the upper and lower limit value.By doing so itisto keep the temperatureunchanged. The system is ofhighanti-jamming, high control precision and flexible design; i

7、t also fitstherugged environment.Itis mainly used in peoples lifetoimprovethequality of the work and life. It is also versatile, so that it can be- 可編輯修改 -。convenient to extend the use of the system. So the design is of profound importance. The general design, hardware design and software design of

8、the system are covered.1.1 IntroductionThe8-bitAT89C51 CHMOSmicrocontrollersaredesignedtohandlehigh-speedcalculationsandfastinput/outputoperations.MCS 51microcontrollersare typicallyused forhigh-speed event controlsystems.Commercial applicationsincludemodems,motor-controlsystems,printers,photocopier

9、s, air conditioner control systems, disk drives, and medicalinstruments.The automotiveindustryuseMCS 51microcontrollersinengine-controlsystems,airbags,suspensionsystems,andantilockbrakingsystems(ABS).TheAT89C51 isespeciallywellsuitedtoapplicationsthatbenefitfromitsprocessingspeed and enhanced on-chi

10、pperipheralfunctionsset,such as automotivepower-traincontrol,vehicledynamic suspension,antilockbraking,and stabilitycontrolapplications.Because of these critical applications, the market requires a reliablecost-effectivecontrollerwitha low interruptlatencyresponse,abilitytoservicethe highnumber of t

11、imeand event drivenintegratedperipheralsneeded inrealtimeapplications,and a CPUwith above average processingpower ina singlepackage. The financialand legalriskofhavingdevicesthatoperate unpredictablyisveryhigh.Once in themarket,particularlyinmissioncriticalapplicationssuch as an autopilotor anti-loc

12、kbrakingsystem, mistakes are financially prohibitive. Redesign costs can run ashigh as a $500K, much more if the fix means 2 back annotating it acrossa productfamilythatshare thesame coreand/orperipheraldesign flaw.Inaddition,fieldreplacementsofcomponents isextremelyexpensive,asthe devices are typic

13、ally sealed in modules with a total value severaltimesthatofthecomponent. To mitigatetheseproblems,itisessentialthatcomprehensivetestingof thecontrollersbe carriedoutatboththecomponent level and system level under worst case environmental andvoltage conditions. This complete and thorough validation

14、necessitatesnot only a well-defined process but also a proper environment and toolstofacilitateandexecutethemissionsuccessfully.IntelChandlerPlatform Engineering group provides postsilicon system validation (SV)- 可編輯修改 -。ofvariousmicro-controllersand processors.The systemvalidationprocess can be bro

15、ken into three major parts. The type of the device anditsapplicationrequirementsdeterminewhichtypesoftestingareperformed on the device.1.2 The AT89C51 provides the following standard features4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,a fivevectortwo-levelinterruptarchitecture,af

16、ull duple ser-ialport, on-chip oscillator and clock circuitry. Inaddition, the AT89C51 is designed with static logic for operation downto zero frequency and supportstwo softwareselectablepower saving modes.The IdleModestops the CPUwhile allowingthe RAM,timer/counters,serialportand interruptsys -tem

17、to continuefunctioning.The Power-down Modesaves the RAM contents but freezes the oscil lator disabling all otherchip functions until the next hardware reset.1.3Pin DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bitopen-drainbi-directionalI/O port.As anoutput port, each pin can sink e

18、ight TTL inputs. When 1s are written toport 0 pins, the pins can be used as high impedance inputs. Port 0 mayalso be configuredto be the multiplexedlow order address/databus duringaccesses to externalprogram and data memory. In thismodeP0 has internalpull ups. Port 0 also receives the code bytes dur

19、ing Flash programming,and outputsthe code bytes duringprogram verification.Externalpullupsare required during program verification.Port 1：Port 1 is an 8-bitbi-directionalI/O portwith internalpullups. The Port 1 output buffers can sink/so -urce four TTL inputs. When 1s are written to Port 1 pins they

20、 are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-

21、bitbi-directionalI/O portwith internalpull- 可編輯修改 -。ups. The Port 2 output buffers can sink/source four TTL inputs. When 1sare written to Port 2 pins they are pulled high by the internal pull upsand can be used as inputs.As inputs,Port 2 pinsthatare externallybeingpulled low will source current (IIL

22、) because of the internal pull ups.Port 2 emits the high-order address byte during fetches from externalprogram memoryand duringaccesses to Port2 pinsthat are externallybeingpulled low will source current (IIL) because of the internal pull ups.Port 2 emits the high-order address byte during fetches

23、from externalprogram memoryand duringaccesses to externaldata memorythatuse 16-bitaddresses(MOVXDPTR)In.thisapplication,itusesstronginternalpull-ups when emitting 1s. During accesses to external data memory thatuse 8-bitaddresses (MOVXRI),Port2 emits the contents of the P2 SpecialFunction Register.

24、Port 2 also receives the high-order address bits andsome control signals durin Flash programming and verification.Port 3：Port 3 isan 8-bitbi-directionalI/O port withinternalpullups. The Port 3 output buffers can sink/sou -rce four TTL inputs. When1s are written to Port 3 pins they are pulled high by

25、 the internal pullups and can be used as inputs.As inputs,Port3 pins thatareexternallybeing pulled low will source current (IIL) because of the pull ups.Port 3 also serves the functions of various special features of theAT89C51 as listed below:RST：Reset input.A highon thispin for two machine cyclesw

26、hiletheoscillator is running resets the device.ALE/PROG： Address LatchEnable outputpulseforlatchingthelow byteof the address during accesses to external memory. This pin is also theprogram pulse input(PROG)duringFlash programming. In normaloperationALE is emitted at a constant rate of 1/6 the oscill

27、ator frequency, andmay be used forexternaltimingorclockingpurposes. Note,however,thatone ALE pulse isskipped duri-ngeach access toexternal Data Memory.Ifdesired, ALE operation can be disabled by setting bit 0 of SFR location8EH. With the bitset,ALEisactiveonly duringa MOVXor MOVCinstruction.Otherwis

28、e,the pinisweakly pulledhigh.Settingthe ALE-disablebithasno effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program- 可編輯修改 -。memory. When theAT89C51 is executing code from external program memory,PSEN isactivatedtwiceeachmachinecyc

29、le,exceptthattwoPSENactivations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in orderto enable the device to fetchcode from externalprogram memorylocationsstarting at 0000H up to FFFFH. Note, however, that if lock bit 1 isprogrammed

30、, EA willbe internallylatchedon reset. EA shouldbe strappedto VCCforinternalprogram executions.Thispinalsreceivesthe12-voltprogramming enable voltage(VPP) duringFlash programming,forpartsthatrequire 12-volt VPP.XTAL1： Input to the inverting oscillator amplifier and input to theinternal clock operati

31、ng circuit.XTAL2 ：Output from the invertingoscillatoramplifier.OscillatorCharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chiposcillator, as shown in Figure 1. Either a quartz crystal or ceramicresonatormay be us

32、ed. To drive thedevicefrom an externalclocksource,XTAL2should be left unconnectedwhileXTAL1isdriven as shown in Figure2.Thereare no requirementson the duty cycleofthe externalclocksignal,sincetheinputtotheinternalclockingcircuitryisthrough adivide-by-two flip-flop,but minimumand maximumvoltagehigh a

33、nd low timespecifications must be observed. Idle Mode In idle mode, the CPU putsitselftosleep whileall theon chipperipheralsremainactive.The modeis invokedby software.The contentoftheon-chipRAMand allthespecialfunctionsregistersremainunchanged duringthismode. The idlemodecanbe terminated by any enab

34、ledinterruptor bya hardware reset. Itshouldbe noted that when idle is terminated by a hard ware reset, the devicenormally resumes program execution, from where it left off, up to twomachine cycles beforethe internalresetalgorithmtakescontrol.On-chiphardware inhibitsaccess tointernalRAMinthisevent,bu

35、taccess totheportpinsis not inhibited.To eliminatethepossibilityofan unexpectedwrite to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.- 可編輯修改 -。Power-down ModeIn the power-down mode,

36、the oscillatoris stopped,and the instructionthatinvokes power-down is the lastinstructionexecuted.The on-chipRAMand Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRS but does not change

37、the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator torestart and stabilize. The AT89C51code memoryarray is programmedbyte-by byte in either programming mode. To program any nonblank byte

38、in the on-chip Flash Memory, the entire memorymust be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, theaddress,data and controlsignalsshouldbe setup accordingtothe Flashprogramming modetableand Figure3 and Figure4. To program theAT89C51, takethefollowingstep

39、s.1.Inputthe desired memorylocationon the addresslines.2.Inputthe appropriatedata byte on the data lines.3. Activatethe correctcombinationofcontrolsignals. 4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lockbits.The byt

40、e-writecycleisself-timedand typicallytakes no more than1.5 ms. Repeat steps 1 through 5, changing the address and data for theentirearrayor untilthe end of the objectfileisreached. Data Polling:The AT89C51 features Data Polling to indicate the end of a write cycle.During a write cycle, an attempted

41、read of the last byte written willresultin thecomplement of the writtendatum on PO.7. Once thewritecyclehas been completed,true dataare validon alloutputs,and thenextcyclemay begin. Data Polling may begin any time after a write cycle has beeninitiated.2.1Ready/Busy:The progress of byte programming c

42、an also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to- 可編輯修改 -。indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmedcode data can b

43、e read back via the address and data lines for verification.The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.2.2 Chip Erase:The entire Flash array is erased electrically by using the propercombinationof controlsignalsan

44、d by holdingALE/PROGlow for10 ms. Thecode array is written with all“1”s. The chip erase operation must beexecuted before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signature bytes are read by the same procedure as a normalverificationof locations030H, 031H, and 032H, ex

45、cept thatP3.6 and P3.7must be pulled to a logic low. The values returned areas follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash arraycan be

46、writtenand theentire arraycan be erased by using the appropriate combination of control signals.Thewriteoperationcycleisselftimedand once initiated,willautomaticallytimeitselfto completion.Amicrocomputer interfaceconverts information between two forms. Outside the microcomputer theinformationhandled

47、by an electronicsystem existsas a physicalsignal,but within the program, it is represented numerically. The function ofany interfacecan be brokendown intoa number ofoperationswhich modifythe data in some way, so that the process of conversion between theexternal and internal forms is carried out in

48、a number of steps. Ananalog-to-digitalconverter(ADC)isusedtoconvertacontinuouslyvariable signal to a corresponding digital form which can take any oneofa fixednumberofpossiblebinary values.Iftheoutputof the- 可編輯修改 -。transducerdoes not varycontinuously,no ADCisnecessary.In thiscasethesignalconditioni

49、ngsectionmust convertthe incomingsignaltoa formwhich can be connected directly to the next part of the interface, theinput/outputsectionofthemicrocomputeritself.Outputinterfacestakea similarform,theobviousdifferencebeingthatherethe flowofinformation is in the opposite direction; it is passed from th

50、e programtotheoutsideworld.Inthiscase theprogrammay callanoutputsubroutine which supervises the operation of the interface and performsthescalingnumberswhichmaybeneededfor digital-to-analogconverter(DAC). This subroutine passes information in turn to an outputdevice which produces a corresponding el

51、ectrical signal, which could beconvertedintoanalogformusingaDAC. Finallythesignalisconditioned(usuallyamplified)toa formsuitableforoperatinganactuator.Thesignalsused withinmicrocomputer circuitsarealmostalways toosmallto be connecteddirectlytothe outsideworld ” and somekind of interface must be used to translate them to a more appropriateform. The