串入并出轉(zhuǎn)換器-verilog

1、設(shè)計(jì)一個(gè)串入并出轉(zhuǎn)換器。輸入是8bit數(shù)據(jù)，輸出是32bit數(shù)據(jù)。給出AMSD 圖和HDL設(shè)計(jì)描述。提交紙質(zhì)文檔。、ASMD圖二、RTL代碼/* 程序名稱：串入并出轉(zhuǎn)換器簡要說明：串行輸入 8bit 數(shù)據(jù)，并行輸出 32bit 數(shù)據(jù)。 編 寫：武書肖最后更新： 2015年3月 28日 星期六 */ module ser_to_par(clk,rst_n,en,data_in,data_out,en_out);inputclk,rst_n,en;input7:0 data_in;/8 位串行輸入output31:0 data_out;/32 位并行輸出outputen_out;/ 輸出有效標(biāo)志位

2、reg7:0p0,p1,p2,p3;/4個(gè) 8位寄存器reg31:0data_reg;/32 位輸出寄存器reg4:0state,next_state; /FSM 狀態(tài)regen_out;parameter s_idle=5b00001, / 狀態(tài)獨(dú)熱編碼s_in_1=5b00010,s_in_2=5b00100,s_in_3=5b01000,s_full=5b10000;assign data_out=en_out?data_reg:32dz;always (posedge clk)/ 同步時(shí)序描述狀態(tài)轉(zhuǎn)移beginif(rst_n=0) state=s_idle;else state=ne

3、xt_state;end/ 組合邏輯描述狀態(tài)轉(zhuǎn)移條件判斷next_state=s_in_1; next_state=s_idle; next_state=s_in_2; next_state=s_in_3; next_state=s_full; next_state=s_in_1; next_state=s_idle;always (state or en ) beginnext_state=state; case(state)s_idle: if(en=1) elses_in_1:s_in_2:s_in_3:s_full: if(en=1)elseendcaseend always (pos

4、edge clk) / 同步時(shí)序描述次態(tài)寄存器的輸出 beginif(rst_n=0) en_out=0;elsecase(next_state)s_idle: en_out=0;s_in_1,s_in_2,s_in_3:beginen_out=0; p3=data_in; p2=p3; p1=p2; p0=p1;end s_full: begin data_reg=p3,p2,p1,p0; en_out=1; if(en=1) p3=data_in;endendcase不使用狀態(tài)機(jī)的 RTL代碼*end endmodule/*module ser_to_par(clk,rst_n,en,da

5、ta_in,data_out,en_out);input clk,rst_n,en;input 7:0 data_in; /8 位串行輸入 output 31:0 data_out; /32 位并行輸出 output en_out; / 輸出有效標(biāo)志位reg 7:0 p0,p1,p2,p3; /4個(gè) 8位寄存器 reg 31:0 data_reg; /32 位輸出寄存器 regen_out;integerin_counter; / 輸入數(shù)據(jù)計(jì)數(shù)assign data_out=en_out?data_reg:32dz;always (posedge clk)beginif(!rst_n)begi

6、nin_counter=0; en_out=0;endelse if(en)beginin_counter=in_counter+1;en_out=0;p3=data_in;p2=p3;p1=p2;p0=p1;data_reg=p3,p2,p1,p0;if(in_counter=3)beginen_out=1;in_counter=0;endendendendmodule三、 Test Benchtimescale 1 ns/ 1 psmodule seri_to_para_vlg_tst();reg clk;reg 7:0 data_in;reg en;reg rst_n;wire 31:0

7、 data_out;wire en_out;seri_to_para i1 (/ port map - connection between master ports and signals/registers.clk(clk),.data_in(data_in),.data_out(data_out),.en(en),.en_out(en_out),.rst_n(rst_n);initialbeginclk=0;rst_n=1;en=0;#10 rst_n=0;#100 rst_n=1;#100 en=1;#10000 $stop;endalways #50 clk=clk;always (n e