EDA第3章補充2-毛刺

1、11. Setup/Hold Time Problem2建立時間和保持時間建立時間和保持時間 建立時間（setup time）是指在觸發(fā)器的時鐘信號上升沿到來以前，數據穩(wěn)定不變的時間，如果建立時間不夠，數據將不能在這個時鐘上升沿被打入觸發(fā)器。保持時間（hold time）是指在觸發(fā)器的時鐘信號上升沿到來以后，數據穩(wěn)定不變的時間， 如果保持時間不夠，數據同樣不能被打入觸發(fā)器(如上圖)。 數據穩(wěn)定傳輸必須滿足建立和保持時間的要求，EDA開發(fā)軟件可以自動計算兩個相關輸入的建立和保持時間3Example 14My Waveform InputSetup time = 2nsHold time = 0.

2、1nsAccording to Setup/Hold Matrix Setup time needs = 2.2nsHold time needs = 0.7nsHow to fix ?It is easy. Extend the Setup time from 2ns to 2.2ns Extend the Hold time from 0.1ns to 0.7ns5Correct WaveformExtend the Setup/Hold time to remove the errorWe fix the simulation error. But do we really fix th

3、e error yet ?Simulation : means all the INPUT WAVEFORM is designer provided. We can easily adjust the INPUT WAVEFORM to remove the simulation error. We need to confirm that the REAL INPUT WAVEFORM full fill the Setup/Hold time requirement. 6Example 2All the Setup/Hold prblem between this two FF7How

4、to fix the problemLet us run the Register Performance Timing AnalysisThe Input Clock Frequency is only 3.2ns width 300MHz8ConclusionIf the Setup/Hold time error happen on the Input Register (Example 1)run the Setup/Hold time Matrix to get informationadjust the Input Waveform but double confirm with

5、the real time operation signalIf the Setup/Hold time error happen between Two Register (Example 2)run the Register Performance to get Fmaxmake sure that the input clock frequency is less than or equal to the Fmax92. Design of Combinational Circuit10What is Combinational CircuitCombinational Circuit

6、ifOutputs at a specificed time are a function only of the at that timeexample of combinational circuitaddress decodersmultiplexersadders11The Simplest Combinational CircuitNothing can be simplest than 2 input AND Gate or 2 input OR Gate2 input AND/OR gate is as simple as 1+1 = 2Altera Device can not

7、 handle this so Simple Circuit122 input AND Gate Input WaveformOutput WaveformWhat happen ?But are you sure it is really so Simple ?13Take a closer lookLook at the Delay MatrixWhat is it means ?Assume the AND gate internaldelay is 0.2nsSimple Arithmetic CalculationFor Signal b :(Trace delay of b) +

8、AND gate internal delay = 8.1ns(Trace delay of b) + 0.2ns = 8.1ns(Trace delay of b) = 7.9nsFor Signal a :(Trace delay of a) + AND gate internal delay = 11.1ns(Trace delay of a) + 0.2ns = 11.1ns(Trace delay of a) = 10.9ns14續(xù)續(xù)Time : 0ns1-00-1001(Trace delay of b) = 7.9ns(Trace delay of a) = 10.9nsTime

9、 : 7.9ns01011Time : 8.1ns01111Time : 10.9ns01110Time : 11.1ns01010Output C change from “0” to “1” at 8.1nsA 3 ns Pulse generate (10.9-7.9 = 3ns)Output C change back from “1” to “0” as the final result15Key Point of Combinational DesignDesign with 2 input AND gate is not as easy as 1+1=2We need to co

10、nsider the Trace Delay and Gate Delay for Combinational Logic: The output of C is “0” : The output of C has a Glitch with 3ns widthIn this example, the 3ns Glitch is caused by Trace DelayEngineer Design Circuit work with not only16續(xù)續(xù)If you want your cirucit work RELIABLE, you need to consider This i

11、s not Altera Device ProblemThis is Design Problem17Go back to the First ExampleNow, we all know that a 2 input AND gate when involve with timing is not as easy as 1+1=218ReminderWhen Glitch will happenwhen more than one signals change at the same timeWhen you design combinational logicGlitch happen

12、is expectedIf you do not get one, you are lucky onlyA good engineer always remember that Combinational logic will have GLITCH 19Glitch issueIf we know how Glitch generatewe can calculate the exact time when the Glitch comes outwe can calculate the exact pulse width of the GlitchSpecial care must be

13、pay attention when the Combinational Logic output is used for of the Flip-Flop of the Flip-Flop of the Flip-Flopof the Latch20ConclusionCombinational Logic is easy to designWithout special care, Combinational Logic will give you unexpect Glitch and kill your design21PLD內部毛刺產生的原因我們在使用分立元件設計數字系統(tǒng)時，由于PC

14、B走線時，存在分布電感和電容，所以幾納秒的毛刺將被自然濾除。而在PLD內部決無分布電感和電容，所以在PLD/FPGA設計中，競爭和冒險問題將變的較為突出。22FPGA中的冒險現象信號在FPGA器件內部通過連線和邏輯單元時，都有一定的延時。延時的大小與連線的長短和邏輯單元的數目有關，同時還受器件的制造工藝、工作電壓、溫度等條件的影響。信號的高低電平轉換也需要一定的過渡時間。由于存在這兩方面因素，多路信號的電平值發(fā)生變化時，在信號變化的瞬間，組合邏輯的輸出有先后順序，并不是同時變化,往往會出現一些不正確的尖峰信號，這些尖峰信號稱為毛刺。如果一個組合邏輯電路中有毛刺出現，就說明該電路存在冒險。（與分立元件不同，由于PLD內部不存在寄生電容電感，這些毛刺將被完整的保留并向下一級傳遞，因此毛刺現象在PLD、FPGA設計中尤為突出）23消除毛刺的方法一消除毛刺的方法一一種方法是在輸出信號的保持時間內，用一定寬度的高電平脈沖與輸出信號做邏輯“與”運算，由此獲取輸出信號的電平值。下圖說明了這種方法，采樣脈沖信號從輸入引腳“SAMPLE”引入。從仿真波形上可以看出，毛刺信號出現在“TEST”引腳上，而“OUT”引腳上的毛刺已