第十二章后端設計

1、第十二章第十二章 后端設計后端設計 Outlines Backend Design Flow Floorplan Place minimal spacing to digital block; IO location nDie size issue nPin limited; Core limited nPower-Ground routing issue nPower ring width according to power analysis nPower strip/mesh spacing nPin placement and IO ring issue (will be talked

2、 in next class) nPad pitch vs. bounding rule; ESD; noise isolation; Die Size Issue cont. Determine the area for standard cells “Utilization” 70% ? 80%? 90%? nExtra space for clk tree synthesis nExtra space for scan chain nLayers for routing Hard Macro Placement Macros are generally placed around the

3、 peripheral I/O ring nA contiguous area for standard cells. nHigher freedom for your place-and-route tools during placement and routing of the standard cells The goal of macro placement is to: nReduce timing-critical paths between the macros and interfacing logic. nReduce interconnections in the fol

4、lowing order: n Chip I/O to macros n Macro to macro n Macro to standard cell blocks Power/Ground Development IR Drop and Electromigration nPower-net IR drop degrades the supply voltage level nExcessive current density in metal wire causes electromigration failure which breaks metal connection nMore

5、significant IR drop effect when Vdd gets smaller nHigher current density when metal wire width is smaller Vdd R Power/Ground Development-cont. Ring structure nPower rings around all layout blocks nMajor power trunks between layout blocks nDifficult to guarantee the worst IR drop Strap structure nSim

6、ple, easy for routing Mesh structure nEvenly distribute of IR nSpacing of Power strips consideration IR drop analysis nFix the problem in early stage P/G Structures Be Ware of Maximum Width Rule Maximum wire width limit due to thermal stress and local density rules Slotting vs. “bus” of thin wires D

7、isadvantage of slotting: nSlots may not be aligned with current flow nTrue IR drop not known until after slotting Especial happen for Power/Ground rings M 1 M 1 GND GND GND GND Commonly used for power/ground Placement Based on a given floorplan, determine the location of cells in a given netlist Goa

8、ls & objectives Routability Guarantee the router can complete the routing step (Global routing) Timing Minimize all critical net delays Minimize die size Make the chip as dense as possible Signal Integrity Check feasibility of routing after placement nLogic effort - for those paths with positive sla

9、ck, reduce cell size Congestion and Fix BeforeAfter Congestion areas Routing Complete power/ground/clock routing (clock tree synthesis) Complete detailed wire routing, conform wiring rule and order) Improve the density Minimize the layer changes Improve critical path and meet timing requirement Prod

10、uce a routed design free of DRC/LVS violations General Routing Flow Clock Tree Synthesis nAdd buffers/inverters, minimize clk skew and delay Post Placement Optimization (PPO) nFix setup violation Pre-Route Standard Cells nVDD/VSS rails on metal 1 nVerify PG connection and routing Route Group Net ncl

11、ocks nbus routing Post-Route CTO nFix clk skew and insertion delay Global Routing ncritical path nlong wire, interconnection Routing flow cont. Track Assignment & Detail Routing nWire connection Search & Repair (DRC/LVS) nfix routing violation (unconnected nets, shorts) Post Route Optimization nFix

12、timing Coarse LVS & DRC checking nmetal width, notch & gap checking Data Output nstream out: gds2 format nverilog out: hierarchy (PT) / non-hierarchy (for Hercules) nparasitic out: spef format (cell view) Clock Tree Synthesis Objective: nminimize clock skew noptimize clock buffers Basic CTS Flow & C

13、oncepts Clock Constraint Define: nClk source: root pin, target insertion delay, target transition time at clk port nClk endpoint: Synchronous pin, ignore/exclude pin nDriving cell, clk cell, delay cell: buffers, inverters, special clk cells nDRC: maximum transition delay, maximum net capacitance, ma

14、ximum fanout, clk number of buffer levels Clock Skew Global Skew and Local Skew nGlobal skew nGlobal skew is the clock arrival time difference between any two flip-flops. nLocal skew nLocal skew is the clock arrival time difference between two flip-flops that are adjacent through combinational logic

15、. Concept of Useful Skew Useful skew is a method of intentionally skewing a clock to improve the timing on a circuit. It is also commonly used in ECO Warning: Could cause problem in DFT scan insertion Use CTS for High-Fanout Net Synthesis High-fanout pins: rest, scan_en Need to balance high-fanout p

16、ins to guarantee the functionality Using CTS tool: high-fanout nets by inserting a balanced buffer tree nTo minimize both skew and insertion delay nBut should avoid using large buffers for power saving Large SoC Clock Distribution Partition the design to several blocks CTS for each block Clk tree ne

17、twork at top level External clock IP Core or Module Core Internal Clock Net PLL Global Clock Net H Tree for Top Clock Network Use big buffer to balance delay and clk skew nEqual distance, equal loads, equal driving ability Clock Distribution Case Study: Pentium Spines FROM PLL Kurd et al., A multigi

18、gahertz clocking scheme for the Pentium 4 microprocessor, JSSC2001 Clock Distribution Case Study: Intels Itanium H Tree Clocking Tam et al., Clock generation and distribution for the first IA-64 microprocessor, JSSC 2000 Issues Large amount of clock buffers added on clock tree nPower consumption nNo

19、ise to supply lines Reduce power consumption nWide wire widths nClock gating cell placement nLimitation of using large clock buffer cells Reduce noise nSpecial clock buffer cells with decoupling capacitor Extraction When complete detailed route nWrite out the hierarchical netlist and parasitic for b

20、ack annotation Data management on huge file of extracted parasitic data Accurate RC and timing model for nanometer design nWidth and spacing dependence nResistance shielding nLocal density effect SDF Back Annotation Used in cell-based design flow Performs delay calculation on parasitic RCs in interc

21、onnect wires DSPF - Detailed Standard Parasitic Format SPEF Standard Parasitic exchange Format SDF - Standard Delay Format used for post- layout simulation nCan be convert from PrimeTime Physical Verification DRC - Design Rule check nVerify the manufacturing rules, example: nInternal layer checks nW

22、ide metal checks nMetal slotting needed for wide metal nLayer-to-layer checks nDFM/DFY nExample: Antenna Rule Check LVS Layout vs. Schematics nCompare layout to schematics- every cell and net DRC Trends and Challenge 75% time on metal layer and via check ERC-type checks increasing Rise of pre-tapeou

23、t DFM utilities Number of Design Rules by ProcessNumber of Design Rules by Process NodeNode 0 200 400 600 800 350 250 180 150 130 90 (nm)(nm) LVS Layout vs. Schematic (LVS) nCheck physical layout against functional gate level schematic to ensure all intended connectivity has been maintained nSteps:

24、nExtract the netlist from layout (GDSII) nCompare the netlist with the one after routing and optimization Hints: nMost of LVS errors are caused by manual layout or congestion n“Virtual connect” (connected by text) could cause a killer failure Signal Integrity Signal Integrity is the ability of a sig

25、nal to generate correct response in a circuit nSignal has digital levels at appropriate and required voltage levels at required instants of time Crosstalk, IR Drop, Electromigration Layout Parasitic vs. Circuit Performance Interconnect parasitic resistors, capacitors and inductors cause extra timing

26、 delay Additional power consumption caused by parasitic RC Inter-wire capacitances cause coupling noise and will dominate interconnect wire delays Parasitic resistances in power supply cause voltage drop and may degrade circuit performance Higher current density in power net may cause electromigrati

27、on failure Inductance Effects Inductive coupling effect is significant for long interconnects and for very fast signal edge rate Inductive coupling is negligible at short trace interconnects, since the edge trace is long compared to the flight time of the signal Inductance extraction and simulation

28、are more difficult than capacitance C L Crosstalk Analysis Definition nAggressor: generating crosstalk nVictim: receiving crosstalk Timing sensitive nCrosstalk analysis consisting signal transition timing window can eliminate pessimistic delay calculation nThe crosstalk spike is related to capacitan

29、ce value and the victim driver impedance Crosstalk Analysis cont. Timing sensitive Crosstalk Prevention Prevent crosstalk from synthesis stage nMinimize the driving size on those non-critical path to reduce the number of aggressors nApply max transition time (set_max_transition) in physical synthesi

30、s/placement to avoid long nets Crosstalk Prevention cont. From routing stage nEffective spacing between noise region and quite region nShielding between critical paths Crosstalk Prevention cont. From routing stage cont. nBuffer insertion nInserted buffer breaks up the coupling capacitance of long wi

31、re Crosstalk Prevention cont. From routing stage cont. nBuffer sizing nIncrease the driver size of victim nDecrease the driver size of aggressor nTrack reordering nTrack reordering is based on timing window Crosstalk Prevention cont. For inductance crosstalk nCoplanar Shields nReference Plan nStagge

32、r Inverter/Buffer Electromigration Effects The electrons flow through the wires and collide w/metal atoms, producing a force that causes the wires to break Caused by the high current densities and high frequencies going through the long, very thin metal wires MTTF (Mean Time To Failure) increases wh

33、en current density and temperature increase Can be eliminated by using the appropriate wire sizing Open Circuit Short circuit Fix EM Controlling current density to limit electromigration failure is needed in design and verification Layout optimization: nIncrease the power line width, layer nIncrease

34、 the power pads nIncrease the connection Issues nMore metal (add 8% cost per layer) nLarger, slower designs (grow in x and y) Other Considerations ESD (will be talked in next class) Package vs. performance (will be talked in next class) DFM/DFY DFM/DFY 90nm and below technologies challenges in yield

35、 DFM Design for Manufacturability DFY Design for Yield DFM and DFY DFM is the management of technology constraints (sizing rules) applied to the layout A manufacturable design however is not necessarily a high-robust or high-yielding design. DFY, as part of Design for Manufacturability, concentrates

36、 on the development and quality of the circuit design in the pre- and post-layout phase. DFY is the management of design sensitivities to the manufacturing process and helps to guarantee high-yielding devices DFM/DFY Methodology Optimal resolution enhancement technology (RET) nMask and exposure nOpt

37、ical Proximity correction (OPC) nPhase Shaft Mask (PSM) Yield enhancement and optimization technology nDFM rules implementation nTo overcome limits of OPC nYield checking during the layout stage nSupported by EDA tools Why Need RET? Wavelength used vs process generation Design for Manufacturing Not

38、all the things can be done by mask and exposure: nCorrections are not complete nSome designs cannot be built at all with certain RET technologies nOf those that CAN be built, some are more manufacturable after RET than others DFM/DFY-driven routing nOPC-driven routing nPSC-driven placement nDFM rule

39、 implementation DFM/Y Rules Limit the use of minimal poly-enclosed gates, minimally enclosed vias and singly contacted lines nBetter yield nLess resistance Example: Via Void rules - doubled vias Current DFM/Y Design Flow Supported Load Design Perform antenna fixes Add contacts/via Metal Fill & Slott

40、ing Verify LVS and DRC Why Need Double Vias? Copper processing causes new problems for vias nVoids in Cu migrate under thermal stress towards vias nIf enough voids migrate to a via it can cause failure nWorse at 90/65nm due to increased stress of smaller via Voids can migrate long distances 10 micro

41、ns Voids can migrate around corners Yield vs. Area Antenna Rules Antenna rules have nothing to do with traditional definition of antenna nReally a collector of static charge, not electromagnetic radiation Antenna problem only happens during manufacturing nPlasma-based process for etching, oxide deposition nPlasma etcher include a voltage into floating wire, stressing the thin gate