基于FPGA的數(shù)字系統(tǒng)設(shè)計實驗3控制液晶顯示屏顯示字符OK

1、Jian程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity lcd isport(clk, reset : in bit;SF_D : out

2、bit_vector(3 downto 0);LCD_E, LCD_RS, LCD_RW, SF_CE0 : out bit;LED : out bit_vector(7 downto 0) );end lcd;architecture behavior of lcd istype tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);signal tx_state : tx_sequence := done;signal tx_byte : bit_vector(7 downto 0

3、);signal tx_init : bit := 0;type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done);signal init_state : init_sequence := idle;signal init_init, init_done : bit := 0;signal i : integer range 0 to 750000 := 0;signal i2 : integer range 0 to 2000 := 0;signal i3 : in

4、teger range 0 to 82000 := 0;signal SF_D0, SF_D1 : bit_vector(3 downto 0);signal LCD_E0, LCD_E1 : bit;signal mux : bit;type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr, char_f, char_p, char_g, char_a, done);signal cur_state : display_state := init;beginL

5、ED = tx_byte; -for diagnostic purposesSF_CE0 = 1; -disable intel strataflashLCD_RW = 0; -write only-The following with statements simplify the process of adding and removing states.-when to transmit a command/data and when not towith cur_state selecttx_init = 0 when init | pause | done,1 when others

6、;-control the buswith cur_state selectmux = 1 when init,0 when others;-control the initialization sequencewith cur_state selectinit_init = 1 when init,0 when others;-register selectwith cur_state selectLCD_RS = 0 when function_set|entry_set|set_display|clr_display|set_addr,1 when others;-what byte t

7、o transmit to lcd-refer to datasheet for an explanation of these valueswith cur_state selecttx_byte = 00101000 when function_set,00000110 when entry_set,00001100 when set_display,00000001 when clr_display,10000000 when set_addr,01001010 when char_J,01001001 when char_I,01000001 when char_A,01001110

8、when char_N,00000000 when others;-main state machinedisplay: process(clk, reset)beginif(reset=1) thencur_state if(init_done = 1) thencur_state = function_set;elsecur_state if(i2 = 2000) thencur_state = entry_set;elsecur_state if(i2 = 2000) thencur_state = set_display;elsecur_state if(i2 = 2000) then

9、cur_state = clr_display;elsecur_state i3 = 0;if(i2 = 2000) thencur_state = pause;elsecur_state if(i3 = 82000) thencur_state = set_addr;i3 = 0;elsecur_state = pause;i3 if(i2 = 2000) thencur_state = char_J;elsecur_state if(i2 = 2000) thencur_state = char_I;elsecur_state if(i2 = 2000) thencur_state = c

10、har_A;elsecur_state if(i2 = 2000) thencur_state = char_N;elsecur_state if(i2 = 2000) thencur_state = done;elsecur_state cur_state = done;end case;end if;end process display;with mux selectSF_D = SF_D0 when 0, -transmitSF_D1 when others; -initializewith mux selectLCD_E = LCD_E0 when 0, -transmitLCD_E

11、1 when others; -initialize-specified by datasheettransmit : process(clk, reset, tx_init)beginif(reset=1) thentx_state -40nsLCD_E0 = 0;SF_D0 = tx_byte(7 downto 4);if(i2 = 2) thentx_state = high_hold;i2 = 0;elsetx_state = high_setup;i2 -230nsLCD_E0 = 1;SF_D0 = tx_byte(7 downto 4);if(i2 = 12) thentx_st

12、ate = oneus;i2 = 0;elsetx_state = high_hold;i2 LCD_E0 = 0;if(i2 = 50) thentx_state = low_setup;i2 = 0;elsetx_state = oneus;i2 LCD_E0 = 0;SF_D0 = tx_byte(3 downto 0);if(i2 = 2) thentx_state = low_hold;i2 = 0;elsetx_state = low_setup;i2 LCD_E0 = 1;SF_D0 = tx_byte(3 downto 0);if(i2 = 12) thentx_state =

13、 fortyus;i2 = 0;elsetx_state = low_hold;i2 LCD_E0 = 0;if(i2 = 2000) thentx_state = done;i2 = 0;elsetx_state = fortyus;i2 LCD_E0 = 0;if(tx_init = 1) thentx_state = high_setup;i2 = 0;elsetx_state = done;i2 = 0;end if;end case;end if;end process transmit;-specified by datasheetpower_on_initialize: proc

14、ess(clk, reset, init_init) -power on initialization sequencebeginif(reset=1) theninit_state = idle;init_done init_done = 0;if(init_init = 1) theninit_state = fifteenms;i = 0;elseinit_state = idle;i init_done = 0;if(i = 750000) theninit_state = one;i = 0;elseinit_state = fifteenms;i SF_D1 = 0011;LCD_

15、E1 = 1;init_done = 0;if(i = 11) theninit_state=two;i = 0;elseinit_state=one;i LCD_E1 = 0;init_done = 0;if(i = 205000) theninit_state=three;i = 0;elseinit_state=two;i SF_D1 = 0011;LCD_E1 = 1;init_done = 0;if(i = 11) theninit_state=four;i = 0;elseinit_state=three;i LCD_E1 = 0;init_done = 0;if(i = 5000

16、) theninit_state=five;i = 0;elseinit_state=four;i SF_D1 = 0011;LCD_E1 = 1;init_done = 0;if(i = 11) theninit_state=six;i = 0;elseinit_state=five;i LCD_E1 = 0;init_done = 0;if(i = 2000) theninit_state=seven;i = 0;elseinit_state=six;i SF_D1 = 0010;LCD_E1 = 1;init_done = 0;if(i = 11) theninit_state=eigh

17、t;i = 0;elseinit_state=seven;i LCD_E1 = 0;init_done = 0;if(i = 2000) theninit_state=done;i = 0;elseinit_state=eight;i init_state = done;init_done = 1;end case;end if;end process power_on_initialize;end behavior;源程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOG

18、IC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity lcd isport(clk, reset : in bit;SF_D : out bit_vector(3 downto 0);LCD_E, LCD_RS, LCD_RW, SF_CE0 : out bit;LED : out bit_vector(7 downto

19、 0) );end lcd;architecture behavior of lcd istype tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);signal tx_state : tx_sequence := done;signal tx_byte : bit_vector(7 downto 0);signal tx_init : bit := 0;type init_sequence is (idle, fifteenms, one, two, three, four, f

20、ive, six, seven, eight, done);signal init_state : init_sequence := idle;signal init_init, init_done : bit := 0;signal i : integer range 0 to 750000 := 0;signal i2 : integer range 0 to 2000 := 0;signal i3 : integer range 0 to 82000 := 0;signal SF_D0, SF_D1 : bit_vector(3 downto 0);signal LCD_E0, LCD_

21、E1 : bit;signal mux : bit;type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr, char_f, char_p, char_g, char_a, done);signal cur_state : display_state := init;beginLED = tx_byte; -for diagnostic purposesSF_CE0 = 1; -disable intel strataflashLCD_RW = 0; -wri

22、te only-The following with statements simplify the process of adding and removing states.-when to transmit a command/data and when not towith cur_state selecttx_init = 0 when init | pause | done,1 when others;-control the buswith cur_state selectmux = 1 when init,0 when others;-control the initializ

23、ation sequencewith cur_state selectinit_init = 1 when init,0 when others;-register selectwith cur_state selectLCD_RS = 0 when function_set|entry_set|set_display|clr_display|set_addr,1 when others;-what byte to transmit to lcd-refer to datasheet for an explanation of these valueswith cur_state select

24、tx_byte = 00101000 when function_set,00000110 when entry_set,00001100 when set_display,00000001 when clr_display,10000000 when set_addr,01000110 when char_f,01010000 when char_p,01000111 when char_g,01000001 when char_a,00000000 when others;-main state machinedisplay: process(clk, reset)beginif(rese

25、t=1) thencur_state if(init_done = 1) thencur_state = function_set;elsecur_state if(i2 = 2000) thencur_state = entry_set;elsecur_state if(i2 = 2000) thencur_state = set_display;elsecur_state if(i2 = 2000) thencur_state = clr_display;elsecur_state i3 = 0;if(i2 = 2000) thencur_state = pause;elsecur_sta

26、te if(i3 = 82000) thencur_state = set_addr;i3 = 0;elsecur_state = pause;i3 if(i2 = 2000) thencur_state = char_f;elsecur_state if(i2 = 2000) thencur_state = char_p;elsecur_state if(i2 = 2000) thencur_state = char_g;elsecur_state if(i2 = 2000) thencur_state = char_a;elsecur_state if(i2 = 2000) thencur

27、_state = done;elsecur_state cur_state = done;end case;end if;end process display;with mux selectSF_D = SF_D0 when 0, -transmitSF_D1 when others; -initializewith mux selectLCD_E = LCD_E0 when 0, -transmitLCD_E1 when others; -initialize-specified by datasheettransmit : process(clk, reset, tx_init)begi

28、nif(reset=1) thentx_state -40nsLCD_E0 = 0;SF_D0 = tx_byte(7 downto 4);if(i2 = 2) thentx_state = high_hold;i2 = 0;elsetx_state = high_setup;i2 -230nsLCD_E0 = 1;SF_D0 = tx_byte(7 downto 4);if(i2 = 12) thentx_state = oneus;i2 = 0;elsetx_state = high_hold;i2 LCD_E0 = 0;if(i2 = 50) thentx_state = low_set

29、up;i2 = 0;elsetx_state = oneus;i2 LCD_E0 = 0;SF_D0 = tx_byte(3 downto 0);if(i2 = 2) thentx_state = low_hold;i2 = 0;elsetx_state = low_setup;i2 LCD_E0 = 1;SF_D0 = tx_byte(3 downto 0);if(i2 = 12) thentx_state = fortyus;i2 = 0;elsetx_state = low_hold;i2 LCD_E0 = 0;if(i2 = 2000) thentx_state = done;i2 =

30、 0;elsetx_state = fortyus;i2 LCD_E0 = 0;if(tx_init = 1) thentx_state = high_setup;i2 = 0;elsetx_state = done;i2 = 0;end if;end case;end if;end process transmit;-specified by datasheetpower_on_initialize: process(clk, reset, init_init) -power on initialization sequencebeginif(reset=1) theninit_state

31、= idle;init_done init_done = 0;if(init_init = 1) theninit_state = fifteenms;i = 0;elseinit_state = idle;i init_done = 0;if(i = 750000) theninit_state = one;i = 0;elseinit_state = fifteenms;i SF_D1 = 0011;LCD_E1 = 1;init_done = 0;if(i = 11) theninit_state=two;i = 0;elseinit_state=one;i LCD_E1 = 0;ini

32、t_done = 0;if(i = 205000) theninit_state=three;i = 0;elseinit_state=two;i SF_D1 = 0011;LCD_E1 = 1;init_done = 0;if(i = 11) theninit_state=four;i = 0;elseinit_state=three;i LCD_E1 = 0;init_done = 0;if(i = 5000) theninit_state=five;i = 0;elseinit_state=four;i SF_D1 = 0011;LCD_E1 = 1;init_done = 0;if(i

33、 = 11) theninit_state=six;i = 0;elseinit_state=five;i LCD_E1 = 0;init_done = 0;if(i = 2000) theninit_state=seven;i = 0;elseinit_state=six;i SF_D1 = 0010;LCD_E1 = 1;init_done = 0;if(i = 11) theninit_state=eight;i = 0;elseinit_state=seven;i LCD_E1 = 0;init_done = 0;if(i = 2000) theninit_state=done;i =

34、 0;elseinit_state=eight;i init_state = done;init_done = 1;end case;end if;end process power_on_initialize;end behavior;第三種 verilog 該程序?qū)崿F(xiàn)對 SPARTAN3E 上2x16 LCD 的初始化及各種初始設(shè)置，最后輸出“OK”字樣 timescale 1ns / 1ps / / Company: / Engineer: / / Create Date: 17:43:15 10/03/2009 / Design Name: / Module Name: lcd_dis

35、p_ok / Project Name: / Target Devices: / Tool versions: / Description: / / Dependencies: / / Revision: / Revision 0.01 - File Created / Additional Comments: / / module lcd_disp_ok(clk,reset,lcd_rs,lcd_rw,lcd_e,lcd_d,flash_ce); input clk; input reset; output lcd_rs; output lcd_rw; output lcd_e; outpu

36、t 3:0 lcd_d; output flash_ce; reg lcd_rs,lcd_e; reg 3:0 lcd_d; assign flash_ce = 1; assign lcd_rw = 0; reg 19:0 delay_count; reg 19:0 num_count; parameter state1 = 6b000001; parameter state2 = 6b000010; parameter state3 = 6b000011; parameter state4 = 6b000100; parameter state5 = 6b000101; parameter

37、state6 = 6b000110; parameter state7 = 6b000111; parameter state8 = 6b001000; parameter state9 = 6b001001; parameter state10 = 6b001010; parameter state11 = 6b001011; parameter state12 = 6b001100; parameter state13 = 6b001101; parameter state14 = 6b001110; parameter state15 = 6b001111; parameter stat

38、e16 = 6b010000; parameter state17 = 6b010001; parameter state18 = 6b010010; parameter state19 = 6b010011; parameter state20 = 6b010100; parameter state21 = 6b010101; parameter state22 = 6b010110; parameter state23 = 6b010111; parameter state24 = 6b011000; parameter state25 = 6b011001; parameter stat

39、e26 = 6b011010; parameter state27 = 6b011011; parameter state28 = 6b011100; parameter state29 = 6b011101; parameter state30 = 6b011110; parameter state31 = 6b011111; parameter state32 = 6b100000; parameter state33 = 6b100001; parameter state34 = 6b100010; parameter state35 = 6b100011; parameter stat

40、e36 = 6b100100; parameter state37 = 6b100101; parameter state38 = 6b100110; parameter state39 = 6b100111; parameter state40 = 6b101000; parameter state41 = 6b101001; parameter state42 = 6b101010; parameter state43 = 6b101011; parameter state44 = 6b101100; parameter state45 = 6b101101; parameter state46 = 6b101110; parameter state47 = 6b101111; parameter state48 = 6b110000; parameter state49 = 6b110001; parameter state50 = 6b110010; parameter state51 = 6b110011; parameter state52 = 6b110100; parameter state53 = 6b110101; parameter state54 = 6b110110; parameter state55 = 6b110111; param