實驗5時序邏輯電路實驗

1、實驗5 時序邏輯電路實驗1.設(shè)計一個完整的時序邏輯電路，并用maxplus進(jìn)行仿真，將結(jié)果下載到實驗箱中，測試電路的正確性。要求：設(shè)計一個24進(jìn)制計數(shù)電路，數(shù)字顯示在數(shù)碼管上，有手動和自動兩種模式，在自動模式下每隔1秒從00顯示到23然后循環(huán)，在手動模式下，每按一次按鍵計數(shù)值加1。每次從23跳到00時，響鈴提示。2. 應(yīng)包含vhdl源程序，詳細(xì)的設(shè)計報告，對程序，仿真結(jié)果，實驗箱運行結(jié)果（圖片貼到報告中）進(jìn)行詳盡的分析24進(jìn)制器（很重要）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity

2、 hours24 isport(clk,x:in std_logic; o_1:out std_logic_vector(3 downto 0); o_2:out std_logic_vector(3 downto 0); w:out std_logic; bee:out std_logic );end hours24;architecture g3 of hours24 issignal count_1,count_2:std_logic_vector(3 downto 0);beginprocess(clk,x)beginif(clk'event and clk = '1&

3、#39; )then if(count_2=2 and count_1=3)then count_2<="0000" count_1<="0000" bee<='1' elsif(count_1=9)then count_2<=count_2+1; count_1<="0000" else count_2<=count_2; count_1<=count_1+1;bee<='0' end if;end if;end process;w<=x;o_2&

4、lt;=count_2 ;o_1<=count_1;end g3;分頻（重要）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;entity fenpin isport(clk:in std_logic; sd:in std_logic; en:in std_logic; clk_f:out std_logic; sd_1:out std_logic; wx:out std_logic; en_1:out std_logic );en

5、d fenpin;architecture g1 of fenpin issignal clk_div:std_logic;beginprocess(clk) variable count:integer range 0 to 4;beginif(clk'event and clk = '1')then if(count=3)then count:=0; else count:=count+1; if( count<2)thenclk_div<= '1'else clk_div <= '0'end if;end if;

6、end if;end process;clk_f<=clk_div;en_1<=en;sd_1<=sd;wx<=clk;end g1;按鍵消除抖動（重要）library ieee;use ieee.std_logic_1164.all;entity xiaodou isport( clk,key,xuan: in std_logic; dmc,clk_out,xuan_out: out std_logic );end xiaodou;architecture g0 of xiaodou issignal r,s,qr,qs,d1,d2,q1,q2,d3,d4,q3,q4

7、,cp:std_logic;beginprocess(clk)beginif(clk'event and clk='1')then d1<=key; d2<=d1; q2<=d2; d3<=qr; d4<=d3; q4<=d4;end if; r<=(not d2)and (not q2); s<=d2 and q2; qr<=r nor qs; qs<=s nor qr; cp<=d4 and (not q4); dmc<=cp;end process;clk_out<=clk;xuan_o

8、ut<=xuan;end g0;選擇器：library ieee;use ieee.std_logic_1164.all;entity xuanze isport(clk_wx,cp,en_2,div:in std_logic; utter_1:out std_logic; utter_2:out std_logic );end xuanze ;architecture g2 of xuanze isbeginprocess(div,cp,en_2)begin if(en_2='0')thenutter_1<=div;else utter_1<=cp;end

9、if;end process;utter_2<=clk_wx;end g2;譯碼器：library ieee;use ieee.std_logic_1164.all;entity yima isport(a:in std_logic_vector(3 downto 0); b:out std_logic_vector(6 downto 0); bee_in,xx:in std_logic; bee_out,ww:out std_logic );end yima;architecture g5 of yima isbeginprocess(a)begincase a iswhen"

10、;0000"=> b <="0111111" when"0001"=> b <="0000110" when"0010"=> b <="1011011" when"0011"=> b <="1001111" when"0100"=> b <="1100110" when"0101"=> b <="11011

11、01" when"0110"=> b <="1111101" when"0111"=> b <="0000111" when"1000"=> b <="1111111" when"1001"=> b <="1101111" when others=> b <="1111111"end case;end process;bee_out<=bee

12、_in;ww<=xx;end g5;選位器：library ieee;use ieee.std_logic_1164.all;entity code isport(c:in std_logic_vector(3 downto 0); d:in std_logic_vector(3 downto 0); ei:in std_logic; bee_in:in std_logic; bee_out,xw:out std_logic; f: out std_logic_vector(3 downto 0) );end code ;architecture g4 of code isbeginpr

13、ocess(ei,c,d)beginif(ei='0')thenf<=c;else f<=d;end if;end process;bee_out<=bee_in;xw<=ei;end g4;頂層文件：（格式很重要）library ieee;use ieee.std_logic_1164.all;entity dingcen isport(clk,key,xuan:in std_logic; bee,s:out std_logic; n:out std_logic_vector(6 downto 0) );end dingcen;architecture

14、 struct of dingcen iscomponent xiaodou isport( clk,key,xuan: in std_logic; dmc,clk_out,xuan_out: out std_logic );end component xiaodou;component fenpin isport(clk:in std_logic; sd:in std_logic; en:in std_logic; clk_f:out std_logic; sd_1:out std_logic; wx:out std_logic; en_1:out std_logic );end compo

15、nent fenpin;component xuanze isport(clk_wx,cp,en_2,div:in std_logic; utter_1:out std_logic; utter_2:out std_logic );end component xuanze;component hours24 isport(clk,x:in std_logic; o_1:out std_logic_vector(3 downto 0); o_2:out std_logic_vector(3 downto 0); w:out std_logic; bee:out std_logic );end c

16、omponent hours24;component code isport(c:in std_logic_vector(3 downto 0); d:in std_logic_vector(3 downto 0); ei:in std_logic; bee_in:in std_logic; bee_out,xw:out std_logic; f: out std_logic_vector(3 downto 0) );end component code;component yima isport(a:in std_logic_vector(3 downto 0); b:out std_log

17、ic_vector(6 downto 0); bee_in,xx:in std_logic; bee_out,ww:out std_logic );end component yima;signal u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13:std_logic;signal ym1,ym2,ym3:std_logic_vector(3 downto 0);beginh1:xiaodou port map(clk=>clk,key=>key,xuan=>xuan,clk_out=>u1,dmc=>u2,xuan_out=>u3);h2:fenpin port map(clk=>u1,sd=>u2,en=>u3,clk_f=>u4,sd_1=>u5,wx=>u6,en_1=>u7);h3:xuanze port map(clk_wx=>u6,cp=>u5,en_2=>u7,div=>u4,utter_1=>u8,utter_2=>u9);h4:hours24 port map(clk