基于eda交通燈控制課程設(shè)計

1、目 錄第一章 設(shè)計內(nèi)容與要求. 21.1、設(shè)計要求.21.2、對題目的理解.2第二章 設(shè)計思路. 32.1、分模塊設(shè)計. 32.2、模塊設(shè)計思路. 3 1、jtdkz. 3 2、xskz. 3 3、cnt45s. 3 4、cnt25s. 3 5、cnt05s. 3 6、輸入輸出模塊. 3第三章設(shè)計模塊具體實現(xiàn).43.1、jtdkz.43.2、xskz.63.3、cnt45s.73.4、cnt25s.103.5、cnt05s.13第四章 整體組裝與測試.154.1、自動轉(zhuǎn)換出來的源程序.154.2、主原理圖.194.3、功能說明.19第五章 設(shè)計總結(jié).205.4、設(shè)計總結(jié).20附錄1 參考文獻.

2、21第一章 設(shè)計內(nèi)容與要求一、設(shè)計要求設(shè)計一個由一條支干道和一條主干道的匯合點形成的十字交叉路口的交通燈控制器，主要要求如下：1.主、支干道各設(shè)有一個綠、黃、紅指示燈，兩個顯示數(shù)碼管。2.主干道處于常允許狀態(tài)，兩支干道有車來才允許通行。3.當(dāng)主、支干道有車時，兩者交替通行，主干道每次放行45s，支干道每次放行25s，在每次由亮綠燈變成亮紅燈轉(zhuǎn)換過程中，要亮5s黃燈作為過渡，并進行減計時顯示。二、對題目的理解（一）、交通燈的功能是實現(xiàn)一個交叉口的通車控制，交通燈顯示有以下4種狀態(tài)：1.主干道綠燈，支干道紅燈；2.主干道綠燈，支干道黃燈；3.主干道紅燈，支干道綠燈；4.主干道黃燈，支干道綠燈。（二

3、）、支干道沒車時，主干道一直亮綠燈；主干道沒車時，主干道和支干道交替亮綠燈；主干道和支干道都有車時同樣交替亮紅綠燈。在紅綠燈交替時亮5s黃燈。第二章 設(shè)計思路一、分模塊設(shè)計1、紅、綠、黃燈控制模塊，模塊名jtdkz；2、倒計時傳輸、控制模塊xskz；3、倒計時45scnt45s；4、倒計時25scnt25s；5、倒計時5scnt05s。6、輸入、輸出。二、模塊設(shè)計思路1、jtdkz根據(jù)交通燈顯示有4種狀態(tài)，可以采用case語句設(shè)置選擇4種狀態(tài)。設(shè)置3個輸入：clk(時鐘脈沖)、sb(支干道傳感器)、sm(主干道傳感器)。2、xskz根據(jù)需要交通燈顯示的不同數(shù)倒計時據(jù)設(shè)置4個輸入使能信號：en4

4、5(45s倒計時使能信號)、en25(25s倒計時使能信號)、en05(5s倒計時使能信號)；再設(shè)置5個倒計時計數(shù)數(shù)據(jù)輸入信號將此時倒計時數(shù)據(jù)輸出：ain45m、ain45b、ain25m、ain25b、ain05；2個輸出信號使數(shù)碼管顯示正在倒計時的時間。3、cnt45s根據(jù)倒計時計數(shù)的要求設(shè)置3個輸入信號：clk(計數(shù)脈沖)、en45(計數(shù)使能)、sb(支干道傳感器信號)；2個輸出dout45m、dout45b，分別用于主、支干道顯示。 4、cnt25s根據(jù)倒計時計數(shù)的要求設(shè)置4個輸入信號：clk(計數(shù)脈沖)、en45(計數(shù)使能)、sm(主干道傳感器信號)、sb(支干道傳感器信號)；2個輸

5、出dout25m、dout25b，分別用于主、支干道顯示。 5、cnt05s根據(jù)倒計時計數(shù)的要求設(shè)置3個輸入信號：clk(計數(shù)脈沖)、en05b(計數(shù)使能)、en05m(計數(shù)使能)；1個輸出dout05，用于主、支干道顯示。 6、輸入輸出模塊，3個輸入分別為：clk、sb、sm，2個輸出分別為dout17.0、dout27.0。第三章設(shè)計模塊具體實現(xiàn)一、jtdkz簡單思路：假設(shè)4種狀態(tài)分別為：a、b、c、d，在clk上升沿來時，根據(jù)sb、sm狀態(tài)判斷交通處于何種狀態(tài)，該狀態(tài)輸出什么信號。設(shè)計的原理圖模塊：設(shè)計源程序：library ieee;use ieee.std_logic_1164.al

6、l;entity jtdkz is port(clk,sm,sb:in std_logic; mr,my0,mg0,br,by0,bg0:out std_logic);end entity jtdkz;architecture art of jtdkz is type state_type is(a,b,c,d); signal state:state_type; begin cnt:process(clk)is variable s:integer range 0 to 45; variable clr,en:bit; begin if(clk'event and clk='

7、1')then if clr='0'then s:=0; elsif en='0'then s:=s; else s:=s+1; end if; case state is when a=>mr<='0'my0<='0'mg0<='1'br<='1'by0<='0'bg0<='0' if(sb and sm)='1' then if s=45 then state<=b;clr:='0&#

8、39;en:='0' else state<=a;clr:='1'en:='1' end if; elsif(sb and(not sm)='1'then state<=b;clr:='0'en:='0' else state<=a;clr:='1'en:='1' end if; when b=>mr<='0'my0<='1'mg0<='0'br<='1'b

9、y0<='0'bg0<='0' if s=5 then state<=c;clr:='0'en:='0' else state<=b;clr:='1'en:='1' end if; when c=>mr<='1'my0<='0'mg0<='0'br<='0'by0<='0'bg0<='1' if(sm and sb)='1'

10、then if s=25 then state<=d;clr:='0'en:='0' else state<=c;clr:='1'en:='1' end if; elsif sb='0' then state<=d;clr:='0'en:='0' else state<=c;clr:='1'en:='1' end if; when d=>mr<='1'my0<='0'mg0<

11、;='0'br<='0'by0<='1'bg0<='0' if s=5 then state<=a;clr:='0'en:='0' else state<=d;clr:='1'en:='1' end if; end case; end if; end process cnt;end architecture art;設(shè)計仿真的截圖：二、xskz簡單設(shè)計思路：根據(jù)en45、en25、en05m、en05b的信號以及3個倒計時計數(shù)器的計數(shù)狀態(tài)

12、決定輸出3個倒計時計數(shù)器中某個的狀態(tài)輸出。原理圖模塊：設(shè)計源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cskz is port(ina:in std_logic; outa:out std_logic);end entity cskz;architecture art of cskz is begin process(ina)is begin if ina='1'then outa<='1' else outa<='0&

13、#39; end if; end process;end architecture art;設(shè)計仿真的截圖：三、cnt45s 簡單思路：clk上升沿到來時，若到計時使能信號和sb信號有效，cnt45s開始計數(shù)，并將輸入狀態(tài)通過dout45m、dout45b分別輸出到主、支干道顯示。 設(shè)計的原理圖模塊： 設(shè)計源程序：3library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt45s is port(sb,clk,en45:in std_logic; dout45m,dout45b:out

14、std_logic_vector(7 downto 0);end cnt45s;architecture art of cnt45s is signal cnt6b:std_logic_vector(5 downto 0); begin process(sb,clk,en45) is begin if sb='0' then cnt6b<=cnt6b-cnt6b-1; elsif(clk'event and clk='1')then if en45='1'then cnt6b<=cnt6b+1; elsif en45='

15、;0'then cnt6b<=cnt6b-cnt6b-1; end if;end if;end process;process(cnt6b)isbegincase cnt6b iswhen"000000"=>dout45m<="01000101"dout45b<="01010000"when"000001"=>dout45m<="01000100"dout45b<="01001001"when"000010"

16、;=>dout45m<="01000011"dout45b<="01001000"when"000011"=>dout45m<="01000010"dout45b<="01000111"when"000100"=>dout45m<="01000001"dout45b<="01000110"when"000101"=>dout45m<="010

17、00000"dout45b<="01000101"when"000110"=>dout45m<="00111001"dout45b<="01000100"when"000111"=>dout45m<="00111000"dout45b<="01000011"when"001000"=>dout45m<="00110111"dout45b<=&quo

18、t;01000010"when"001001"=>dout45m<="00110110"dout45b<="01000001"when"001010"=>dout45m<="00110101"dout45b<="01000000"when"001011"=>dout45m<="00110100"dout45b<="01101001"when"0

19、01100"=>dout45m<="00110011"dout45b<="00111000"when"001101"=>dout45m<="00110010"dout45b<="00110111"when"001110"=>dout45m<="00110001"dout45b<="00110110"when"001111"=>dout45m<

20、="00110000"dout45b<="00110101"when"010000"=>dout45m<="00101001"dout45b<="00110100"when"010001"=>dout45m<="00101000"dout45b<="00110011"when"010010"=>dout45m<="00100111"dout45

21、b<="00110010"when"010011"=>dout45m<="00100110"dout45b<="00110001"when"010100"=>dout45m<="00100101"dout45b<="00110000"when"010101"=>dout45m<="00100100"dout45b<="00101001"w

22、hen"010110"=>dout45m<="00100011"dout45b<="00101000"when"010111"=>dout45m<="00100010"dout45b<="00100111"when"011000"=>dout45m<="00100001"dout45b<="00100110"when"011001"=>d

23、out45m<="00100000"dout45b<="00100101"when"011010"=>dout45m<="00011001"dout45b<="00100100"when"011011"=>dout45m<="00011000"dout45b<="00100011"when"011100"=>dout45m<="00010111&q

24、uot;dout45b<="00100010"when"011101"=>dout45m<="00010110"dout45b<="00100001"when"011110"=>dout45m<="00010101"dout45b<="00100000"when"011111"=>dout45m<="00010100"dout45b<="00011

25、001"when"100000"=>dout45m<="00010011"dout45b<="00011000"when"100001"=>dout45m<="00010010"dout45b<="00010111"when"100010"=>dout45m<="00010001"dout45b<="00010110"when"100011&q

26、uot;=>dout45m<="00010000"dout45b<="00010101"when"100100"=>dout45m<="00001001"dout45b<="00010100"when"100101"=>dout45m<="00001000"dout45b<="00010011"when"100110"=>dout45m<="

27、00000111"dout45b<="00010010"when"100111"=>dout45m<="00000110"dout45b<="00010001"when"101000"=>dout45m<="00000101"dout45b<="00010000"when"101001"=>dout45m<="00000100"dout45b<=&

28、quot;00001001"when"101010"=>dout45m<="00000011"dout45b<="00001000"when"101011"=>dout45m<="00000010"dout45b<="00000111"when"101100"=>dout45m<="00000001"dout45b<="00000110"when oth

29、ers=>dout45m<="00000000"dout45b<="00000000"end case;end process;end;設(shè)計仿真的截圖：4、cnt25s簡單思路：clk上升沿到來時，若到計時使能信號、sm信號和sb信號有效，cnt25s開始計數(shù)，并將輸入狀態(tài)通過dout25m、dout25b分別輸出到主、支干道顯示。設(shè)計的原理圖模塊：設(shè)計源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt25s is

30、 port(sb,sm,clk,en25:in std_logic; dout25m,dout25b:out std_logic_vector(7 downto 0);end entity cnt25s;architecture art of cnt25s is signal cnt5b:std_logic_vector(4 downto 0); beginprocess(sb,sm,clk,en25)isbegin if sb='0'then cnt5b<=cnt5b-cnt5b-1; elsif sm='0'then cnt5b<=cnt5b-c

31、nt5b-1; elsif(clk'event and clk='1')then if en25='1'then cnt5b<=cnt5b+1; elsif en25='0'then cnt5b<=cnt5b-cnt5b-1; end if; end if; end process; process(cnt5b)is begin case cnt5b is when"00000"=>dount25b<="00100101"dout25m<="00110000&

32、quot; when"00001"=>dount25b<="00100100"dout25m<="00101001" when"00010"=>dount25b<="00100011"dout25m<="00101000" when"00011"=>dount25b<="00100010"dout25m<="00100111" when"00100&qu

33、ot;=>dount25b<="00100001"dout25m<="00100110" when"00101"=>dount25b<="00100000"dout25m<="00100101" when"00110"=>dount25b<="00011001"dout25m<="00100100" when"00111"=>dount25b<=&qu

34、ot;00011000"dout25m<="00100011" when"01000"=>dount25b<="00010111"dout25m<="00100010" when"01001"=>dount25b<="00010110"dout25m<="00100001" when"01010"=>dount25b<="00010101"dout25m

35、<="00100000" when"01011"=>dount25b<="00010100"dout25m<="00011001" when"01100"=>dount25b<="00010011"dout25m<="00011000" when"01101"=>dount25b<="00010010"dout25m<="00010111"

36、; when"01110"=>dount25b<="00010001"dout25m<="00010110" when"01111"=>dount25b<="00010000"dout25m<="00010101" when"10000"=>dount25b<="00001001"dout25m<="00010100" when"10001"=

37、>dount25b<="00001000"dout25m<="00010011" when"10010"=>dount25b<="00000111"dout25m<="00010010" when"10011"=>dount25b<="00000110"dout25m<="00010001" when"10100"=>dount25b<="0

38、0000101"dout25m<="00010000" when"10101"=>dount25b<="00000100"dout25m<="00001001" when"10110"=>dount25b<="00000011"dout25m<="00001000" when"10111"=>dount25b<="00000010"dout25m<

39、="00000111" when"11000"=>dount25b<="00000001"dout25m<="00000110" when others=>dount25b<="00000000"dout25m<="00000000"end case;end process;end;設(shè)計仿真的截圖：5、cnt05s簡單思路：clk上升沿到來時，若到計時使能信號有效，cnt25s開始計數(shù)，并將輸入狀態(tài)通過dout05輸出到主、支干道顯示。設(shè)計

40、的原理圖模塊：設(shè)計源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt05s isport(clk,en05m,en05b:in std_logic; dout5:out std_logic_vector(7 downto 0);end cnt05s;architecture art of cnt05s is signal cnt3b:std_logic_vector(2 downto 0); begin process(clk,en05m,en05b)is begin if

41、(clk'event and clk='1')then if en05m='1'then cnt3b<=cnt3b+1; elsif en05b='1'then cnt3b<=cnt3b+1; elsif en05b='0'then cnt3b<=cnt3b-cnt3b-1; end if; end if; end process; process(cnt3b) begin case cnt3b is when"000"=>dout5<="00000101&quo

42、t; when"001"=>dout5<="00000100" when"010"=>dout5<="00000011" when"011"=>dout5<="00000010" when"100"=>dout5<="00000001" when others=>dout5<="00000000" end case; end process;end;設(shè)計仿真

43、的截圖：第四章 整體組裝與測試一、自動轉(zhuǎn)換出來的源程序：library ieee;use ieee.std_logic_1164.all; library work;entity block1 is port( clk : in std_logic;sm : in std_logic;sb : in std_logic;mr : out std_logic;my : out std_logic;mg : out std_logic;br : out std_logic;by : out std_logic;bg : out std_logic;dout1 : out std_logic_vec

44、tor(7 downto 0);dout2 : out std_logic_vector(7 downto 0);end block1;architecture bdf_type of block1 is component cnt05sport(clk : in std_logic; en05m : in std_logic; en05b : in std_logic; dout5 : out std_logic_vector(7 downto 0);end component;component cnt25sport(sb : in std_logic; sm : in std_logic

45、; clk : in std_logic; en25 : in std_logic; dout25b : out std_logic_vector(7 downto 0); dout25m : out std_logic_vector(7 downto 0);end component;component cnt45sport(sb : in std_logic; clk : in std_logic; en45 : in std_logic; dout45b : out std_logic_vector(7 downto 0); dout45m : out std_logic_vector(

46、7 downto 0);end component;component jtdkzport(clk : in std_logic; sm : in std_logic; sb : in std_logic; mr : out std_logic; my0 : out std_logic; mg0 : out std_logic; br : out std_logic; by0 : out std_logic; bg0 : out std_logic);end component;component xskzport(en45 : in std_logic; en25 : in std_logi

47、c; en05m : in std_logic; en05b : in std_logic; ain05 : in std_logic_vector(7 downto 0); ain25b : in std_logic_vector(7 downto 0); ain25m : in std_logic_vector(7 downto 0); ain45b : in std_logic_vector(7 downto 0); ain45m : in std_logic_vector(7 downto 0); doutb : out std_logic_vector(7 downto 0); do

48、utm : out std_logic_vector(7 downto 0);end component;signalsynthesized_wire_13 : std_logic;signalsynthesized_wire_14 : std_logic;signalsynthesized_wire_15 : std_logic;signalsynthesized_wire_16 : std_logic;signalsynthesized_wire_8 : std_logic_vector(7 downto 0);signalsynthesized_wire_9 : std_logic_ve

49、ctor(7 downto 0);signalsynthesized_wire_10 : std_logic_vector(7 downto 0);signalsynthesized_wire_11 : std_logic_vector(7 downto 0);signalsynthesized_wire_12 : std_logic_vector(7 downto 0);begin my <= synthesized_wire_13;mg <= synthesized_wire_16;by <= synthesized_wire_14;bg <= synthesize

50、d_wire_15;b2v_inst : cnt05sport map(clk => clk, en05m => synthesized_wire_13, en05b => synthesized_wire_14, dout5 => synthesized_wire_8);b2v_inst1 : cnt25sport map(sb => sb, sm => sm, clk => clk, en25 => synthesized_wire_15, dout25b => synthesized_wire_9, dout25m => synthesized_wire_10);b2v_inst2 : cnt45sport map(sb => sb, clk => clk, en45 => synthesized_wire_16, dout45b => synthesized_wire_11, dout45m => synthesized_wire_12);