基于fpga的數(shù)字密碼鎖(使用矩陣鍵盤 )

1、基于FPGA 數(shù)字密碼鎖 板子使用的是DE2頂層topmodule lock(reset,clk,row,col,mm0,mm1,mm2,mm3,led1,led2,led3,set_flog);input clk,reset;input 3:0row;output wire 3:0 col;output wire 6:0 mm0,mm1,mm2,mm3;output reg led1, led2,led3;wire 3:0key_value;reg 3:0 temp_key;reg 3:0 m0,m1,m2,m3;reg 3:0 m_0,m_1,m_2,m_3;reg 5:0 state;r

2、eg 2:0 wei;wire key_valid;reg 1:0count_wrong;output reg set_flog;parameter valid =6'b000000, set =6'b000001, collection_mm =6'b000010, cmd =6'b000100, collection =6'b001000, wrong =6'b010000, correct =6'b100000, die_lock =6'b000011, lock =6'b000111; always (posedg

3、e clk or negedge reset)begin if(!reset) begin state<=6'b000000;wei<=0; led3<=0;set_flog<=0;led1<=0; led2<=0; m0<=15;m1<=15;m2<=15;m3<=15; end else begin case(state) valid : if(key_valid) begin temp_key<=key_value; state<=collection; end else state<=valid; c

4、ollection : begin if(key_value>=0&&key_value<=9) begin if(led1&&(!set_flog)/開啟狀態(tài) 不能按數(shù)字鍵 state<=valid; else if(!key_valid)&&(wei<5) begin led2<=0; state<=collection_mm; wei<=wei+1'b1; end else state<=collection; end else if(!key_valid) state<=cmd

5、; endcollection_mm: begin case(wei) 1:m0<=temp_key; 2:m1<=temp_key; 3:m2<=temp_key; 4:m3<=temp_key; endcase state<=valid; endcmd : begin case(temp_key) 15:if(!led1) begin m0<=15;m1<=15;m2<=15;m3<=15;/* clear state<= valid; wei<=0; led2<=0; led1<=0; end else sta

6、te<= valid; 14:if(led1) state<= valid; else if(wei) /back delete begin case(wei) 1:m0<=15; 2:m1<=15; 3:m2<=15; 4:m3<=15; endcase wei<=wei-1'b1; state<=valid; led2<=0; end else state<=valid; 13: if(set_flog)/保存密碼 begin set_flog<=0;led1<=0;m_0<=m0;m_1<=m1;

7、m_2<=m2;m_3<=m3;state<=lock;end else if(m0=m_0)&&(m1=m_1)&&(m2=m_2)&&(m3=m_3)/compare begin state<=correct;m0<=15;m1<=15;m2<=15;m3<=15; end else begin state<=wrong;count_wrong<=count_wrong+1;end 12: state<=lock; 10: if(led1) /set begin set_flo

8、g<=1; wei<=0; m0<=15;m1<=15;m2<=15;m3<=15; state<=valid; end default:state<=valid; endcaseendcorrect :begin /open led1<=1; state<=valid; count_wrong<=0; end wrong :begin led2<=1;state<=valid;led1<=0; if(count_wrong=3) /lock die begin count_wrong<=0; state

9、<=die_lock; end endlock :begin led1<=0;wei<=0;led2<=0; m0<=15;m1<=15;m2<=15;m3<=15; set_flog<=0; state<=valid;enddie_lock:led3<=1; endcaseendendwire 15:0 mm=m3,m2,m1,m0; key key_scan(reset,clk,row,col,key_value,key_valid);display dis_u1(clk,mm,mm3,mm2,mm1,mm0);endmod

10、ule鍵盤掃描模塊module key(reset,clk,row,col,key_value,key_flag);input clk,reset;input 3:0 row;/hangoutput reg 3:0 col;/lieoutput reg 3:0 key_value;output reg key_flag;reg 3:0 row_reg;reg 3:0 col_reg;reg 19:0 count;reg 2:0 state;reg clk_500khz;always (posedge clk or negedge reset)if(!reset) begin clk_500kh

11、z<=0;count<=0; endelse if(count>=5000) begin clk_500khz<=clk_500khz;count<=0;endelse count<=count + 1'b1;always (posedge clk_500khz or negedge reset)begin if(!reset)begin col<=0;state<=0;row_reg<=0;col_reg<=0;end else begin case(state) 0:begin col<=0; key_flag<

12、;=0; if(row3:0!=4'b1111) begin state<=1;col3:0<=4'b1110; end else state<=0; end 1: if(row3:0!=4'b1111) state<=5; else begin state<=2;col<=4'b1101;end 2: if(row3:0!=4'b1111) state<=5; else begin state<=3;col<=4'b1011;end 3: if(row3:0!=4'b1111) st

13、ate<=5; else begin state<=4;col<=4'b0111;end 4: if(row3:0!=4'b1111) state<=5; else state<=0; 5: if(row3:0!=4'b1111) begin col_reg<=col; row_reg<=row; state<=5; key_flag<=1; end else state <=0;endcaseendendalways(clk or col_reg or row_reg or key_value)begin i

14、f(!reset) key_value<=0; else if(key_flag=1'b1) begin case(col_reg,row_reg) 8'b1110_1110:key_value<=1; 8'b1110_1101:key_value<=2; 8'b1110_1011:key_value<=3; 8'b1110_0111:key_value<=10;/a 8'b1101_1110:key_value<=4; 8'b1101_1101:key_value<=5; 8'b1101

15、_1011:key_value<=6; 8'b1101_0111:key_value<=11;/b 8'b1011_1110:key_value<=7; 8'b1011_1101:key_value<=8; 8'b1011_1011:key_value<=9; 8'b1011_0111:key_value<=12;/c 8'b0111_1110:key_value<=15;/* 8'b0111_1101:key_value<=0; 8'b0111_1011:key_value<

16、=14;/# 8'b0111_0111:key_value<=13;/d endcase endendendmodule顯示模塊module display(clk,mm,wei0,wei1,wei2,wei3);input 15:0mm;input clk;output reg 6:0 wei0,wei1,wei2,wei3;always (clk)begin case(mm3:0)4'b0000:wei0<=7'b 1000000; 4'b0001:wei0<=7'b 1111001; 4'b0010:wei0<=7&

17、#39;b 0100100; 4'b0011:wei0<=7'b 0110000; 4'b0100:wei0<=7'b 0011001; 4'b0101:wei0<=7'b 0010010; 4'b0110:wei0<=7'b 0000010; 4'b0111:wei0<=7'b 1111000; 4'b1000:wei0<=7'b 0000000; 4'b1001:wei0<=7'b 0011000;4'b1010:wei0<

18、=7'b 0001000; 4'b1011:wei0<=7'b 0000011; 4'b1100:wei0<=7'b 1000110; 4'b1101:wei0<=7'b 0100001; 4'b1110:wei0<=7'b 0000110; 4'b1111:wei0<=7'b 1000000; /4'b1111:wei0<=7'b 0001110;endcase case(mm7:4)4'b0000:wei1<=7'b 100000

19、0; 4'b0001:wei1<=7'b 1111001; 4'b0010:wei1<=7'b 0100100; 4'b0011:wei1<=7'b 0110000; 4'b0100:wei1<=7'b 0011001; 4'b0101:wei1<=7'b 0010010; 4'b0110:wei1<=7'b 0000010; 4'b0111:wei1<=7'b 1111000; 4'b1000:wei1<=7'b 00

20、00000; 4'b1001:wei1<=7'b 0011000;4'b1010:wei1<=7'b 0001000; 4'b1011:wei1<=7'b 0000011; 4'b1100:wei1<=7'b 1000110; 4'b1101:wei1<=7'b 0100001; 4'b1110:wei1<=7'b 0000110; 4'b1111:wei1<=7'b 1000000; /4'b1111:wei1<=7'

21、b 0001110; endcase case(mm11:8)4'b0000:wei2<=7'b 1000000; 4'b0001:wei2<=7'b 1111001; 4'b0010:wei2<=7'b 0100100; 4'b0011:wei2<=7'b 0110000; 4'b0100:wei2<=7'b 0011001; 4'b0101:wei2<=7'b 0010010; 4'b0110:wei2<=7'b 0000010; 4&#

22、39;b0111:wei2<=7'b 1111000; 4'b1000:wei2<=7'b 0000000; 4'b1001:wei2<=7'b 0011000;4'b1010:wei2<=7'b 0001000; 4'b1011:wei2<=7'b 0000011; 4'b1100:wei2<=7'b 1000110; 4'b1101:wei2<=7'b 0100001; 4'b1110:wei2<=7'b 0000110; 4'b1111:wei2<=7'