畢業(yè)設(shè)計（論文）外文文獻翻譯3G移動終端基帶信號處理器設(shè)計與實現(xiàn)

1、3g移動終端基帶信號處理器設(shè)計與實現(xiàn)摘要：隨著數(shù)字技術(shù)的進步，高速、超大規(guī)模集成電路廣泛使用，3g移動終端基帶信號處理系統(tǒng)正朝著靈活、高度集成化、模塊化、通用化的方向發(fā)展?；鶐盘柼幚砥魇菙?shù)字技術(shù)與通信技術(shù)相結(jié)合的產(chǎn)物，它能靈活處理數(shù)字基帶信號，調(diào)制無線信號以便實現(xiàn)同通信網(wǎng)絡(luò)系統(tǒng)前端基站的無線通信。文章設(shè)計了一種基于先進微處理器(arm)、數(shù)字信號處理(dsp)和現(xiàn)場可編程門陣列(fpga)體系結(jié)構(gòu)的3g移動終端基帶信號處理器。這種體系結(jié)構(gòu)的優(yōu)點在于當(dāng)提供更能滿足客戶需求的先進處理器時，整個系統(tǒng)容易集成，而且可以通過軟件方法方便地增加功能，而不必定制只讀存儲器(rom)編碼的新芯片。同時系統(tǒng)使

2、用軟件實現(xiàn)聯(lián)合檢測和信號解碼功能，通過軟件更新輕松實現(xiàn)對系統(tǒng)的任何升級，無需硬件修改。 關(guān)鍵字：3g，信號處理design and realize of 3g mobile termination baseband signal processorabstract:along with digital technique's progress, high speed, the ultra large scale integrated circuit widely uses, the 3g mobile termination baseband signal processing sys

3、tem toward nimble, integrated, modular, the universalized direction is developing highly. the baseband signal processor is the product which the digital technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with t

4、he communication network system front end the base depot wireless communication. along with digital technique's progress, high speed, the ultra large scale integrated circuit widely uses, the 3g mobile termination baseband signal processing system toward nimble, integrated, modular, the universa

5、lized direction is developing highly. the baseband signal processor is the product which the digital technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base d

6、epot wireless communication. the article has designed one kind based on advanced microprocessor (arm), digital signal processing (dsp) and scene programmable gate array (fpga) the architecture 3g mobile termination baseband signal processor. this kind of architecture's merit lies, when provides

7、can meet the customer need the advanced processor, the overall system easy to integrate, moreover may increase the function conveniently through the software method, but does not need to have custom-made the non-erasable storage (rom) code the new chip. simultaneously the system use software realize

8、s the union examination and the signal decoding function, with ease realizes through the software update to system's any promotion, does not need the hardware to revise.keywords：3g,signal process1設(shè)計思路隨著實時數(shù)字信號處理技術(shù)的發(fā)展，arm、dsp和fpga體系結(jié)構(gòu)成為3g移動終端實現(xiàn)的主要方式。本文的設(shè)計通過arm對目標(biāo)及環(huán)境進行建模、運算，生成網(wǎng)絡(luò)協(xié)議仿真數(shù)據(jù)庫，應(yīng)用dsp進行數(shù)據(jù)調(diào)度、

9、運算和處理，最后形成所需的調(diào)幅、調(diào)相、調(diào)頻等控制字，通過fpga控制收發(fā)器芯片產(chǎn)生射頻模擬信號。利用數(shù)字芯片之間的通用性，arm與dsp間的通信，不僅能實時處理接收和發(fā)送的數(shù)據(jù)，還可以適應(yīng)不同移動網(wǎng)絡(luò)的具體要求，同時方便加載新的程序。fpga數(shù)字頻率合成技術(shù)以其在頻率捷變速度、相位連續(xù)性、相對帶寬、高分辨率以及集成化等方面的優(yōu)異性能，為 3g移動終端射頻信號模擬的實現(xiàn)方式提供了選擇。 2硬件實現(xiàn)本系統(tǒng)主要部分是arm主控模塊、dsp實時數(shù)據(jù)處理模塊和fpga信號生成模塊。arm主控模塊實現(xiàn)物理層與協(xié)議棧的通信，接收高層的指令，執(zhí)行相應(yīng)的任務(wù)。如協(xié)議棧需要在某些子幀中的某個或幾個上行時隙發(fā)送數(shù)據(jù)

10、到核心網(wǎng)，在某些子幀中的某個或幾個下行時隙接收核心網(wǎng)的數(shù)據(jù)，這時把所有的指令和數(shù)據(jù)都存放在同步動態(tài)隨機存儲器(sdram)中，然后通知dsp去執(zhí)行。dsp實時數(shù)據(jù)處理模塊得到數(shù)據(jù)和命令后，首先處理發(fā)送數(shù)據(jù)，對數(shù)據(jù)進行信道編碼調(diào)制、crc附著、交織、擴頻調(diào)制等，然后處理接收數(shù)據(jù)，如信道估計、去干擾、crc校驗、信道解碼、解擴、唯特比解碼等。fpga為信號生成模塊，管理26 m時鐘，進行分頻的任務(wù)，控制模擬基帶(abb)的自動發(fā)送功率控制(apc)、自動接收增益控制(agc)、自動頻率控制(afc)等，同時也實時控制射頻(rf)的工作。當(dāng)dsp中的一些算法非常穩(wěn)定后，可以用fpga來實現(xiàn)這些算法，

11、減少dsp的處理負(fù)擔(dān)。2.1接口arm與dsp的數(shù)據(jù)交換是通過雙口隨機存儲器(ram)來實現(xiàn)的，起到上下行控制命令、參數(shù)和數(shù)據(jù)等緩存和交換的作用。這里收發(fā)雙口ram數(shù)據(jù)線的位數(shù)大小為16 bit，sdram 存儲大小為128 m。硬件中斷信號線8(int8)與硬件中斷信號線9(int9)每5ms相互產(chǎn)生一次，等于td-scdma空口信號的子幀中斷，同時也可以作為arm與dsp的控制命令、響應(yīng)來實現(xiàn)arm與dsp之間的通信。fpga的主要的接口有data_out15:0接口，與數(shù)模轉(zhuǎn)換器(a/d)接口和與rf接口。data_out15:0接口用來輸出fpga運算的結(jié)果，與dsp的數(shù)據(jù)總線掛接在一

12、起，在fpga內(nèi)部設(shè)置一個三態(tài)門，開門信號就是 fpga的片選信號ce。當(dāng)ce不選通的時候，三態(tài)門輸出為高阻狀態(tài)，不會影響dsp的數(shù)據(jù)總線。在每一個樣點間隔的時間內(nèi)，fpga運算出相關(guān)值的實部和虛部，將它們分別鎖存在4個16 bit的鎖存器中，并將與dsp相連的data_ready信號置高電平，表示數(shù)據(jù)已經(jīng)準(zhǔn)備好。dsp檢測到data_ready為高后會進行讀操作，用地址總線的高幾位產(chǎn)生出片選信號將fpga選通，通過地址總線的低兩位a0、a1來選擇4個鎖存器的其中一個，依次讀取實部和虛部兩個32位數(shù)的高16位和低16位。fpga內(nèi)部會對dsp的讀操作計數(shù)，確認(rèn)數(shù)據(jù)分4次讀出后，則將data_r

13、eady置低，直到下一次運算完畢后再抬高。fpga的頻率、相位和幅度控制字的設(shè)置和控制信號的產(chǎn)生由tms320c5510完成，fpga可以看作是異步存儲設(shè)備與tms320c5510的外存儲器接口 (emif)相連，emif采用32 bit總線。與數(shù)模轉(zhuǎn)換器(a/d)接口的a/d一端連接abb，另一端連接fpga，傳輸要發(fā)送的數(shù)據(jù)和移動網(wǎng)絡(luò)接收的數(shù)據(jù)。在與a/d的接口部分中，有 3個輸入端rif、ps和clk。rif用來串行輸入a/d轉(zhuǎn)換來的樣點值；ps為幀同步信號，它在輸入到fpga后用來驅(qū)動fpga內(nèi)部的總體控制模塊；clock為移位時鐘，它控制a/d與fpga之間數(shù)據(jù)串行傳輸?shù)囊莆?。與rf

14、接口主要是用來控制發(fā)送和接收rf芯片工作。2.2主控模塊主控模塊負(fù)責(zé)控制和協(xié)調(diào)各種工作，arm采用ti公司生產(chǎn)的開放式多媒體應(yīng)用平臺(omap)微處理器，通過集成鎖相環(huán)倍頻系統(tǒng)主頻可以達到 66 mhz，最大外部存儲空間可達256 mb，片上資源豐富，外圍控制能力強性價比高。由它控制dsp模塊接收網(wǎng)絡(luò)發(fā)送的命令及參數(shù)，實現(xiàn)無線自由的協(xié)議通信。2.3實時數(shù)據(jù)處理模塊實時數(shù)據(jù)處理模塊1通過共享內(nèi)存與arm實現(xiàn)發(fā)送的命令、傳輸參數(shù)和數(shù)據(jù)，根據(jù)設(shè)定的移動終端工作狀態(tài)，如cell search、隨機接入過程(ra)、專用控制信道(dcch)，及目標(biāo)、環(huán)境的實時動態(tài)計算fpga的控制字。同時也通過共享內(nèi)存

15、上報從網(wǎng)絡(luò)接收的數(shù)據(jù)和信息傳輸給arm;通過鎖存器向處理板提供控衰減控制信號實現(xiàn)睡眠，來達到省電。dsp采用ti公司c5000系列中的tms320c5510，系統(tǒng)時鐘達600 mhz，數(shù)據(jù)處理速率可以達到4 800 mips。提供32/16 bit主機口，具有兩個獨立的外部存儲器接口，其中emif支持64 bit總線寬度。2.4 fpga模塊設(shè)計本文的設(shè)計采用stratix系列芯片，內(nèi)嵌多達10 mbit的3種ram塊：512 bit容量的小型ram、4 kb容量的標(biāo)準(zhǔn)ram、512 kb的大容量ram。fpga模塊具有true_lvds電路，支持低電壓差分信號(lvds)、低電壓正射極耦合邏

16、輯(lvpecl)、準(zhǔn)電流模式邏輯 (pcml)和超傳輸模式(hypertranport)差分i/o電氣標(biāo)準(zhǔn)，且有高速通信接口。本設(shè)計提供了完整的時鐘管理方案，具有層次化的結(jié)構(gòu)和多達12個鎖相環(huán)(pll)。stratix系列使用的開發(fā)軟件是altera公司提供的新一代開發(fā)軟件quartus ii。該系列芯片的最大特色是內(nèi)嵌硬件乘法器和乘加結(jié)構(gòu)的可編程dsp模塊，適用于實現(xiàn)高速信號處理。這種dsp模塊是高性能的嵌入算術(shù)單元，它可以配置為硬件乘法器、加減法器、累加器和流水線寄存器。stratix系列具有多達28個dsp模塊，可配置為224個嵌入乘法器，可以為大數(shù)據(jù)吞吐量的應(yīng)用提供靈活、高效和有價值

17、的方案。這些dsp模塊可以實現(xiàn)多種典型的dsp功能，如有相關(guān)器、限沖擊響應(yīng)(fir)濾波、快速傅立葉變換(fft)功能和加密/解密功能等，其中相關(guān)器算法設(shè)計是各種其他算法實現(xiàn)的基礎(chǔ)和基本組成部分。移動終端系統(tǒng)接收到的射頻信號經(jīng)過前端預(yù)處理后，送到a/d采樣，然后通過串行方式輸出樣點值到fpga2。每個樣點值是用10 bit的二進制補碼表示的，需先通過一個串/并轉(zhuǎn)換器轉(zhuǎn)化為寬度為10 bit的并行信號。首先樣點值要進行的是希爾波特變換，希爾波特變換有多種實現(xiàn)方法，這里采用一個129階的濾波器來實現(xiàn)，濾波器的抽頭系數(shù)由 matlab函數(shù)remez產(chǎn)生，得到與其正交的另一路信號;然后以這兩路信號分別

18、作為實部和虛部，與本地序列進行相關(guān)運算，將相關(guān)值的實部和虛部送給 dsp做后續(xù)處理。這樣，dsp才可以通過先對相關(guān)值求模，然后對模值出現(xiàn)的峰值的間隔、幅值和數(shù)目等信息進行判斷和進一步處理，來確定是否捕捉到信號。2.5 pfga與rf的接口、總線及時序控制設(shè)計為了增加信道容量、改善帶寬效率，td-scdma通過利用上行鏈路(反向鏈路)同步、軟件無線電和智能天線的技術(shù)將時分雙工(tdd)與 cdma結(jié)合起來。td-scdma要求手機的射頻部分具有快速的切換時間、高的動態(tài)范圍以及發(fā)送機和接收機部分的高線性度。max2410是一個完整正交發(fā)射器，它由一個正交調(diào)制器、可變增益if和rf放大器組成。max

19、2309是一種為基于cdma的單頻單模蜂窩電話系統(tǒng)設(shè)計的if接收機，其輸入頻率范圍經(jīng)過優(yōu)化達到70 mhz300 mhz，在35 db增益下達-33 db，在-35 db增益下達+1.7 db。fpga控制rf主要通過4個rf控制寄存器：a word寄存器、b word寄存器、c word寄存器和d word寄存器。3軟件實現(xiàn)移動終端軟件包括應(yīng)用層軟件、通信協(xié)議軟件和物理層軟件3部分。應(yīng)用層軟件lay 4-7：包含人機界面(mmi)和系統(tǒng)應(yīng)用層協(xié)議(s/w)部分，mmi為移動終端使用者接口，s/w類似移動終端的操作系統(tǒng)。通信協(xié)議軟件lay2-3：該部分軟件較大，主要為通信協(xié)議，主要保證無線通信

20、系統(tǒng)可以在各種狀況順暢互通。物理層軟件lay 1：負(fù)責(zé)協(xié)調(diào)dsp、其他硬件和軟件。物理層軟件的設(shè)計將能實現(xiàn)節(jié)能的特性、多資源、多時隙的處理、數(shù)據(jù)包和對其他網(wǎng)絡(luò)系統(tǒng)的監(jiān)測。在設(shè)計物理層軟件時的還要對相鄰小區(qū)的監(jiān)測，特別是當(dāng)相鄰小區(qū)間彼此還沒有同步的時候。移動終端軟件各個模塊主要實現(xiàn)與硬件的對應(yīng)關(guān)系如下：應(yīng)用層軟件lay 4-7和通信協(xié)議軟件lay 2-3軟件的實現(xiàn)主要是在arm中實現(xiàn)，假如lay 4-7需要一些特別高要求的應(yīng)用時，可以再增加相應(yīng)的硬件模塊，而不影響原有的架構(gòu)，如增加高要求多媒體的處理和播放;物理層軟件lay 1主要在dsp和fpga中實現(xiàn)。在軟件編程時arm和dsp可以使用c語言

21、來實現(xiàn)，使用的調(diào)試工具為ccs軟件，當(dāng)dsp中有一些算法非常成熟后，移動通信對這塊的實時性要求比較高時，應(yīng)該用匯編語言來實現(xiàn)，在fpga中可以用vhdl語言來實現(xiàn)。在編程是首先盡量定義好各個功能模塊的任務(wù)，然后定義好各個功能模塊的接口參數(shù)等，在可以不用全局變量的時候盡量不用。另一個主要挑戰(zhàn)是在td-scdma終端里實現(xiàn)聯(lián)合檢測算法，特別是關(guān)于算法的時間優(yōu)化。dsp和fpga之間的任務(wù)分配上要有一個合理協(xié)調(diào)的分工，這樣能夠最大限度的發(fā)揮這兩個處理器的功能。在實際軟件編程中，算法程序計算量大、編碼延時過長，因此需要在保證質(zhì)量的前提下對算法進行優(yōu)化。在滿足精度要求下,進一步將算法簡化，粗化搜索范圍來

22、降低計算量;對于高級語言程序代碼，用混合匯編、去除嵌套循環(huán)等方法進行代碼優(yōu)化，提高代碼效率。4 結(jié)束語該系統(tǒng)很好的實現(xiàn)了3g移動終端處理功能，但實際環(huán)境比仿真環(huán)境更復(fù)雜，需要給出解決辦法，然后再驗證。目前該方案實現(xiàn)了384 kb/s工作，使用3個時隙(每個時隙128 kb/s);實現(xiàn)了基于高速下行分組接入(hsdpa)技術(shù)提高數(shù)據(jù)速率，它類似于wcdma和cdma2000標(biāo)準(zhǔn)所提供的速率。開發(fā)的3g芯片組能夠滿足消費者對于改善性能和功能的要求，同時又保持了相同或更低的價格。design and realize of 3g mobile termination baseband signal p

23、rocessor along with digital technique's progress, high speed, the ultra large scale integrated circuit widely uses, the 3g mobile termination baseband signal processing system toward nimble, integrated, modular, the universalized direction is developing highly. the baseband signal processor is t

24、he product which the digital technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base depot wireless communication. along with digital technique's progress

25、, high speed, the ultra large scale integrated circuit widely uses, the 3g mobile termination baseband signal processing system toward nimble, integrated, modular, the universalized direction is developing highly. the baseband signal processor is the product which the digital technique and the commu

26、nication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base depot wireless communication. the article has designed one kind based on advanced microprocessor (arm), digital signal proces

27、sing (dsp) and scene programmable gate array (fpga) the architecture 3g mobile termination baseband signal processor. this kind of architecture's merit lies, when provides can meet the customer need the advanced processor, the overall system easy to integrate, moreover may increase the function

28、conveniently through the software method, but does not need to have custom-made the non-erasable storage (rom) code the new chip. simultaneously the system use software realizes the union examination and the signal decoding function, with ease realizes through the software update to system's any

29、 promotion, does not need the hardware to revise.1 design mentality along with the real-time digital signal processing technology's development, arm, dsp and the fpga architecture becomes the fundamental mode which the 3g mobile termination realizes. this article design carries on the modelling,

30、 the operation through arm to the goal and the environment, the production network protocol simulation database, carries on the data dispatch, the operation and processing using dsp, finally forms control words and so on amplitude modulation which, phase modulation, frequency modulation needs, produ

31、ces the radio frequency simulated signal through the fpga control transceiver chip. using digital chip between versatility, arm and dsp correspondence, not can only the real-time processing receive the data which and transmit, but may also adapt the different motion network specific request, simulta

32、neously facilitates loads the new procedure. the fpga digit frequency synthesis technology take it in aspect and so on frequency agility speed, phase continuity, relative bandwidth, high resolution as well as integration outstanding performance, as the 3g mobile termination radio-frequency signal si

33、mulation realizes the way to provide the choice.2 hardware realize this systems main part are the arm master control module, the dsp real-time data processing module and fpga signal production module. the arm master control module realizes the physical level and the agreement stack's corresponde

34、nce, receives the high-level instruction, carries out the corresponding task. if the agreement stack needed in certain sub-frames some either several upward time slot transmission data to the core network, in certain sub-frames some or several downward time slot receive core network's data, by n

35、ow deposits all instructions and the data in synchronized dynamic random-access memory (sdram), then informed dsp to carry out. after the dsp real-time data processing module obtains the data and the order, first processes the transmission data, carries on the channel coding modulation, crc to the d

36、ata to adhere to stick cohere, to interweave, the wide frequency modulation and so on, then the processing receive data, like the channel estimated that disturbs, the crc verification, the channel decoding, the despread, only especially compared to the decoding and so on. fpga is the signal producti

37、on module, manages 26 m clocks, carries on the frequency division the duty, control simulation baseband (abb) automatic transmission power control (apc), automatic reception gain control (agc), automatic frequency control (afc) and so on, simultaneously also real-time control radio frequency (rf) wo

38、rk. when in after dsp some algorithms are stable, may use fpga to realize these algorithms, reduces dsp the processing burden. 2.1 connection arm and the dsp data exchange realizes through pair of mouth stochastic memory (ram), namely figure 1 sdram, plays ascending-descending buffers and the exchan

39、ge and so on control command, parameter and data role. here receives and dispatches the pair of mouth ram data line the figure size is 16 bit, the sdram memory size is 128 m. the hardware interrupt holding wire 8(int8) produces mutually with hardware interrupt holding wire 9(int9) every 5 ms one tim

40、e, was equal to that the td-scdma idle talk signal the sub-frame interrupts, simultaneously may also as arm and the dsp control command, the response realizes between arm and the dsp correspondence.the fpga main connection has the data_out15:0 connection, with d/a converter (a/d) connection and with

41、 the rf connection.the data_out15:0 connection uses for to output the fpga operation the result, hangs with the dsp data bus meets in the same place, establishes a three states of matter gate in the fpga interior, the enabling signal is fpga selects patches or strips of land as worth saving for seed

42、 signal ce. when ce does not select, the three states of matter gate output is the high-resistance condition, will not affect dsp the data bus. in each sampling point gap's time, fpga operates the correlative value the real part and the imaginary component, distinguishes the lock them to have 4

43、16 bit in the latches, and signal will set at the high level with dsp the connected data_ready, indicated that the data already prepared. dsp examines data_ready is gao houhui carries on reads the operation, produces with address bus's high several selects patches or strips of land as worth savi

44、ng for seed the signal to select fpga, through address bus's low two a0, a1 chooses 4 latches, reads the real part and the imaginary component two 32 figures in turn high 16 and low 16. the fpga interior will read the operation counting to dsp, confirmed after the data will be divided 4 read-out

45、, will set at data_ready lowly, finished after the next operation raised again. the fpga frequency, the phase and the scope control word's establishment and control signal's production completes by tms320c5510, fpga may regard as is the asynchronous storage device and tms320c5510 external me

46、mory connection (emif) is connected, emif uses 32 bit main lines. d/a converter (a/d) connection's a/d end connection abb, another end connection fpga, the transmission must transmit data and motion network receive data. with in a/d connection part, has 3 input end rif, ps and clk. rif uses for

47、the sampling point value which serial input a/d transforms; ps is the frame synchronizing signal, it in inputs uses for after fpga to actuate the fpga internal overall control module; clock is shifts the clock, it controls between a/d and fpga data serial transmission shifting. the rf connection is

48、mainly uses for to control transmits and receives the rf chip work.2.2 master control module the master control module is responsible to control and to be coordinated each kind of work, arm uses the open style multimedia application platform (omap) microprocessor which ti corporation produces, may a

49、chieve 66 mhz through the integrated phase-locked loop frequency multiplication system basic frequency, the biggest exterior storage space may reach 256 mb, on the piece the fruitful in resources, the periphery control stubborn and unyielding person price scaled height of burst. controls the dsp mod

50、ule receive network transmission by it the order and the parameter, realizes the wireless free agreement correspondence. 2.3 real-time data processing module real-time data processing module 1 realizes the transmission order, the transmission parameter and the data through the sharing memory and arm

51、, according to the hypothesis mobile termination active status, like cell search, stochastic turning on process (ra), dedicated control channel (dcch), and the goal, the environment real-time dynamic calculates fpga the control word. simultaneously also gives arm through sharing memory reporting fro

52、m the network receive's data and the intelligence transmission; provides through the latch to the processing board controls the weaken control signal to realize the sleep, achieves the province electricity. dsp uses in ti corporation c5000 series tms320c5510, the system clock reaches 600 mhz, th

53、e data processing speed may achieve 4800 mips. provides 32/16 bit main engine mouth, has two independent exterior memory interfaces, emif supports 64 bit main line width2.4 fpga modulesdesign this article the design to use the stratix series chip, in inlays reaches 10 mbit 3 kind of ram blocks: 512

54、bit capacity small ram, 4 kb capacity standard ram, 512 kb large capacity ram. the fpga module has the true_lvds electric circuit, supports low voltage difference signal (lvds), low voltage emitter-coupled logic (lvpecl), accurate electric current pattern logic (pcml) and ultra mode of transmission

55、(hypertranport) the difference i/o electricity standard, and has the high-speed service connection. this design has provided the complete clock management plan, has the hierarchical structure and reaches 12 phase-locked loop (pll). the stratix series use's development software is the new generat

56、ion who altera corporation provides develops software quartus ii.this series chip's biggest characteristic are in inlay the hardware multiplier and while add the structure the programmable dsp module, is suitable in realizes the high speed signal processing. this kind of dsp module is the high p

57、erformance inserting arithmetic unit, it may dispose for the hardware multiplier, adds and subtracts the buddhist musical istrument, the accumulator and the assembly line register. the stratix series has reaches 28 dsp modules much, may dispose is 224 inserting multipliers, may provide nimble, highl

58、y effective and the valuable plan for the big data volume of goods handled application. these dsp module may realize many kinds of model dsp functions, like has the correlation instrument, to limit the impact on respond the (fir) filter, the fast fournier transformation (fft) function and the encryp

59、tion/decipher function and so on, the correlation instrument algorithm design is the foundation which and the basic building block each other algorithms realize.the mobile termination system receives after front end the radio-frequency signal passes through pretreats, delivers a/d sampling, then through serial mode output sampling point value to fpga2. each sampling point value is with 10 bit two's complement expressions, must/and the switch transforms through a string fo