作業(yè)-基于verilog HDL的八位超前進(jìn)位加法器

1、基于verilog HDL的八位超前進(jìn)位加法器Verilog 綜合作業(yè) 陳孫文 2011-10-25指導(dǎo)老師：鄧婉玲老師目錄：1. 超前進(jìn)位加法器原理2. 算法代碼3. modelsim SE軟件實(shí)現(xiàn)功能仿真4. synplify pro軟件實(shí)現(xiàn)綜合正文：一、 原理（1）、全加器列出真值表如表所示，若Ai、Bi兩個(gè)一位二進(jìn)制數(shù)相加，以Ci表示來自低位的的進(jìn)位，Si表示和，Ci表示向高位的進(jìn)位，可以看出該電路考慮來低位的進(jìn)位，是一個(gè)一位數(shù)的全加器電路，其邏輯符號如圖所示。串并行超前進(jìn)位加法器的特點(diǎn)是：各級進(jìn)位信號同時(shí)產(chǎn)生，減小或消除因進(jìn)位信號逐級傳遞所用的時(shí)間。每一位的進(jìn)位信號不依賴于從低位逐級

2、傳遞，而是開始就能確定。全加器真值可以得到邏輯表達(dá)式：為表達(dá)簡單，定義兩個(gè)中間變量Gi和Pi 得出得到各位進(jìn)位信號的邏輯表達(dá)式為： 當(dāng)實(shí)際位數(shù)較多時(shí)，往往將全部數(shù)位按4位一組分成若干組，組內(nèi)采用超前進(jìn)位，組間采用串行進(jìn)價(jià)，組成所謂的串并行進(jìn)位加法器。二、 算法代碼：有4bits.v、8bits.v、testbench.v三個(gè)文件；4bits.v實(shí)現(xiàn)輸入為4位數(shù)的加法器；8bits.v中調(diào)用4bits.v中的函數(shù)來實(shí)現(xiàn)8位數(shù)相加；testbench.v為測試代碼；實(shí)現(xiàn)四位加法4bits.v部分：module fast_adder4b(ina,inb,carry_in,sum_out,clk,rs

3、t_n); parameter ADDER_WIDTH=4; parameter SUM_WIDTH=5; input ADDER_WIDTH-1:0ina; /輸入數(shù)ina，8位 input ADDER_WIDTH-1:0inb; /輸入數(shù)inb，8位 input carry_in; input rst_n; input clk; output SUM_WIDTH-1:0 sum_out; reg SUM_WIDTH-1:0 sum_out; wire ADDER_WIDTH-1:0sg; wire ADDER_WIDTH-1:0sp; wire ADDER_WIDTH-1:0sc; ass

4、ign sg0=ina0&inb0; /中間變量G0=ina0&inb0; assign sg1=ina1&inb1; assign sg2=ina2&inb2; assign sg3=ina3&inb3; assign sp0=ina0inb0; /中間變量P0=ina0inb0; assign sp1=ina1inb1; assign sp2=ina2inb2; assign sp3=ina3inb3; assign sc0=sg0|(sp0&carry_in); /進(jìn)位位C0 assign sc1=sg1|(sp1&(sg0|(sp

5、0&carry_in); assign sc2=sg2|(sp2&(sg1|(sp1&(sg0|(sp0&carry_in); assign sc3=sg3|(sp3&(sg2|(sp2&(sg1|(sp1&(sg0|(sp0&carry_in); always(posedge clk or negedge rst_n) begin if(!rst_n) sum_out<=5'b00000; else begin sum_out0<=sp0carry_in; /輸出結(jié)果位 sum_out1<=sp1sc0

6、; sum_out2<=sp2sc1; sum_out3<=sp3sc2; sum_out4<=sc3; end endendmodule實(shí)現(xiàn)八位加法8bits.v部分：module pipe_adder8b(ina,inb,sum_out,clk,rst_n); parameter ADDER_WIDTH=8; parameter SUM_WIDTH=9; parameter HALF_ADDER_WIDTH=4; input ADDER_WIDTH-1:0ina; input ADDER_WIDTH-1:0inb; input rst_n; input clk; outp

7、utSUM_WIDTH-1:0 sum_out; reg SUM_WIDTH-1:0 sum_out; reg HALF_ADDER_WIDTH-1:0 ina_lsb; reg HALF_ADDER_WIDTH-1:0 ina_msb; reg HALF_ADDER_WIDTH-1:0 inb_lsb; reg HALF_ADDER_WIDTH-1:0 inb_msb; reg HALF_ADDER_WIDTH-1:0 ina_msb1; reg HALF_ADDER_WIDTH-1:0 inb_msb1; reg HALF_ADDER_WIDTH:0 sum11; wireHALF_ADD

8、ER_WIDTH:0 sum1; wireHALF_ADDER_WIDTH:0 sum2; always (posedge clk or negedge rst_n) begin if(!rst_n) begin ina_lsb<=4'b0000; ina_msb<=4'b0000; inb_lsb<=4'b0000; inb_msb<=4'b0000; end else begin ina_lsb<=ina3:0; ina_msb<=ina7:4; inb_lsb<=inb3:0; inb_msb<=inb7:4

9、; end end fast_adder4b u1(ina_lsb,inb_lsb,1'b0,sum1,clk,rst_n); /低四位調(diào)用4位加法器模塊 always (posedge clk or negedge rst_n) begin if(!rst_n) begin ina_msb1<=4'b0000; inb_msb1<=4'b0000; end else begin ina_msb1<=ina_msb; inb_msb1<=inb_msb; end end fast_adder4b u2(ina_msb1,inb_msb1,sum1

10、4,sum2,clk,rst_n); /高四位調(diào)用4位加法器模塊 always (posedge clk or negedge rst_n) begin if(!rst_n) sum11<=4'b0000; else sum11<=sum1; end always (posedge clk or negedge rst_n) begin if(!rst_n) sum_out<=9'b0000_00000; else sum_out<=sum2,sum113:0; endendmoduletestbengch.v部分：timescale 1ns/1nsmo

11、dule test_8a; reg clk,rst_n; reg 7:0ina,inb; wire 8:0sum_out; always #20 clk=clk; /時(shí)鐘信號40ns一個(gè)周期 initial begin rst_n=1; clk=0; #30 ina=43; /給a賦值43 inb=61; #200 rst_n=0; #40 rst_n=1; #2000 $stop; end /fast_adder4b bbb(.ina(ina),.inb(inb),.carry_in(1'b0),.sum_out(sum_out),.clk(clk),.rst_n(rst_n); pipe_adder8b te(.ina(ina),.inb(inb),.sum_out