單片機外文翻譯

1、中原工學院信息商務學院外文翻譯51系列單片機的結構和功能51系列單片機是英特爾公司生產(chǎn)的具有一定結構和功能的單片機產(chǎn)品。這家公司在1976年引入8位MCS - 48系列單片機后，于1980年又推出了8位高檔的MCS - 51系列單片機。它包含很多種這類型的單片機，如8051，8031，8751，80C51BH，80C31BH等，它們的基本組成，基本性能和指令系統(tǒng)都是一樣的。一般情況習慣用8051來代表51系列單片機。一個單片機的系統(tǒng)是由以下幾部分組成：（1）一個8位CPU微處理器。（2）靜態(tài)隨機存取存儲器，能夠儲存程序運行過程中產(chǎn)生的數(shù)據(jù)。（3）程序存儲器ROM / EPROM中（4KB/8K

2、B），用來保存程序和一些初始數(shù)據(jù)。但是在一些單片機中不使用ROM / EPROM中，如8031，8032，80C51系列等。（4）4個8排的I / O并行接口P0 P3，每個口可以用作輸入，也可以用作輸出。（5）2個定時器/計數(shù)器，每個定時器/計數(shù)器可設置計數(shù)用來計數(shù)外部事件，可以設置成常用的定時方式，并可以根據(jù)計算或結果控制單片機的運行。（6）五個中斷源控制系統(tǒng)。（7）1個雙向串行I / O口的UART（通用異步接收器/發(fā)送器UART），用于實現(xiàn)單片機的串行通信。（8）振蕩器和時鐘產(chǎn)生電路，需要外部電源的石英晶體微調(diào)電路，允許接在12MHz的振蕩頻率上。上述部分通過內(nèi)部數(shù)據(jù)總線連接。其中，C

3、PU是單片機的核心，它是單片機的控制和指揮中心，ALU算數(shù)邏輯運算單元可進行算術運算和邏輯運算，由1個 8暫時存儲器，和2個 8位的累加器組成。ACC累加器是ALU運算結果的存放單元，一般數(shù)據(jù)通過它來傳送。此外，ACC往往被視為對8051內(nèi)的數(shù)據(jù)傳輸中轉(zhuǎn)站。和通常的微處理器一樣，它是最繁忙的寄存器。有記憶功能并執(zhí)行命令。該控制器包括程序計數(shù)器，可讀寫的存儲器，振蕩器和定時電路等。該程序計數(shù)器是有兩對8或16位計數(shù)器，它是一個字節(jié)地址計數(shù)器，在個人電腦運行程序時，執(zhí)行下一個單元的內(nèi)容，程序執(zhí)行時可以改變它的內(nèi)容從而改變運行的結果。在8051芯片振蕩電路中，需要外接石英晶體和微調(diào)電容，其頻率范圍為

4、1.2MHz-12MHz。該脈沖信號，即為8051的工作周期，是最小的時間單位。8051和其他單片機一樣，都有相同的控制和功能，就像一個樂隊跟從拍子指揮一樣。在8051中有ROM（程序存儲器，只能讀取），和RAM（數(shù)據(jù)存儲器，可以讀和寫），他們有各自獨立的內(nèi)存地址空間，也有相同的處理方式。8051和8751的程序存儲器的存儲容量為4KB，地址從0000H開始，在使用過程中其中的數(shù)據(jù)不變。8051、8751、8031數(shù)據(jù)存儲器的內(nèi)存為128B，默認地址是00FH，用于保存中間數(shù)據(jù)和緩存。在這128B的內(nèi)存中，有32 bytes，被稱作工作寄存器，和常用的微處理器不同的是，8051的RAM是按功能

5、來劃分模塊的。MCS - 51系列單片機和一般電腦的處理方式不同。一般電腦會自動分配地址空間，ROM和RAM的計算機可以安排在不同的空間內(nèi)，地址范圍會根據(jù)ROM和RAM的位置分配不同地址空間。在訪問的內(nèi)存，不管是ROM和RAM，只有一個地址對應一個內(nèi)存單元，都要按這個順序訪問。這種內(nèi)存結構是所謂的普林斯頓結構。 8051的存儲器按物理結構劃分可分為程序存儲器空間和數(shù)據(jù)存儲空間，共有四個內(nèi)存空間，按結構位置的不同分為內(nèi)部程序存儲空間、外部程序存儲空間、內(nèi)部數(shù)據(jù)存儲空間和外部數(shù)據(jù)存儲空間。但從用戶的使用角度看，8051存儲器地址空間被分成三類：（1）片內(nèi)，安排FFFFH的塊，片外的（使用16個地址

6、）串口0000H地址。（2）外部數(shù)據(jù)存儲器地址空間為64KB，地址是從0000H到 FFFFH（含16個地址）的位置排列也。（3）256B的數(shù)據(jù)存儲器（使用8個地址）的地址空間。上述三個重疊的內(nèi)存空間地址，用8051指令系統(tǒng)的傳輸不同的數(shù)據(jù)和使用的功能區(qū)分。CPU的訪問內(nèi)存時，訪問ROM使用MOVC語句，訪問RAM塊順序使用片外操作的MOVX語句，訪問內(nèi)存片段使用MOV語句。8051單片機有4個8并行的I / O端口，分別為P0，P1，P2和P3。每個端口是8位精確的雙向口，共占了32針。每一個I / O線可作為獨立的入口和出口。每個端口包括一個鎖存器（即特殊功能寄存器），一個出口驅(qū)動器和引進

7、緩沖器。使數(shù)據(jù)能夠鎖存輸出，數(shù)據(jù)可以及時緩沖，其余四個具有相同的功能。接外部存儲擴大它們的內(nèi)存時，這四個口就可作為雙向口常用的I / O口，這是，P2口看到高8位地址，P0口是一個公共兩用口，傳送輸出低8的地址和數(shù)據(jù)。8051單片機四個I/O端口的電路設計非常巧妙。熟悉I/O端口邏輯電路，不但有利于正確合理地使用端口，而且會對設計單片機外圍邏輯電路有所啟發(fā)。端口的負載能力和接口都有一定要求，由于P0口的輸出級與P1-P3 口的輸出級在結構上是不同的，因此，它門的負載能力和接口要求也各不相同。P0口與其他口不同，它的輸出級無上拉電阻。當把它用作通用口使用時，輸出級是開漏電路，故用其輸出去驅(qū)動NM

8、OS輸入時需外接上拉電阻。用作輸入時，應先向口鎖存器寫1。P0口的每一位輸出可驅(qū)動8個LS型TTL負載。P1口也是一個準雙向口，用作通用I/O。其電路的輸出部分與P0口不同，內(nèi)部有上拉負載電阻與電源相連。實質(zhì)上，電阻是兩個場效應管FET并在一起：一個FET為負載管，其電阻固定。另一個可工作在導同或截止兩種狀態(tài)，使其總電阻值變化近似0或組值很大兩種情況。當電阻近似為0時，可將引腳快速上拉至高電平；當電阻值很大時，P1口為高阻輸入狀態(tài)。當P1口輸出高電平時，能向外提供拉電流負載，所以不必再接上拉電阻。在端口用作輸入時，也必須先向?qū)逆i存器寫入1，使FET截止。由于片內(nèi)負載電阻較大約20千歐姆到4

9、0千歐姆，所以不會對輸入的數(shù)據(jù)產(chǎn)生影響。P2口某位的結構與P0口類似，有MUX開關。驅(qū)動部分與P1口類似，但比P1口多了一個轉(zhuǎn)換控制部分。P3口是一個多功能端口，它比P1口多了“與非”門3和緩沖器4。正是這兩部分，使得她除了具有P1口的準雙向功能之外，還可以使用各引腳所具有的第二功能。“與非”門3的作用實際上是一個開關，決定是輸出鎖存器上的數(shù)據(jù)還是輸出第二功能的信號。當W=1時，輸出Q端信號；當Q=1時，可輸出W線信號。編程時，可不必事先有軟件設置P3口為第一功能還是第二功能。當CPU對P3口進行SFR尋址（位或字節(jié)）訪問時，有內(nèi)部硬件自動將第二功能輸出/輸入線時，有內(nèi)部硬件鎖存器Q=1. P

10、3口的工作原理與P1口類似。P1-P3口的輸出級接有內(nèi)部上拉負載電阻，它們的每一位輸出可驅(qū)動4個LS型TTL負載。作為輸入口時，任何TTL或NMOS電路都能以正常的方式驅(qū)動8051單片機的P1-P3口。由于它們的輸出級具有上拉電阻，也可以被集電極開路或漏極開路所驅(qū)動，而無需外接上拉電阻。口也都是準雙向口。作為輸入時，必須先對相應端口鎖存器寫1。對于80C51單片機，端口只能提供幾毫安的輸出電流，故當作輸出口去驅(qū)動一個普通晶體管的基極時，應在端口與晶體管基極間串聯(lián)一個電阻，以限制高電平輸出時的電流。P1-P3復位是單片機的初始化操作。其主要功能是把PC初始化為0000H，使單片機從0000H單元

11、開始執(zhí)行程序。除了進入系統(tǒng)的正常初始化之外，當由于程序運行出錯或操作錯誤使系統(tǒng)處于死鎖狀態(tài)時，為擺脫困境，也需按復位鍵重新啟動。在8051中RST引腳是復位信號的輸入端。復位信號是高電平有效，其有效時間應持續(xù)24個振蕩周期（即二個機器周期）以上。若使用頻率6兆赫茲的晶振，則復位信號持續(xù)時間應超過4微妙才能完成復位操作。整個復位電路包括芯片內(nèi)，外兩部分。外部電路產(chǎn)生的復位信號(RST)送至施密特觸發(fā)器，再有片內(nèi)復位電路在每個機器周期的S5P2時刻對施密特觸發(fā)器的輸出進行采樣，然后才得到內(nèi)部復位操作所需的信號。一般復位電路中的電阻，電容參數(shù)適用于6晶振，能保證復位信號高電平持續(xù)時間大于2個機器周期

12、。復位電路雖然簡單，但其作用非常重要。一個單片機系統(tǒng)能否正常運行，首先要檢查是否能復位成功。初步檢查可用示波器探頭監(jiān)視引腳，按下復位鍵，觀察是否有足夠幅度的波形輸出（瞬時的），還可以通過改變復位電路來進行實驗。 本文摘譯自單片機數(shù)據(jù)手冊Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produce

13、s. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH, etc, their basic composition, basi

14、c performance and instruction system are all the same. 8051 daily representatives-51 serial one-chip computers. A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data th

15、at write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032, 80C51, etc.

16、(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or r

17、esult of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of comp

18、uter to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip comput

19、er, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporary of 8, storing device 2 tempo

20、rarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , op

21、eration result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with an expresses in the order. The controller includes the

22、 procedure counter, the order is deposited, the order deciphers the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content

23、which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, na

24、mely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded. There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write

25、 ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memo

26、ry data memory 128B, address false 00FH, use for middle result to deposit operation, the data is stored temporarily and the data are buffered etc. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM an

27、d job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of t

28、his address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the s

29、tructure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure

30、 forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) in the slice, arranges blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addres

31、ses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the orde

32、r symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 one-chip computer have four 8 walk abreast I/O ports; call P0, P1, P2 and P3. Each port is

33、8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register): one exports the driver and an introduction buffer. Make data can latch when outputting, data can buffe

34、r when making introduction , but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0

35、mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing. The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to d

36、esigning the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothi

37、ng in common with each other. P0 mouth is different from other mouth, it output grade draws the resistance supreme. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting to

38、go out to fail. When being used as introduction, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance lin

39、k with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two states, make its president resistance value change approximate 0 or group value he

40、avy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ; When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current lo

41、ad to offer outwards, draw the resistance on needn't answer and then. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, makes FET end. Relatively about 20,000 ohms because of the load resistance in scene and because of 40,000 ohm will not exert a

42、n influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1, P3 mouth one multi-functional port, mouth getting many than P1 it have "and" 3 d

43、oors and 4 buffers". Two parts these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3 functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =at

44、1 o'clock, output Q end signal; Act as Q =at 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance. It hardware not inside is the automatic to have two function

45、 outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth. Output grade, P3 of mouth, P1 of P1, connect with inside have load resi

46、stance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source

47、resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer use of output electric currents, i

48、s it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1P3 Being restored to the throne is the operation of initializing of an one-ch

49、ip computer. Its main function is to turn PC into 0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament, need to be pressed and restored to the throne the key restarting