自動售貨機(jī)fpga與verilog代碼

1、深圳大學(xué)課程論文題目 設(shè)計一個自動售貨機(jī) 成績 專業(yè) 課程名稱、代碼 年級 姓名 學(xué) 號 時間 年 月 設(shè)計一個自動售貨機(jī)基本要求：可以對3種不同種類的貨物進(jìn)行自動售貨,價格分別為A=1.00, B=1.50, C=1.60。售貨機(jī)可以接受1元,5角,1角三種硬幣(即有三種輸入信號IY,IWJ,IYJ),并且在7段數(shù)碼管(二位代表元,一位代表角)顯示已投入的總錢數(shù),選擇貨物的輸入信號Ia,Ib,Ic,輸出指示信號為 Sa, Sb ,Sc 分別表示售出相應(yīng)的貨物,同時輸出的信號yuan, jiao代表找零，并顯示在7段數(shù)碼管上。規(guī)格說明：1. 按一下button1按鈕，表示購買貨物A，第一個LE

2、D燈亮；按兩下button1按鈕，表示購買貨物B，第二個LED燈亮；按三下button1按鈕，表示購買貨物C，第三個LED燈亮。2. LED燈亮后，開始輸入硬幣。button2按一下，輸入1元，按兩下，輸入兩元，以此類推；Button3按一下輸入5角，按兩下代表1元，以此類推；button4按一下輸入1角，按兩下輸入2角，以此類推。7段數(shù)碼管顯示已投入的總錢數(shù)，再次按下button1鍵，7段數(shù)碼管顯示找零數(shù)目，同時指示貨物的LED燈熄滅。 3. 本實驗使用FPGA板：Sparant6XC6SLX16CSG324C（建project時，需要選擇該芯片的型號）。論文要求：1. 論文的格式采用標(biāo)準(zhǔn)的

3、深圳大學(xué)以論文、報告等形式考核專用答題紙；2. 論文中應(yīng)完包括ASM圖, 以及VerilogHDL代碼，并且代碼應(yīng)該與ASM圖相一致.3. 論文應(yīng)包括該電路的VerilogHDL仿真.4. 論文應(yīng)該有FPGA開發(fā)的布局布線后結(jié)果.5. 報告應(yīng)該有實驗成功的開發(fā)板截圖.1. 狀態(tài)圖本設(shè)計需要2個狀態(tài)機(jī)，一個是售貨機(jī)工作狀態(tài)機(jī)，一個是按鍵消抖用的FSM2. Verilog 代碼：timescale 1ns / 1psmodule automat(clk_in,reset,cs,Led,seg,button1_in,button2_in,button3_in,button4_in ); input

4、clk_in,reset;input button1_in,button2_in,button3_in,button4_in;output 2:0 Led;output 3:0 cs;output 7:0 seg;reg 7:0 seg;reg 3:0 cs;reg 2:0 Led;reg 6:0 total;reg 4:0 state;reg 2:0 state1,state2,state3,state4;reg 4:0 cnt1,cnt2,cnt3,cnt4;reg button1,button2,button3,button4;reg 6:0 ones,tens;reg clk;reg

5、23:0 divcnt;parameter wait0 = 3'b001;parameter delay = 3'b010;parameter wait1 = 3'b100;parameter idle = 5'b00001;parameter selA = 5'b00010;parameter selB = 5'b00100;parameter selC = 5'b01000;parameter count = 5'b10000;always (posedge clk_in or negedge reset) / clk_div

6、iderbeginif (!reset)beginclk <= 1'b0;divcnt <= 0;endelse if (divcnt = 99999)beginclk <= 1'b1;divcnt <= 0;endelse if (divcnt = 49999)beginclk <= 1'b0;divcnt <= divcnt + 1;endelsedivcnt <= divcnt + 1; end always (posedge clk or negedge reset) / 7seg scan clk=1Khzbegini

7、f (!reset)begincs <= 4'b1101;seg <= 8'b00111000;endelse if (cs = 4'b1101)begincs <= 4'b1110;case(ones)0: seg <= 8'b10000001;1: seg <= 8'b11001111;2: seg <= 8'b10010010;3: seg <= 8'b10000110;4: seg <= 8'b11001100;5: seg <= 8'b10100100

8、;6: seg <= 8'b10100000;7: seg <= 8'b10001111;8: seg <= 8'b10000000;9: seg <= 8'b10000100;default: seg <= 8'b01110000; endcaseendelse if (cs = 4'b1110)begincs <= 4'b1101;case(tens)0: seg <= 8'b00000001;1: seg <= 8'b01001111;2: seg <= 8

9、9;b00010010;3: seg <= 8'b00000110;4: seg <= 8'b01001100;5: seg <= 8'b00100100;6: seg <= 8'b00100000;7: seg <= 8'b00001111;8: seg <= 8'b00000000;9: seg <= 8'b00000100;default: seg <= 8'b01110000; endcaseendendalways (total) /total decodebeginif

10、(total < 10 && total >= 0)begintens = 0;ones = total;endelse if (total < 20 && total >= 10)begintens = 1;ones = total - 10;endelse if (total < 30 && total >= 20)begintens = 2;ones = total - 20;endelse if (total < 40 && total >= 30)begintens = 3

11、;ones = total - 30;endelse if (total < 50 && total >= 40)begintens = 4;ones = total - 40;endelse if (total < 60 && total >= 50)begintens = 5;ones = total - 50;endelse if (total < 70 && total >= 60)begintens = 6;ones = total - 60;endelse if (total < 80 &am

12、p;& total >= 70)begintens = 7;ones = total - 70;endelse if (total < 90 && total >= 80)begintens = 8;ones = total - 80;endelse if (total < 100 && total >= 90)begintens = 9;ones = total - 90;endelsebegintens = 9;ones = 9;endendalways (posedge clk or negedge reset) /

13、undo key jitter fsm for button1_inbeginif (!reset)beginbutton1 <= 1'b0;cnt1 <= 0;state1 <= wait0;endelsebeginbutton1 <= 1'b0;case (state1)wait0: begin if (button1_in)state1 <= delay; elsestate1 <= wait0; end delay: begin if (cnt1 = 24) begincnt1 <= 0;if (button1_in)begin

14、button1 <= 1'b1;state1 <= wait1;endelsestate1 <= wait0; end else begincnt1 <= cnt1 + 1;state1 <= delay; end end wait1: beginif (button1_in)state1 <= wait1;elsestate1 <= wait0; end default: state1 <= wait0; endcaseendendalways (posedge clk or negedge reset) / undo key jitt

15、er fsm for button2_inbeginif (!reset)beginbutton2 <= 1'b0;cnt2 <= 0;state2 <= wait0;endelsebeginbutton2 <= 1'b0;case (state2)wait0: begin if (button2_in)state2 <= delay; elsestate2 <= wait0; end delay: begin if (cnt2 = 24) begincnt2 <= 0;if (button2_in)beginbutton2 <=

16、 1'b1;state2 <= wait1;endelsestate2 <= wait0; end else begincnt2 <= cnt2 + 1;state2 <= delay; end end wait1: beginif (button2_in)state2 <= wait1;elsestate2 <= wait0; enddefault: state2 <= wait0; endcaseendendalways (posedge clk or negedge reset) / undo key jitter fsm for but

17、ton3_inbeginif (!reset)beginbutton3 <= 1'b0;cnt3 <= 0;state3 <= wait0;endelsebeginbutton3 <= 1'b0;case (state3)wait0: begin if (button3_in)state3 <= delay; elsestate3 <= wait0; end delay: begin if (cnt3 = 24) begincnt3 <= 0;if (button3_in)beginbutton3 <= 1'b1;stat

18、e3 <= wait1;endelsestate3 <= wait0; end else begincnt3 <= cnt3 + 1;state3 <= delay; end end wait1: beginif (button3_in)state3 <= wait1;elsestate3 <= wait0; end default: state3 <= wait0; endcaseendendalways (posedge clk or negedge reset) / undo key jitter fsm for button3_inbegini

19、f (!reset)beginbutton4 <= 1'b0;cnt4 <= 0;state4 <= wait0;endelsebeginbutton4 <= 1'b0;case (state4)wait0: begin if (button4_in)state4 <= delay; elsestate4 <= wait0; end delay: begin if (cnt4 = 24) begincnt4 <= 0;if (button4_in)beginbutton4 <= 1'b1;state4 <= wait

20、1;endelsestate4 <= wait0; end else begincnt4 <= cnt4 + 1;state4 <= delay; end end wait1: beginif (button4_in)state4 <= wait1;elsestate4 <= wait0; end default: state4 <= wait0; endcaseendend always (posedge clk or negedge reset) /FSM for automatbeginif (!reset)begintotal <= 0;Led

21、 <= 3'b000;state <= idle;endelsebegincase (state)idle: begin Led <= 3'b000; if (button1)state <= selA; elsestate <= idle; end selA: begin total <= 0; Led <= 3'b100; if (button1) state <= selB; else if (button2) begin state <= count; total <= total + 10; end

22、else if (button3) begin state <= count; total <= total + 5; end else if (button4) begin state <= count; total <= total + 1; end else state <= selA; endselB: begin Led <= 3'b010; if (button1) state <= selC; else if (button2) begin state <= count; total <= total + 10; en

23、d else if (button3) begin state <= count; total <= total + 5; end else if (button4) begin state <= count; total <= total + 1; end else state <= selB; endselC: begin Led <= 3'b001; if (button2) begin state <= count; total <= total + 10; end else if (button3) begin state &l

24、t;= count; total <= total + 5; end else if (button4) begin state <= count; total <= total + 1; end else state <= selC; end count: begin if (button2) beginstate <= count;total <= total + 10; end else if (button3) beginstate <= count;total <= total + 5; end else if (button4) be

25、ginstate <= count;total <= total + 1; end else if (button1 && (total >= 10) && Led = 3'b100) begintotal <= total - 10;state <= idle; end else if (button1 && (total >= 15) && Led = 3'b010) begintotal <= total - 15;state <= idle; end else

26、 if (button1 && (total >= 16) && Led = 3'b001) begintotal <= total - 16;state <= idle; end elsestate <= count; enddefault: state <= idle;endcaseendendendmodule3. 仿真:Tb代碼：timescale 1ns / 1psmodule tb;reg clk_in;reg reset;reg button1_in;reg button2_in;reg button3_in;

27、reg button4_in;wire 3:0 cs;wire 2:0 Led;wire 7:0 seg;automat uut (.clk_in(clk_in), .reset(reset), .cs(cs), .Led(Led), .seg(seg), .button1_in(button1_in), .button2_in(button2_in), .button3_in(button3_in), .button4_in(button4_in);initial begin/ Initialize Inputsclk_in = 0;reset = 0;button1_in = 0;butt

28、on2_in = 0;button3_in = 0;button4_in = 0;#1000;reset = 1;#1000;button1_in = 1;#2000000button1_in = 0;#2000000button1_in = 1;#2000000button1_in = 0;#2000000button1_in = 1;#2000000button1_in = 0;#2000000button1_in = 1;#2000000button1_in = 0;#2000000button1_in = 1;#2000000button1_in = 0;#2000000button1

29、_in = 1; #50000000 button1_in = 0;/delay 50ms#50000000 button2_in = 1;#50000000button2_in = 0;#50000000button3_in = 1;#50000000button3_in = 0;#50000000button4_in = 1;#50000000button4_in = 0;#50000000button1_in = 1;#50000000button1_in = 0; endalways#5 clk_in = clk_in; endmodule把button1_in 仿真成與物理電路一樣

30、有大約十幾秒的抖動Button1 正確的忽略掉抖動產(chǎn)生的影響，產(chǎn)生了一個周期的脈沖買A=1元仿真的過程：button1一來state進(jìn)入買selA狀態(tài) button2一來state 進(jìn)入count狀態(tài)且total+10 （total=投進(jìn)錢總數(shù)剩10）即表示投進(jìn)了1元，button3一來 total = 15 表示投進(jìn)了1.5元,button4一來 total = 16 表示投了1.6元，最后按button1 出貨和找零，total=6表示找零0.6角4.實物展示：本設(shè)計下載平臺是 Nexys3 Board Ucf：#clkNet "clk_in" LOC=V10 | IO

31、STANDARD=LVCMOS33;Net "clk_in" TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;Net "reset" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0# LedsNet "Led<0>" LOC = U16 | IOSTANDARD = LVCMOS33; #Ba

32、nk = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0Net "Led<1>" LOC = V16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1Net "Led<2>" LOC = U15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2 #Net "seg<7>&quo

33、t; LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP# 7 segment displayNet "seg<6>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CANet "seg<5>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name

34、= IO_L51N_M1DQ13, Sch name = CBNet "seg<4>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CCNet "seg<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CDNet "seg<2>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CENet "seg<1>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF,