[物理][第6章] 組合電路構件塊ppt課件

1、組組 合合 電電 路路 構構 件件 塊塊延延 邊邊 大大 學學 工工 學學 院院電電 子子 信信 息息 通通 信信 學學 科科許許 一一 男男選選 擇擇 器器Multiplexers(mux)22 選選 1 選選 擇擇 器器(mux)3 s: 選擇選擇信信號號(select signal) W0, W1: 輸輸入信入信號號 (input signals) f: 輸輸出信出信號號 (output signal) sf0w01w12by1 mux 真值真值表表:2 選選 1 選選 擇擇 器器 圖圖 形形 符符 號號4w0w1f01ssf0w01w12by1 mux 真值真值表表:2by1 mux

2、圖圖形符形符號號5sf0w01w12by1 mux 真值真值表表:w0w1sf2 選選 1 選選 擇擇 器器(mux)電電 路路6w0w1sf2選選1選擇選擇器的器的Verilog HDL編編程程(1)module mux2to1 (w0, w1, s, f); input w0, w1, s; output f; assign f = s ? w1 : w0;endmodulesf0w01w17module mux2to1 (w0, w1, s, f); input w0, w1, s; output f; assign f = s ? w1 : w0;endmodule2選選1選擇選擇器的

3、器的Verilog HDL編編程程(2)module mux2to1 (w0, w1, s, f); input w0, w1, s; output reg f; always (w0, w1, s) f = s ? w1 : w0;endmodule82選選1選擇選擇器的器的Verilog HDL編編程程(3)module mux2to1 (w0, w1, s, f); input w0, w1, s; output reg f; always (w0, w1, s) f = s ? w1 : w0;endmodulemodule mux2to1 (w0, w1, s, f); input

4、w0, w1, s; output reg f; always (w0, w1, s) if (s=0) f=w0; else f=w1;endmodulemodule mux2to1 (w0, w1, s, f); input w0, w1, s; output f; assign f = s ? w1 : w0;endmodule測試測試程序程序Test Bench) ?要求要求1： 時時延延單單位位為為1ns, 時時延精度延精度為為100ps 2： 單單位位時時延延delay) = 50ns 3: 經(jīng)過經(jīng)過1個單個單位位時時延后延后選擇選擇w1, 4: 經(jīng)過經(jīng)過2個單個單位位時時延后延后

5、選擇選擇w0, 5: 經(jīng)過經(jīng)過4個單個單位位時時延后延后選擇選擇w1, 6: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w0, 7: 經(jīng)過經(jīng)過3個單個單位位時時延后延后選擇選擇w1,timescale 1ns/1nsmodule tb_mux2to1; reg 1:0 w; reg s; wire f; parameter DELAY=10;mux2to1 M2to1 (.w(w), .s(s), .f(f); /always #(DELAY/2) clk=clk; initial begin w=2b10; s=1b0; #DELAY s=1; #(DELAY*2) s=0; #(DELAY

6、*4) s=1; #(DELAY*2) s=0; #(DELAY*3) s=1; #(DELAY*100) $finish; endendmodule 測試測試程序程序Test Bench) 新建文件新建文件夾夾D:mux2to1) ModelSim 環(huán)環(huán)境境新建工程新建工程New-Project) 工程工程稱號稱號mux2to1) 建立新文件建立新文件mux2to1)建立新文件建立新文件tb_mux2to1)終終了了 編輯編輯程序程序 編編程程 主程序主程序編編程程測試測試程序程序 編編程程終終了了 Compile仿仿真真Simulate) 選擇測試選擇測試程序程序添加波形添加波形圖圖 運轉

7、運轉程序程序 否否 仿仿真結真結果果 4 選選 1 選選 擇擇 器器(mux)29 s: 選擇選擇信信號號(select signal) W0, W1: 輸輸入信入信號號 (input signals) f: 輸輸出信出信號號 (output signal) s1s0f00w001w110w011w34by1 mux 真值真值表表:4 選選 1 選選 擇擇 器器 圖圖 形形 符符 號號30w0w1f0001s14by1 mux 圖圖形符形符號號s1s0f00w001w110w211w34by1 mux 真值真值表表:1011w3w2s031s0f4 選選 1 選選 擇擇 器器 電電 路路s1s

8、0f00w001w110w211w34by1 mux 真值真值表表:s1w0w1w2w3301201101001ssssssss fwwww324選選1選擇選擇器的器的Verilog HDL編編程程(1)module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmodules1s0f00w001w110w211w34by1 mux 真值真值表表:33RTL (Register Transfer Level) 存存

9、放器放器傳輸級傳輸級module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmodule344選選1選擇選擇器的器的Verilog HDL編編程程(2)module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmodulemodu

10、le mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output reg f; always (*) if (s=2b00) f = w0; else if (s=2b01) f = w1; else if (s=2b10) f = w2; else f = w3;endmodule35RTL (Register Transfer Level) 存存放器放器傳輸級傳輸級module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0

11、 s; output reg f; always (*) if (s=2b00) f = w0; else if (s=2b01) f = w1; else if (s=2b10) f = w2; else f = w3;endmodule364選選1選擇選擇器的器的Verilog HDL編編程程(3)module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output reg f; always (*) if (s=2b00) f = w0; else if (s=2b01) f = w1; else

12、 if (s=2b10) f = w2; else f = w3;endmodulemodule mux4to1 (w, s, f); input 3:0 w; input 1:0 s; output reg f; always (w, s) if (s=0) f = w0; else if (s=1) f = w1; else if (s=2) f = w2; else f = w3;endmodule374選選1選擇選擇器的器的Verilog HDL編編程程(4)module mux4to1 (w, s, f); input 3:0 w; input 1:0 s; output reg f

13、; always (w, s) if (s=0) f = w0; else if (s=1) f = w1; else if (s=2) f = w2; else f = w3;endmodulemodule mux4to1 (w, s, f); input 3:0 w; input 1:0 s; output reg f; always (w, s) case (s) 0: f = w0; 1: f = w1; 2: f = w2; 3: f = w3;endmodule測試測試程序程序Test Bench) ?要求要求1： 時時延延單單位位為為1ns, 時時延精度延精度為為1ns 2： 單

14、單位位時時延延delay) = 50ns 3: 經(jīng)過經(jīng)過1個單個單位位時時延后延后選擇選擇w1, 4: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w3, 5: 經(jīng)過經(jīng)過4個單個單位位時時延后延后選擇選擇w2, 6: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w0, 7: 經(jīng)過經(jīng)過3個單個單位位時時延后延后選擇選擇w1,module mux4to1 (w0, w1, w2, w3, s, f); input w0, w1, w2, w3; input 1:0 s; output f; assign f=s1?(s0?w3:w2):(s0?w1:w0);endmoduletimescale 1ns

15、/1nsmodule tb_mux4to1; reg w0, w1, w2, w3; reg 1:0 s; wire f; parameter DELAY=50;mux4to1 M4to1 (.w0(w0), .w1(w1), .w2(w2), .w3(w3), .s(s), .f(f); initial begin w0=1b0; w1=1b1; w2=1b0; w3=1b1; s=2b0; #DELAY s=2b01; #(DELAY*2) s=2b11; #(DELAY*4) s=2b10; #(DELAY*20) s=2b00; #(DELAY*3) s=2b01; #(DELAY*3

16、00) $finish; endendmodule測試測試程序程序Test Bench) (1)要求要求1： 時時延延單單位位為為1ns, 時時延精度延精度為為1ns 2： 單單位位時時延延delay) = 50ns 3: 經(jīng)過經(jīng)過1個單個單位位時時延后延后選擇選擇w1, 4: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w3, 5: 經(jīng)過經(jīng)過4個單個單位位時時延后延后選擇選擇w2, 6: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w0, 7: 經(jīng)過經(jīng)過3個單個單位位時時延后延后選擇選擇w1,s1s0f00w001w110w211w3ModelSim時時序仿序仿真結真結果果圖圖(1) Model

17、Sim時時序仿序仿真結真結果果圖圖(2) timescale 1ns/1nsmodule tb_mux4to1; reg 3:0 w; reg 1:0 s; wire f; parameter DELAY=50;mux4to1 M4to1 (.w(w), .s(s), .f(f); initial begin w=4b0101; s=2b0; #DELAY s=2b01; #(DELAY*2) s=2b11; #(DELAY*4) s=2b10; #(DELAY*20) s=2b00; #(DELAY*3) s=2b01; #(DELAY*300) $finish; endendmodule測

18、試測試程序程序Test Bench) (2)要求要求1： 時時延延單單位位為為1ns, 時時延精度延精度為為1ns 2： 單單位位時時延延delay) = 50ns 3: 經(jīng)過經(jīng)過1個單個單位位時時延后延后選擇選擇w1, 4: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w3, 5: 經(jīng)過經(jīng)過4個單個單位位時時延后延后選擇選擇w2, 6: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w0, 7: 經(jīng)過經(jīng)過3個單個單位位時時延后延后選擇選擇w1,s1s0f00w001w110w211w3module mux4to1 (w, s, f); input 3:0 w; input 1:0 s; outpu

19、t reg f; always (w, s) if (s=0) f = w0; else if (s=1) f = w1; else if (s=2) f = w2; else f = w3;endmoduleModelSim時時序仿序仿真結真結果果圖圖(2) 442選選1選擇選擇器器來實現(xiàn)來實現(xiàn)4選選1選擇選擇器器w0w101w2w301f01s0s1s1s0f00w001w110w211w34by1 mux 真值真值表表:M0M145Verilog HDL編編程程module mux2to1 (w,s,f); input 1:0 w; input s; output f; assign f

20、=s?w1:w0;endmodulemodule mux4to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmodule46Verilog HDL測試測試程序？程序？module mux2to1 (w,s,f); input 1:0 w; input s; output f; assign f=s?w1:w0;endmodulemodule mux4

21、to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmodule測試測試程序程序Test Bench) 要求要求1： 時時延延單單位位為為1ns, 時時延精度延精度為為1ns 2： 單單位位時時延延delay) = 50ns 3: 經(jīng)過經(jīng)過1個單個單位位時時延后延后選擇選擇w1, 4: 經(jīng)過經(jīng)過2個單個單位位時時延后延后選擇選擇w3, 5: 經(jīng)過經(jīng)過4

22、個單個單位位時時延后延后選擇選擇w2, 6: 經(jīng)過經(jīng)過6個單個單位位時時延后延后選擇選擇w0, 7: 經(jīng)過經(jīng)過1個單個單位位時時延后延后選擇選擇w1,timescale 1ns/1nsmodule tb_mux4to1; reg 3:0 w; reg 1:0 s; wire f; parameter DELAY=50;mux4to1 M4to1 (.w(w), .s(s), .f(f); initial begin w=4b0101; s=2b0; #DELAY s=2b01; #(DELAY*2) s=2b11; #(DELAY*4) s=2b10; #(DELAY*6) s=2b00; #

23、(DELAY*1) s=2b01; #(DELAY*30) $finish; endendmodulemodule mux4to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmoduleModelSim時時序仿序仿真結真結果果圖圖498 選選 1 選選 擇擇 器器 (RTL)508選選1選擇選擇器的器的Verilog HDL編編程程1module m

24、ux4to1 (w,s,f); input 3:0 w; input 1:0 s; output f; wire 1:0 M; mux2to1 mux1 (w1:0, s0, M0); mux2to1 mux2 (w3:2, s0, M1); mux2to1 mux3 (M1:0, s1, f);endmodulemodule mux2to1 (w,s,f); input 1:0 w; input s; output f; assign f=s?w1:w0;endmodulemodule mux8to1 (w,s,f); input 7:0 w; input 2:0 s; output f;

25、wire 1:0 M; mux4to1 mux1 (w3:0,s1:0,M0); mux4to1 mux2 (w7:4,s1:0,M1); mux2to1 mux3 (M1:0,s2,f);endmodule518選選1選擇選擇器的器的測試測試程序程序timescale 1ns/1nsmodule tb_mux8to1; reg 7:0 w; reg 2:0 s; wire f; parameter DELAY=50;mux8to1 M8to1 (.w(w), .s(s), .f(f); initial begin w=8b00110101; s=3b010; #DELAY s=3b011;

26、#DELAY s=3b001; #DELAY s=3b101; #DELAY w=8b1100010; s=3b001; #DELAY s=3b010; #DELAY s=3b100; #DELAY s=3b110; #DELAY w=8b10111001; s=3b101; #DELAY w=8b11000011; s=3b100; #DELAY s=3b100; #(DELAY*30) $finish; endendmodulemodule mux8to1 (w,s,f); input 7:0 w; input 2:0 s; output f; wire 1:0 M; mux4to1 mu

27、x1 (w3:0,s1:0,M0); mux4to1 mux2 (w7:4,s1:0,M1); mux2to1 mux3 (M1:0,s2,f);endmodule52ModelSim 時時序仿序仿鎮(zhèn)結鎮(zhèn)結果果536 選選 1 選選 擇擇 器器546選選1選擇選擇器的器的Verilog HDL程序程序module mux6to1(w,s,f); input 5:0w; input 2:0 s; output reg f; always(w,s) if(s=3b000) f=w0; else if(s=3b001) f=w1; else if(s=3b010) f=w2; else if(s=3

28、b011) f=w3; else if(s=3b100) f=w4; else if(s=3b101) f=w5; else f=f;endmoduleRTL (Register Transfer Level) 存存放器放器傳輸級傳輸級566選選1選擇選擇器的器的Quartus2時時序仿序仿真真576選選1選擇選擇器的器的測試測試程序程序timescale 1ns/1nsmodule tb_mux6to1; reg 5:0 w; reg 2:0 s; wire f;mux6to1 M_6to1 (.w(w), .s(s), .f(f);initial begin s=3b000; w=6b00

29、0001; #50 s=3b001; w=6b000100; #50 s=3b010; w=6b000110; #50 s=3b011; w=6b100110; #50 s=3b100; w=6b010001; #50 s=3b101; w=6b011111; #50 s=3b110; w=6b111111; #150 s=3b111;endendmodulemodule mux6to1(w,s,f); input 5:0w; input 2:0 s; output reg f; always(w,s) if(s=3b000) f=w0; else if(s=3b001) f=w1; else

30、 if(s=3b010) f=w2; else if(s=3b011) f=w3; else if(s=3b100) f=w4; else if(s=3b101) f=w5; else f=f;endmoduleModelSim時時序仿序仿真結真結果果圖圖5916選選1選擇選擇器的器的Verilog HDL編編程程1： 5個個4選選1選擇選擇器器2： 2個個8選選1選擇選擇器器 + 1個個2選選1選擇選擇器器3： 15個個2選選1選擇選擇器器6016選選1選擇選擇器的器的Verilog HDL編編程程module mux16to1 (w, s, f); input 15:0 w; input

31、3:0 s; output f; wire 3:0 m; mux4to1 Mux1 (w3:0, s1:0, m0); mux4to1 Mux2 (w7:4, s1:0, m1); mux4to1 Mux3 (w11:8, s1:0, m2); mux4to1 Mux4 (w15:12, s1:0, m3); mux4to1 Mux5 (m3:0, s3:2, f);endmoduleRTL (Register Transfer Level) 存存放器放器傳輸級傳輸級62多多 路路 選選 擇擇 器器 (1)w1w2f000011101110真值真值表表:f = W1 W2f = W1 W2+邏

32、輯邏輯函函數(shù)數(shù):63多多 路路 選選 擇擇 器器 (2)w1w2f000011101110真值真值表表:01f0001w14by1 mux 圖圖形符形符號號101101w264多多 路路 選選 擇擇 器器 (3)w1w2f000011101110真值真值表表:w1f0w21w2If (w1 = 0) f = w2;else f = w2 65多多 路路 選選 擇擇 器器 (4)真值真值表表:w1f0w21w2w0w1f01If (w1 = 0) f = w2;else f = w2 664選選1多路器多路器來實現(xiàn)來實現(xiàn)三三輸輸入表入表決決器器真值真值表表:w1w2w3f000000100100

33、01111000101111011111w1w2f00001w310w31110w3f1w1w267譯譯 碼碼 器器Decoder68譯碼譯碼器器 (n-to-m decoder)- 在數(shù)字系統(tǒng)當中在數(shù)字系統(tǒng)當中, 離散的情報量可以由二進制離散的情報量可以由二進制(binary)數(shù)來表示數(shù)來表示- 實踐上實踐上, ASIC運用領域當中譯碼器運用領域當中譯碼器(decoder)是最多運用的是最多運用的- n位數(shù)的二進制數(shù)輸入信號可以轉換為位數(shù)的二進制數(shù)輸入信號可以轉換為 個不同的輸出信號個不同的輸出信號- 譯碼器譯碼器 - - Decoder - - n-to-m 譯碼器譯碼器 (m = ) -

34、 dec2to4, dec3to8 n2n269n位輸入位輸入 位輸出位輸出 譯碼器譯碼器 .Wn-1EnW0.Y012nyn位位輸輸入入使能使能(enable)n2位位輸輸出出binary decodernton2n2702到到4 譯碼譯碼器器 (2-to-4 decoder)真值真值表表:W0W1EnY0Y1Y2Y3圖圖形符形符號號EnW1W0Y3Y2Y1Y010000011010010110010011110000XX0000712 到到 4 譯譯 碼碼 器器 的的 邏邏 輯輯 電電 路路W1Y0Y1Y2Y3W0En邏輯電邏輯電路路真值真值表表:EnW1W0Y3Y2Y1Y01000001

35、1010010110010011110000XX0000722到到4譯碼譯碼器的器的Verilog HDL 編編程程(1)真值真值表表:module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (En, W) case (En, W) 3b100: Y = 4b0001; 3b101: Y = 4b0010; 3b110: Y = 4b0100; 3b111: Y = 4b1000; default: Y = 4b0000; endcaseendmoduleEnW1W0Y3Y2Y1Y0100000110

36、10010110010011110000XX0000732到到4譯碼譯碼器的器的Verilog HDL編編程程(2)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (W, En) begin if (En = 0) Y = 4b0000; else case (W) 0: Y = 4b0001; 1: Y = 4b0010; 2: Y = 4b0100; 3: Y = 4b1000; endcase endendmodulemodule dec2to4 (W, En, Y); input 1:

37、0 W; input En; output reg 3:0 Y; always (En, W) case (En, W) 3b100: Y = 4b0001; 3b101: Y = 4b0010; 3b110: Y = 4b0100; 3b111: Y = 4b1000; default: Y = 4b0000; endcaseendmodule742到到4譯碼譯碼器的器的Verilog HDL編編程程(3)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (W, En) begin if (E

38、n = 0) Y = 4b0000; else case (W) 0: Y = 4b0001; 1: Y = 4b0010; 2: Y = 4b0100; 3: Y = 4b1000; endcase endendmodulemodule dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; integer k; always (W, En) for (k = 0; k = 3; k = k+1) if (W = k) & (En = 1) Yk = 1; else Yk = 0;endmodule752到到4 譯碼譯

39、碼器的器的時時序仿序仿真真(Quartus II)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (En, W) case (En, W) 3b100: Y = 4b0001; 3b101: Y = 4b0010; 3b110: Y = 4b0100; 3b111: Y = 4b1000; default: Y = 4b0000; endcaseendmoduleRTL (Register Transfer Level) : 存放器存放器傳輸級傳輸級76分析分析時時序仿序仿真結真結果果772到

40、到4 譯碼譯碼器的器的時時序仿序仿真真 (2)module dec2to4 (W, En, Y); input 1:0 W; input En; output reg 3:0 Y; always (W, En) begin if (En = 0) Y = 4b0000; else case (W) 0: Y = 4b0001; 1: Y = 4b0010; 2: Y = 4b0100; 3: Y = 4b1000; endcase endendmoduleRTL:782到到4 譯碼譯碼器的器的時時序仿序仿真真 (3)module dec2to4 (W, En, Y); input 1:0 W;

41、 input En; output reg 3:0 Y; integer k; always (W, En) for (k = 0; k B; AgtB = 1,A B) AgtB = 1; else AltB = 1; endendmodule4 位位 算算 術術 比比 較較 器器 的的 RTL4 位位 算算 術術 比比 較較 器器 的的 時時 序序 仿仿 真真 begin AeqB = 0; AgtB = 0; AltB = 0; if (A = B) AeqB = 1; else if (A B) AgtB = 1; else AltB = 1; end132移移 位位 器器Shift

42、Register133 移移 位位 器器 (Shift Register)輸輸入信入信號號:向右挪向右挪動動1位位:Clock:?DCB輸輸出信出信號號:輸輸入信入信號號:輸輸出信出信號號:MSBLSB?D DCBADCBA134 移移 位位 器器 (Shift Register)shift : 控制信控制信號號W : w3 w2 w1 w0: 4位位輸輸入信入信號號Y : Y3 Y2 Y1 Y0: 4位位輸輸出信出信號號Step 1: If (shift = 1) 向右挪向右挪動動1位位(W);Step 2 Y ?Setp 3: else Y ?Y3 = 0, Y2 = w3, Y1 = w

43、2, Y0 = w1Y = W, k = 0135 移移 位位 器器 的的 邏邏 輯輯 電電 路路 圖圖1010101010shiftY3Y2Y1Y0k0W3W2W1W00136 移位器移位器(向右向右)的的Verilog HDL編編程程 (1)module shift4 (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin Y

44、= W; k = 0; end endendmoduleW3W2W1W0Y3 Y2 Y1 Y00W3W2W1k輸輸入信入信號號:向右挪向右挪動動1位位:輸輸出信出信號號:137 移位器的移位器的Verilog HDL編編程程 (2)module shifter (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y = W 1; k = W0; end else begin Y = W; k = 0; end en

45、dendmodulemodule shift4 (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin Y = W; k = 0; end endendmodulealways (W, Shift) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin

46、Y = W; k = 0; end end時時序仿序仿真真1時時序仿序仿真真2 always (W, Shift) begin if (Shift) begin Y = W 1; k = W0; end else begin Y = W; k = 0; end endRTLmodule shifter (W, Shift, Y, k); input 3:0 W; input Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y = W 1; k = W0; end else begin

47、 Y = W; k = 0; end endendmodule時時序仿序仿真真 (clk)3module test (clk, Shift, W, Y, k); input clk, Shift; input 3:0 W; output reg 3:0 Y; output reg k; always (posedge clk) begin if (Shift) begin Y3 = 0; Y2:0 = W3:1; k = W0; end else begin Y = W; k = 0; end endendmodulemodule shifter (clk, W, Shift, Y, k);

48、input clk, Shift; input 3:0 W; output reg 3:0 Y; output reg k; always (posedge clk) begin if (Shift) begin Y = W 1; k = W0; end else begin Y = W; k = 0; end endendmodule時時序仿序仿真真 (clk)4串型移位器串型移位器 (右初始右初始值值=0A = rtin, A3:1;移位器移位器右右1位位CLK串型串型輸輸入信入信號號rtin)Clear串型串型輸輸出信出信號號(A)- - - - 1 0 1 10000 (初始初始100

49、0 (1st)1100 (2nd)0110 (3rd)1011 (4th)串型移位器串型移位器 (右的分解右的分解A = rtin, A3:1;3210In210rtinA3:13初始形初始形狀狀：移位形移位形狀狀：3102最最終終形形狀狀：module test (CLK, Clr, rtin, A); input CLK, Clr; / clock and clear input rtin; / serial input output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if

50、(Clr) A = 4b0000; else A = rtin, A3:1; endendmoduleVerilog HDL 編編程程時時序仿序仿真真time simulation)module test (CLK, Clr, rtin, A); input CLK, Clr; / clock and clear input rtin; / serial input output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = 4b0000; else A = rti

51、n, A3:1; endendmodule串型移位器串型移位器 (右右)初始初始值值=datamodule test (CLK, Clr, rtin, DataIn, A); input CLK, Clr; / clock and clear input rtin; / serial input input 3:0 DataIn; / input data output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = DataIn; else A = rtin, A3

52、:1; endendmodule移位器的移位器的運運用用(bit to byte)CLK串型串型輸輸入信入信號號Bit)Clear輸輸出信出信號號(Byte)組組合器合器(記數(shù)記數(shù)器器,移位器移位器- - 1 0 1 1 1 0 1 1Message Signal10111011- 串型串型輸輸入入(Bit)- 組組合合8位位數(shù)數(shù)的的Byte- 1Byte 信信號輸號輸出出時輸時輸出出message 信信號號移位器的移位器的運運用用(bit to byte)串型串型輸輸入信入信號號Bit)輸輸出信出信號號(Byte)記數(shù)記數(shù)器器移位器移位器輸輸出信出信號號(Message)Verilog HD

53、L 編編程程module test (CLK, Clr, Bit, Byte, FirstByteSignal, zBitCnt); input CLK, Clr; input Bit; output 7:0 Byte; output FirstByteSignal; output 3:0 zBitCnt; reg 7:0 Byte; reg FirstByteSignal; reg 3:0 zBitCnt;always (posedge CLK or negedge Clr) begin if (Clr) begin zBitCnt = 4d0; Byte = 8d0; FirstByteS

54、ignal = 1b0; end else begin Byte = Bit, Byte7:1; zBitCnt = zBitCnt + 1b1; if(zBitCnt=4d8) FirstByteSignal = 1b1; else FirstByteSignal = 1b0; end endendmodule時時序仿序仿真真time simulation)輸輸入信入信號號： 1 1 0 1 1 1 0 1LSBMSB 移位器移位器(向左向左)的的Verilog HDL編編程程 (1)152module shift4 (W, Shift, Y, k); input 3:0 W; input

55、Shift; output reg 3:0 Y; output reg k; always (W, Shift) begin if (Shift) begin Y0 = 0; Y3:1 = W2:0; k = W3; end else begin Y = W; k = 0; end endendmoduleW3W2W1W0Y3 Y2 Y1 Y0kW2W10輸輸入信入信號號:向左挪向左挪動動1位位:輸輸出信出信號號:W0時時序仿序仿真真1 always (W, Shift) begin if (Shift) begin Y0 = 0; Y3:1 = W2:0; k = W3; end else

56、begin Y = W; k = 0; end end時時序仿序仿真真2 always (W, Shift) begin if (Shift) begin Y = W 1; k = W3; end else begin Y = W; k = 0; end end串型移位器串型移位器 (左左)初始初始值值=0A = A2:0, rtin;移位器移位器右右1位位CLK串型串型輸輸入信入信號號rtin)Clear串型串型輸輸出信出信號號(A)- - - - 1 0 1 10000 (初始初始0001 (1st)0011 (2nd)0110 (3rd)1100 (4th)串型移位器串型移位器 (左左)

57、的分解的分解3210In210rtinA2:03初始形初始形狀狀：移位形移位形狀狀：3102最最終終形形狀狀：A = A2:0, rtin;module test (CLK, Clr, rtin, DataIn, A); input CLK, Clr; / clock and clear input rtin; / serial input input 3:0 DataIn; / input data output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = Da

58、taIn; else A = A2:0, rtin; endendmoduleVerilog HDL 編編程程時時序仿序仿真真module test (CLK, Clr, rtin, DataIn, A); input CLK, Clr; / clock and clear input rtin; / serial input input 3:0 DataIn; / input data output 3:0 A; / output signal reg 3:0 A;always (posedge CLK or negedge Clr) begin if (Clr) A = DataIn; e

59、lse A = A2:0, rtin; endendmoduleMemory(存存儲儲器器Memory存存儲儲器器MemoryRAM (Random Access Memory) (隨隨機存取存機存取存儲儲器器)ROM (Read Only Memory) (只只讀讀存存儲儲器器) Digital LogicROMRAMRAMRandom Access Memory)- 可可寫寫 (Memory Write Operation)- 可可讀讀 (Memory Read Operation)- bit byte words- 16 bit = 2 byte = 1 wordsRAM的模的模塊圖塊圖

60、Memory unitn數(shù)數(shù)據(jù)據(jù)輸輸入入線線(n data input lines)N數(shù)數(shù)據(jù)據(jù)輸輸出出線線(n data output lines)K 地址地址線線(K address lines)讀讀(Read)寫寫(Write)例例: 1024 x 16 Memory 內內容容二進制(binary)十進制(decimal)Memory contest000000000001011010101011101000000000111010101110001001000000001020000110101000110111111110110211010001110001100111111111010220