eap項(xiàng)目總結(jié)報(bào)告13p

1、驗(yàn)一:譯碼器及計(jì)數(shù)器設(shè)計(jì)實(shí)驗(yàn)1、實(shí)驗(yàn)?zāi)康?）復(fù)習(xí)二進(jìn)制譯碼器的功能。2）學(xué)習(xí)VHDL語(yǔ)言源程序輸入方法。3）學(xué)習(xí)VHDL語(yǔ)言源程序檢查和修改。4）掌握用VHDL語(yǔ)言設(shè)計(jì)一個(gè)3線-8線譯碼器和六十進(jìn)制計(jì)數(shù)器的方 法。5）掌握VHDL語(yǔ)言編輯器的基本操作。2、實(shí)驗(yàn)內(nèi)容1）本實(shí)驗(yàn)給出了有錯(cuò)誤的3線一8線譯碼器的VHDL程序，請(qǐng)采用VHDL 編輯器，修改調(diào)試程序。2）采用VHDL設(shè)計(jì)方法，設(shè)計(jì)一個(gè)60進(jìn)制計(jì)數(shù)器，采用BCD碼輸出。3、實(shí)驗(yàn)步驟（一）、38譯碼器1、分析3 8入譯碼器原理，設(shè)計(jì)相應(yīng)端口以及信號(hào)輸入輸出變量等。2、其中為三位XG2A、G2政為三個(gè)輸入控制端。只有當(dāng)譯碼器才X處于全為高電平。

2、1111110 1 r000000000000000001111則0、0110011TTj o11G譯碼器將處在禁止?fàn)?010101111111011111G1、1 豐 1, G2A= 0,G2B= 0 時(shí)，譯1態(tài)1態(tài)、11110111110111打11011111 .所有輸出端1 0111110111111101111111(二)、設(shè)計(jì)一個(gè)60進(jìn)制計(jì)數(shù)器，采用 BCD碼輸出。1) BCD碼：用4位二進(jìn)制數(shù)編碼表示1位十進(jìn)制數(shù)2) 一個(gè)十進(jìn)制計(jì)數(shù)器即為一個(gè)4位二進(jìn)制計(jì)數(shù)器，若將兩個(gè) 4位二進(jìn)制計(jì)數(shù)器連接起來(lái)就可構(gòu)成100進(jìn)制以?xún)?nèi)的計(jì)數(shù)器。實(shí)驗(yàn)程序1、3-8譯碼器library IEEE;use

3、 IEEE . STD_LOGIC_1164 .ALL;use IEEE . STD_LOGIC_ARITH .ALL;use IEEE . STD_LOGIC_UNSIGNED.ALL;-Uncomment the following lines to use the declarations that are-provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity T138 isport(A,B,C,G1,G2A,G2B:inst

4、do gic;Y:outstdo gic_vector(7 dow nto 0);end T138;architecture Behavioral of T138 issig nal DN:stdo gic_vector(2 dow nto 0);beg inD_IN<=C&B&A;process(DN,G1,G2A,G2B) beg inif(G1='1' and G2A='0' and G2B='0') then case DN iswhen "000" =>Y<= "00000

5、001"when "001"=>Y<= "00000010"when "010"=>Y<= "00000100"when "011"=>Y<= "00001000"when "100"=>Y<= "00010000"when "101"=>Y<= "00100000"when "110"=>Y<=

6、 "01000000"when "111"=>Y<= "10000000"whe n others=>n ull; end case;else Y<="11111111"end if;end process;end Behavioral;仿真結(jié)果:1o01III IIHnIHHIIII HI Hiul IIIII|» ill IIIIII H H IIIIIIIIl l|lIHilTlIIIagro煩障印吸30005- UOn*IpTi2.60進(jìn)制計(jì)數(shù)器實(shí)驗(yàn)程序：library I

7、EEE;- Un comme nt the followi ng lines to use the declarati ons that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity jishuqi isport(clk:in std_logic;en ,clr:i n std_logic; q,qd:out stdogic_vector(3 downto 0); end jishuqi;architecture

8、Behavioral of jishuqi issig nal co:std_logic;signal ql,qh:stdogic_vector(3 downto 0); beg in q( 3)<=qh (3);q( 2)<=qh (2);q(1)<=qh(1); q(0)<=qh(0); qd( 3)<=ql(3); qd(2) <=ql (2);qd(1)<=ql(1);qd(0)<=ql(0);P1:process(clk,e n,clr)begi nif (clr='1') then ql<="0000&

9、quot;elsif (clk'event and clk='1') thenif (en='1') thenif (ql="1001") the n ql<="0000"elseql<=ql+'1' end if;end if;end if;end process P1; co<=ql(3) and ql(0);P2:process(clk,clr)begi nif (clr='1') then qh<="0000"elsif(clk&#

10、39;eve nt and clk='1') the n if (co='1') the n if (qh="0101") then qh<="0000"else qh<=qh+'1'end if;end if;end if;end process P2;end Behavioral;rjimnjiiEIJL0LTLHrLJmrLru卜國(guó)h C1J1- ' oo j0ETUlHrtr網(wǎng)ij卿廉郎醐;山切晦酈帥to車(chē)10? IBSI rl1 bLTLH和ruKVa fii1 uGct r

11、tmcra前 k 21 - fi'i L (pirirLRHrun仿真結(jié)果實(shí)驗(yàn)二、四位全加器和8位移位寄存器設(shè)計(jì)實(shí)驗(yàn)1、實(shí)驗(yàn)?zāi)康?）學(xué)習(xí)了解加法器工作原理。2）學(xué)習(xí)用VHDL語(yǔ)言設(shè)計(jì)全加器的設(shè)計(jì)方法。3）學(xué)習(xí)使用元件例化的方法設(shè)計(jì)多位加法器。4）了解移位寄存器的工作原理5）學(xué)習(xí)移位寄存器設(shè)計(jì)方法2、實(shí)驗(yàn)內(nèi)容1）用VHDL語(yǔ)言設(shè)計(jì)全加器。2）用元件例化方法設(shè)計(jì)一個(gè)四位二進(jìn)制加法器。3）用VHDL語(yǔ)言設(shè)計(jì)一個(gè)雙向可控移位寄存器3、實(shí)驗(yàn)步驟1）4位二進(jìn)制加法器可以由4個(gè)一位全加器通過(guò)級(jí)聯(lián)的方式構(gòu)成。全加器：完成加數(shù)、被加數(shù)、低位的進(jìn)位數(shù)三個(gè)1位數(shù)相加，并產(chǎn)生本位和 及向高位進(jìn)位”。2）移位寄

12、存器是由D-型觸發(fā)器構(gòu)成的，將前一個(gè)觸發(fā)器的輸出作為下一個(gè)觸發(fā)器的輸入，每個(gè)觸發(fā)器的時(shí)鐘連接成同步方式。常用的移位寄存器有并行輸入串行輸出移位寄存器和串行輸入并行輸出移位寄存器。這些移位寄存器經(jīng)常用作串并轉(zhuǎn)換電路。試驗(yàn)程序：1. 用元件例化方法設(shè)計(jì)一個(gè)四位二進(jìn)制加法器 全加器：library IEEE;- Un comme nt the followi ng lines to use the declarati ons that are - provided for instantiating Xilinx primitive components.-library UNISIM;-use U

13、NISIM.VCompo nen ts.all;en tity qua njia isport (a,b,ci n:in stdo gic;cout,sum:out std_logic);end qua njia;architecture Behavioral of qua njia issig nal int: std_logic;beg inint <= a xor b ;cout <=(a and b) or (int and cin);sum <= int xor cin;end Behavioral;library IEEE;- Un comme nt the fo

14、llowi ng lines to use the declarati ons that are - provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity siwei isgen eric (n:i nteger:= 4 );port (a,b:in stdogic_vector(n downto 1);cin: in std_logic;sum: out std_logic_vect or(n dow nto 1);cout: o

15、ut std_logic); end siwei;architecture Behavioral of siwei is comp onent qua njiaport (a,b,ci n:in stdo gic; sum,cout:out std_logic);end comp onent;sig nal carry: stdo gic_vector( n dow nto 1);beg inU1: quanjia port map(a(1),b(1),ci n,sum(1),carry(1);U2: quanjia port map(a(2),b(2),carry(1),sum(2),car

16、ry(2);U3: quanjia port map(a(3),b(3),carry(2),sum(3),carry(3);U4: quanjia port map(a(4),b(4),carry(3),sum(4),cout); end Behavioral;實(shí)驗(yàn)截圖：2. 用VHDL語(yǔ)言設(shè)計(jì)一個(gè)8位雙向可控移位寄存器程序代碼：library IEEE;- Uncomment the following lines to use the declarations that are-provided for instantiating Xilinx primitive components. -library UNISIM;entity yiwei is port(Dim:in std_logic;S:in stdo gic; clk:in std_logic; Q:out stdo gic_vector(7 downto 0); end yiwei;architecture Behavioral of yiwei is signal qtemp:stdo gic_vector(7 downto 0):="00000000" beginprocess(clk,S)begin if(clk'event and clk=&