出租車計(jì)費(fèi)器VHDL語(yǔ)言

1、數(shù)字邏輯電路課程設(shè)計(jì) 出租車計(jì)費(fèi)器的設(shè)計(jì)計(jì)算機(jī)學(xué)院 軟件工程1401趙雷 3140608027出租車計(jì)費(fèi)器的設(shè)計(jì)1、 系統(tǒng)設(shè)計(jì)任務(wù)及要求（1） 能實(shí)現(xiàn)計(jì)費(fèi)功能，計(jì)費(fèi)標(biāo)準(zhǔn)為：按行駛里程收費(fèi)，起步價(jià)為7.00元，并在車行3千米后再按2元/千米，當(dāng)總費(fèi)用達(dá)到或超過40元時(shí)，每千米收費(fèi)4元，客戶端需要停車等待時(shí)按時(shí)間收費(fèi)，計(jì)費(fèi)單價(jià)每20秒1元。（2） 設(shè)計(jì)動(dòng)態(tài)掃描電路：以十進(jìn)制顯示出租車行駛的里程與車費(fèi)，在數(shù)碼管上顯示（前四個(gè)顯示里程，后三個(gè)顯示車費(fèi)）。（3） 用VHDL語(yǔ)言設(shè)計(jì)符合上述功能要求的出租車計(jì)費(fèi)器，并用層次化設(shè)計(jì)方法設(shè)計(jì)該電路。（4） 完成電路全部設(shè)計(jì)后，通過系統(tǒng)試驗(yàn)箱下載驗(yàn)證設(shè)計(jì)的正確性

2、。2、 系統(tǒng)設(shè)計(jì)方案根據(jù)系統(tǒng)設(shè)計(jì)設(shè)計(jì)要求不難得知，整個(gè)出租車計(jì)費(fèi)系統(tǒng)按功能主要分為速度選擇模塊、計(jì)程模塊、計(jì)時(shí)模塊、計(jì)費(fèi)模塊4個(gè)模塊。頂層原理圖1. 速度模塊：通過對(duì)速度信號(hào)sp的判斷，決定行使的路程，這里是通過速度信號(hào)來(lái)模擬一個(gè)變量的取值。如kinside變量，其含義是行進(jìn)100m所需的時(shí)鐘周期數(shù)，然后每行進(jìn)100m，則產(chǎn)生一個(gè)脈沖clkout來(lái)驅(qū)動(dòng)計(jì)費(fèi)模塊。VHDL語(yǔ)言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Taxi_part1 is port(clk,reset,st

3、art,stop:in std_logic; sp :in std_logic_vector(2 downto 0); clkout :out std_logic);end Taxi_part1;architecture behavior of Taxi_part1 isbegin process(clk,reset,stop,start,sp) type state_type is(s0,s1); variable s_state:state_type; variable cnt:integer range 0 to 1400; variable kinside:integer range

4、0 to 1400;begin case sp is when "000"=> kinside:=0; when "001"=> kinside:=1400; when "010"=> kinside:=1200; when "011"=> kinside:=1000; when "100"=> kinside:=800; when "101"=> kinside:=600; when "110"=> kinsid

5、e:=400; when "111"=> kinside:=200; end case; if(reset='1') then s_state:=s0; elsif(clk'event and clk='1') then case s_state is when s0=> cnt:=0;clkout<='0' if(start='1') then s_state:=s1; else s_state:=s0; end if; when s1=> clkout<='0&

6、#39; if(stop='1') then s_state:=s0; -相當(dāng)于無(wú)客戶上車 elsif(sp="000") then s_state:=s1; -有客戶上車，但車速位0，即客戶剛上車還未起步 elsif(cnt=kinside) then cnt:=0;clkout<='1' s_state:=s1; else cnt:=cnt+1; s_state:=s1; end if; end case; end if; end process;end behavior;2.計(jì)程模塊：由于一個(gè)clkout信號(hào)代表行進(jìn)100m，故通

7、過對(duì)clkout計(jì)數(shù)，可以獲得共行進(jìn)的距離kmcount。VHDL語(yǔ)言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Taxi_part2 is port(clkout,reset:in std_logic; kmcnt1:out std_logic_vector(3 downto 0); kmcnt2:out std_logic_vector(3 downto 0); kmcnt3:out std_logic_vector(3 downto 0);end Taxi_part2;a

8、rchitecture behavior of Taxi_part2 isbegin process(clkout,reset) variable km_reg:std_logic_vector(11 downto 0);begin if(reset='1') then km_reg:="000000000000" elsif(clkout'event and clkout='1') then -km_reg(3 downto 0)對(duì)應(yīng)里程十分位 if(km_reg(3 downto 0)="1001")then

9、km_reg:=km_reg+"0111" -十分位向個(gè)位的進(jìn)位處理 else km_reg(3 downto 0):=km_reg(3 downto 0)+"0001" end if; if(km_reg(7 downto 4)="1010")then km_reg:=km_reg+"01100000" -個(gè)位向十位的進(jìn)位處理 end if;end if;kmcnt1<=km_reg(3 downto 0);kmcnt2<=km_reg(7 downto 4);kmcnt3<=km_reg(11

10、 downto 8);end process;end behavior;3. 計(jì)時(shí)模塊：在汽車啟動(dòng)時(shí)，當(dāng)遇到顧客等人時(shí)，出租車采用計(jì)時(shí)收費(fèi)的方式。通過對(duì)速度信號(hào)sp的判斷決定是否開始記錄時(shí)間。當(dāng)stop=1時(shí)，不計(jì)費(fèi)，當(dāng)stop=0，sp=0時(shí)，開始按時(shí)間計(jì)費(fèi)，當(dāng)時(shí)間達(dá)到足夠長(zhǎng)時(shí)則產(chǎn)生Timecount脈沖，并重新計(jì)時(shí)。一個(gè)Timecount脈沖相當(dāng)于等待的時(shí)間達(dá)到了時(shí)間計(jì)費(fèi)的長(zhǎng)度。使用1kHz的系統(tǒng)時(shí)鐘，計(jì)算20s計(jì)數(shù)值為20000。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity

11、Taxi_part3 is port(clk,reset,start,stop:in std_logic; sp:in std_logic_vector(2 downto 0); timecount:out std_logic);end Taxi_part3;architecture behavior of Taxi_part3 isbegin process(reset,clk,sp,stop,start) type state_type is(t0,t1,t2); variable t_state:state_type; variable waittime: integer range 0

12、 to 1000; begin if(reset='1') then t_state:=t0; elsif(clk'event and clk='1')then case t_state is when t0 => waittime:=0;timecount<='0' if(start='1') then t_state:=t1; else t_state:=t0; end if; when t1 => if(sp="000") then t_state:=t2; else waitt

13、ime:=0;t_state:=t1; end if; when t2 => waittime:=waittime+1; timecount<='0' if(waittime=1000) then timecount<='1' -20s,即1000個(gè)clk，產(chǎn)生一個(gè)時(shí)間計(jì)費(fèi)脈沖 waittime:=0; elsif(stop='1') then t_state:=t0; elsif(sp="000") then t_state:=t2; else timecount<='0't_stat

14、e:=t1; end if; end case;end if;end process;end behavior;4.計(jì)費(fèi)模塊：計(jì)費(fèi)模塊由兩個(gè)線程組成。其中一個(gè)進(jìn)程根據(jù)條件對(duì)Enable和Price賦值：當(dāng)記錄的距離達(dá)到3千米后Enable變?yōu)?，開始進(jìn)行每千米收費(fèi)，當(dāng)總費(fèi)用大于40元后，則單價(jià)Price由原來(lái)的2元/千米變?yōu)?元/千米；第二個(gè)進(jìn)程在每個(gè)時(shí)鐘周期判斷Timecount和Clkcount的值。當(dāng)其為1時(shí)，則在總費(fèi)用上加上相應(yīng)的費(fèi)用。VHDL語(yǔ)言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.

15、all;entity Taxi_part4 is port(clk,reset,timecount,clkout:in std_logic; kmcnt2:in std_logic_vector(3 downto 0); kmcnt3:in std_logic_vector(3 downto 0); count1:out std_logic_vector(3 downto 0); count2:out std_logic_vector(3 downto 0); count3:out std_logic_vector(3 downto 0);end Taxi_part4;architecture

16、 behavior of Taxi_part4 issignal cash:std_logic_vector(11 downto 0);signal Price:std_logic_vector(3 downto 0);signal Enable: std_logic;begin process(cash,kmcnt2) begin if(cash>="000001000000") then price<="0100" else Price<="0010" end if; if(kmcnt2>="00

17、11")or(kmcnt3>="0001") then Enable<='1' else Enable<='0' end if; end process;kmmoney2:process(reset,clkout,clk,Enable,Price,kmcnt2)variable reg2:std_logic_vector(11 downto 0);variable clkout_cnt:integer range 0 to 10;begin if(reset='1') then cash<=&

18、quot;000000000111" -起步費(fèi)用設(shè)為7元 elsif(clk'event and clk='1') then if(timecount='1') then -判斷是否需要時(shí)間計(jì)費(fèi)，每20s加一元 reg2:=cash; if(reg2(3 downto 0)+"0001">"1001") then reg2(7 downto 0):=reg2(7 downto 0)+"00000111" if(reg2(7 downto 4)>"1001"

19、;) then cash <=reg2+"000001100000" else cash<=reg2; end if; else cash<=reg2+"0001" end if;elsif(clkout='1' and Enable='1')then -里程計(jì)費(fèi) if(clkout_cnt=9) then clkout_cnt:=0; reg2:=cash; if("0000"&reg2(3 downto 0)+price(3 downto 0)>"00001

20、001") then reg2(7 downto 0):=reg2(7 downto 0)+"00000110"+price; if(reg2(7 downto 4)>"1001") then cash<=reg2+"000001100000" else cash<=reg2; end if; else cash<=reg2+price; end if; else clkout_cnt:=clkout_cnt+1; end if;end if;end if;end process;count1<

21、=cash(3 downto 0); -總費(fèi)用的個(gè)位count2<=cash(7 downto 4); -總費(fèi)用的十位count3<=cash(11 downto 8); -總費(fèi)用的百位end behavior;5. 顯示模塊：時(shí)間的顯示需要用到全部8個(gè)數(shù)碼管，由于實(shí)驗(yàn)板上的所有數(shù)碼管均對(duì)應(yīng)同一組7段碼，因此，需要采用動(dòng)態(tài)掃描的方式實(shí)現(xiàn)時(shí)間顯示。VHDL語(yǔ)言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity display isport(clk:in std_logic;

22、kmcount1:in std_logic_vector(3 downto 0); kmcount2:in std_logic_vector(3 downto 0); kmcount3:in std_logic_vector(3 downto 0); count1:in std_logic_vector(3 downto 0); count2:in std_logic_vector(3 downto 0); count3:in std_logic_vector(3 downto 0); clkout:out std_logic_vector(6 downto 0); sel:buffer st

23、d_logic_vector(2 downto 0);end display;architecture dtsm of display is signal key:std_logic_vector(3 downto 0); begin process(clk) variable dount:std_logic_vector(2 downto 0):="000" begin if rising_edge(clk) then if dount="111" then dount:="000" else dount:=dount+1; end

24、 if; end if; sel<=dount; end process; process(sel) begin case sel is when "000"=>key<=kmcount3(3 downto 0 ); when "001"=>key<=kmcount2(3 downto 0); when "011"=>key<=kmcount1(3 downto 0); when "010"=>key<="1011" when "101"=>key<=count3(3 downto 0); when "110"=>key<=count2(3 downto 0); when "111"=>key<=count1(3 downto 0); when "100"=>key<="1010" when others=&g