EDA課程設(shè)計報告5位整數(shù)乘法器設(shè)計

1、哈爾濱工業(yè)大學（威海）信息科學與工程學院EDA課程設(shè)計報告有符號5位整數(shù)乘法器設(shè)計與制作指導老師：學生班級：學生姓名：學生學號：目 錄1.課程設(shè)計的性質(zhì)、目的和任務(wù)32.題目要求33.設(shè)計步驟43.1整體原理框圖：43.2乘法器整體電路原理圖：43.3輸入模塊：43.4運算模塊：53.5顯示控制模塊：83.6顯示模塊：94.整體仿真145. 調(diào)試中遇到的問題及解決的方法156.心得體會157.建議：151.課程設(shè)計的性質(zhì)、目的和任務(wù)創(chuàng)新精神和實踐能力二者之中，實踐能力是基礎(chǔ)和根本。這是由于創(chuàng)新基于實踐、源于實踐，實踐出真知，實踐檢驗真理。實踐活動是創(chuàng)新的源泉，也是人才成長的必由之路。通過課程設(shè)

2、計的鍛煉，要求學生掌握電路的一般設(shè)計方法，具備初步的獨立設(shè)計能力，提高綜合運用所學的理論知識獨立分析和解決問題的能力，培養(yǎng)學生的創(chuàng)新精神。2.題目要求設(shè)計一個兩個5位數(shù)相乘的乘法器。用發(fā)光二極管顯示輸入數(shù)值，用7段顯示器顯示十進制結(jié)果。乘數(shù)和被乘數(shù)分兩次輸入。在輸入乘數(shù)和被乘數(shù)時，要求顯示十進制輸入數(shù)據(jù)。輸入顯示和計算結(jié)果顯示，采用分時顯示方式進行，可參見計算器的顯示功能時鐘結(jié)果寄存累加器相乘邏輯移位寄存移位寄存被乘數(shù)乘數(shù)3.設(shè)計步驟3.1整體原理框圖：輸入模塊運算模塊顯示控制模塊顯示模塊3.2乘法器整體電路原理圖：3.3輸入模塊：模塊說明：由 CH,DH控制數(shù)據(jù)的輸入，由SHUJU端輸入數(shù)據(jù)

3、，當CH,DH為0，0時輸入被乘數(shù)，由輸出端A輸出，當按下“乘號鍵CH”即CH,DH為1，0時輸入乘數(shù)，由輸出端B輸出，當RESET為0時輸出端清零。VHDL程序代碼如下：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY shuru IS PORT(CH,DH,RESET,CLK:IN STD_LOGIC; shuju:IN STD_LOGIC_VECTOR(4 DOWNTO 0); A,B:OUT STD_LOGIC_V

4、ECTOR(4 DOWNTO 0);END shuru;ARCHITECTURE behave OF shuru IS BEGIN PROCESS(CH,DH,shuju,RESET,CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN IF RESET='1' THEN A<="00000" B<="00000" ELSE IF CH='0' AND DH='0' THEN A<=shuju; ELSIF CH='1'

5、AND DH='0' THEN B<=shuju; ELSE NULL; END IF; END IF; END IF; END PROCESS;END behave;3.4運算模塊：模塊說明：分別由AO和BO端接收被乘數(shù)和乘數(shù)，由CJ端輸出帶符號位的二進制乘積結(jié)果。此模塊由三個子模塊組成：“數(shù)字與符號分離子模塊”，“乘法運算子模塊”及“數(shù)字與符號重組子模塊”。VHDL程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY yunsuan ISPORT(A0:IN STD_LOGIC_VECTOR(4 DOWNTO 0

6、); B0:IN STD_LOGIC_VECTOR(4 DOWNTO 0); CJ:OUT STD_LOGIC_VECTOR(8 DOWNTO 0);END yunsuan;ARCHITECTURE BEHAVE OF yunsuan IS COMPONENT sffl PORT(A,B:IN STD_LOGIC_VECTOR(4 DOWNTO 0); FH:OUT STD_LOGIC; C,D:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT; COMPONENT MUL PORT(E,F:IN STD_LOGIC_VECTOR(3 DOWNTO

7、 0); Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT; COMPONENT sfcz PORT(Q:IN STD_LOGIC_VECTOR(7 DOWNTO 0); FHO:IN STD_LOGIC; CJO:OUT STD_LOGIC_VECTOR(8 DOWNTO 0); END COMPONENT; SIGNAL C1,D1:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL FHW:STD_LOGIC; SIGNAL OUT1:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN U1:sff

8、l PORT MAP(A=>A0,B=>B0,C=>C1,D=>D1,FH=>FHW); U2:MUL PORT MAP(E=>C1,F=>D1,Q=>OUT1); U3:sfcz PORT MAP(Q=>OUT1,FHO=>FHW,CJO=>CJ);END BEHAVE;數(shù)字與符號分離子模塊：程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sf

9、fl ISPORT(A,B:IN STD_LOGIC_VECTOR(4 DOWNTO 0); FH:OUT STD_LOGIC; C,D:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END sffl;ARCHITECTURE behave OF sffl ISBEGIN C<=A(3 DOWNTO 0); D<=B(3 DOWNTO 0); FH<=A(4) XOR B(4);END behave;乘法運算子模塊：程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARIT

10、H.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MUL IS PORT(E,F:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END MUL;ARCHITECTURE behave OF MUL IS SIGNAL Q1:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL Q2:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL Q3:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL Q4:STD

11、_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL FF0:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL FF1:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL FF2:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL FF3:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINFF0<=F(0)&F(0)&F(0)&F(0);FF1<=F(1)&F(1)&F(1)&F(1);FF2<=F(2)&F(2)&

12、;F(2)&F(2);FF3<=F(3)&F(3)&F(3)&F(3);Q1<=E AND FF0;Q2<=(E AND FF1)&"0"Q3<=(E AND FF2)&"00"Q4<=(E AND FF3)&"000"Q<=Q1+Q2+Q3+Q4;END behave;數(shù)字與符號重組子模塊：程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;

13、USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sfcz ISPORT(Q:IN STD_LOGIC_VECTOR(7 DOWNTO 0); FHO:IN STD_LOGIC; CJO:OUT STD_LOGIC_VECTOR(8 DOWNTO 0);END sfcz;ARCHITECTURE behave OF sfcz IS BEGIN CJO<=FHO & Q; END behave;3.5顯示控制模塊：模塊說明：當CH,DH為0，0時顯示被乘數(shù)，當按下“乘號鍵CH”即CH,DH為1，0時顯示乘數(shù)，當按下“等號鍵DH”即CH,DH為1，1時顯示

14、乘積。 VHDL程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xskz ISPORT(CH:IN STD_LOGIC; DH:IN STD_LOGIC; CLK:IN STD_LOGIC; AIN:IN STD_LOGIC_VECTOR(4 DOWNTO 0); BIN:IN STD_LOGIC_VECTOR(4 DOWNTO 0); CJIN:IN STD_LOGIC_VECTOR(8 DOWNTO 0); shuchu:OUT STD_LOGIC_VECTOR(8 DOWNTO 0);END xskz;ARCHITECTURE

15、 behave OF xskz ISBEGIN PROCESS(CH,DH,CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN IF(CH='0' AND DH='0')THEN shuchu<=AIN(4)&"0000"&AIN(3 DOWNTO 0); ELSIF(CH='1' AND DH='0')THEN shuchu<=BIN(4)&"0000"&BIN(3 DOWNTO 0); EL

16、SE shuchu<=CJIN; END IF; END IF; END PROCESS;END BEHAVE;3.6顯示模塊：模塊說明：由AIN端接收要顯示的二進制內(nèi)容，輸出轉(zhuǎn)換成十進制后各位對應(yīng)的數(shù)碼管顯示代碼。此模塊由六個子模塊組成：“輸出數(shù)字與符號分離子模塊”，“進制轉(zhuǎn)換子模塊”，“消零子模塊”，“符號位數(shù)碼管顯示子模塊”，“數(shù)字位數(shù)碼管顯示子模塊”和“滅點子模塊”。 此模塊組成結(jié)構(gòu)如下：輸出數(shù)字與符號分離子模塊：程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY outsffl ISPORT(AIN:IN STD_LOG

17、IC_VECTOR(8 DOWNTO 0); fhout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); shujuout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END outsffl;ARCHITECTURE behave OF outsffl ISSIGNAL B:STD_LOGIC;BEGINB<=AIN(8); PROCESS(B) BEGIN CASE B IS WHEN'0'=>fhout<="0000" WHEN'1'=>fhout<="00

18、01" WHEN OTHERS=>fhout<=NULL; END CASE; END PROCESS;shujuout<=AIN(7 DOWNTO 0);END behave;進制轉(zhuǎn)換子模塊：此模塊是用來對結(jié)果進行二進制到十進制轉(zhuǎn)換的，便于在顯示數(shù)碼管上顯示。定義3個變量A1,A2,A3，并賦初值為0，從高到低判斷輸入的數(shù)據(jù)A（二進制）的各個位，首先是百位，若大于一百，則A3加1，EJZ減去100；然后是十位，若大于十，則A2加1，EJZ減去10；最后是個位，直接將EJZ剩余值賦值給A1。依次將A1,A2,A3賦值給GOUT,SOUT,BOUT輸出。程序代碼如下：

19、module zhuanhuan(clk,a,bout,sout,gout);input clk;input7:0 a;output3:0 bout,sout,gout;reg3:0 A1,A2,A3,bout,sout,gout;reg7:0 aa;reg2:0 num;always(posedge clk)begincase(num) 0: begin aa7:0<=a; num<=1; A1<=0; A2<=0; A3<=0; end 1: begin if(aa>=100) begin A3<=A3+1; aa<=aa-100; end

20、else if(aa>=10)&&(aa<100) begin A2<=A2+1; aa<=aa-10; end else if(aa>=1)&&(aa<10) begin A1<=aa; aa<=0; end else begin num<=2; end end 2: begin gout<=A1; sout<=A2; bout<=A3; num<=0; end default:num<=0; endcase endendmodule消零子模塊：程序代碼如下：LIBRARY I

21、EEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xiaoling ISPORT(B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S:IN STD_LOGIC_VECTOR(3 DOWNTO 0); G:IN STD_LOGIC_VECTOR(3 DOWNTO 0); BOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); GOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END xiaoling;ARCHITECTUR

22、E behave OF xiaoling ISBEGIN PROCESS(B,S,G) BEGIN IF(B="0000")THEN IF(S="0000")THEN IF(G="0000")THEN BOUT<="1010" SOUT<="1010" GOUT<="1010" ELSE BOUT<="1010" SOUT<="1010" GOUT<=G; END IF; ELSE BOUT<=

23、"1010" SOUT<=S; GOUT<=G; END IF; ELSE BOUT<=B; SOUT<=S; GOUT<=G; END IF; END PROCESS;END behave; 符號位數(shù)碼管顯示子模塊：程序代碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY fh_led ISPORT(fh:IN STD_LOGIC_VECTOR(3 DOWNTO 0); fh_show:OUT STD_LOGIC_VECTOR(

24、6 DOWNTO 0);END fh_led;ARCHITECTURE behave OF fh_led ISBEGIN PROCESS(fh) BEGIN CASE fh IS WHEN"0000"=>fh_show<="1111111" WHEN"0001"=>fh_show<="0111111" WHEN OTHERS=>fh_show<="0000000" END CASE; END PROCESS;END behave;數(shù)字位數(shù)碼管顯示子模塊：程序代

25、碼如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY shuzi_led ISPORT(shuzi:IN STD_LOGIC_VECTOR(3 DOWNTO 0); shuzi_show:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END shuzi_led;ARCHITECTURE behave OF shuzi_led ISBEGIN PROCESS(shuzi) BEGIN CASE shuzi IS WHEN"0000"=>s

26、huzi_show<="1000000" WHEN"0001"=>shuzi_show<="1111001" WHEN"0010"=>shuzi_show<="0100100" WHEN"0011"=>shuzi_show<="0110000" WHEN"0100"=>shuzi_show<="0011001" WHEN"0101"=>shuzi_show<="0010010" WHEN"0110&q