定時器A寄存器

1、寄存器 縮寫Timer_A Control TAxCTLTimer_A Capture/Compare Control 0 TAxCCTL0Timer_A Counter TAxRTimer_A Capture/Compare 0 TAxCCR0Timer_A Interrupt Vector TAxIVTimer_A Expansion 0 TAxEX0Timer_A Control Register (TAxCTLUnusedTASSELIDMCUnusedTACLRTAIETAIFGTASSEL Bits 9-8 Timer_A clock source select00 TAxCLK0

2、1 ACLK10 SMCLK11 Inverted TAxCLKID Bits 7-6 Input divider. These bits along with the IDEX bits select the divider for the input clock00 /101 /210 /411 /8MC Bits 5-4 Mode control00 Stop mode: Timer is halted01 Up mode: Timer counts up to TAxCCR010 Continuous mode: Timer counts up to 0FFFFh11 Up/down

3、mode: Timer counts up to TAxCCR0 then down to 0000hTACLR Bit 2 Timer_A clearSetting this bit resets TAxR, the timer clock divider, and the count direction. The TACLR bit is automatically reset and is always read as zero.TAIE Bit 1 Timer_A interrupt enable0 Interrupt disabled1 Interrupt enabledTAIFG

4、Bit 0 Timer_A interrupt flag0 No interrupt pending1 Interrupt pendingTimer_A Counter Register (TAxR 計數(shù) 寄存器 ： 寫入初值 然后開始 自增/自減 到達一定值后 溢出 發(fā)出中斷Capture/Compare Control Register (TAxCCTL0CMCCISSCSSCCIUnusedCAPOUTMODCCIECCIOUTCOVCCIFGCM Bits 15-14 Capture mode00 No capture01 Capture on rising edge10 Captur

5、e on falling edge11 Capture on both rising and falling edgesCCIS Bits 13-12 Capture/compare input selectThese bits select the TAxCCRn input signal. See the device-specific data sheet for specific signal connections00 CCIxA01 CCIxB10 GND11 VCCSCS Bit 11 Synchronize capture source0 Asynchronous captur

6、e1 Synchronous captureSCCI Bit 10 Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read via this bit.CAP Bit 8 Capture mode0 Compare mode1 Capture modeOUTMOD Output mode000 OUT bit value001 Set010 Toggle/reset011 Set/reset100 Toggle101 Rese

7、t110 Toggle/set111 Reset/setCCIE0 Interrupt disabled1 Interrupt enabledCCICapture/compare input. The selected input signal can be read by this bit.OUT0 Output low1 Output highCOV0 No capture overflow occurred1 Capture overflow occurredCCIFG Capture/compare interrupt flag0 No interrupt pending1 Inter

8、rupt pendingTimer_A Interrupt Vector Register (TAxIV000000000000TAIV0TAIV Timer_A interrupt vector value00h No interrupt pending02h Capture/compare 1 TAxCCR1 CCIFG Highest04h Capture/compare 2 TAxCCR2 CCIFG06h Capture/compare 3 TAxCCR3 CCIFG08h Capture/compare 4 TAxCCR4 CCIFG0Ah Capture/compare 5 TAxCCR5 CCIFG0Ch Capture/compare 6 TAxCCR6 CCIFG0Eh Timer overflow TAxCTL TAIFG LowestTimer_A Expansion 0 Register (TAxEX0UnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedIDEXIDEX Input di