EDA中用VHDL語言編程的實驗

1、EDA課程中VHDL的分頻程序(1)將 32KHz分成1KHz 占空比百分之五十LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY fenpin ISPORT (CLK: IN STD_LOGIC;q: OUT STD_LOGIC);END fenpin;ARCHITECTURE arc OF fenpin ISsignal wire:std_logic;BEGIN PROCESS (clk) VARIABLE cnt: INTEGER RANGE 0 TO 31;BEGIN IF clk'EVENT AND clk='1'

2、THENIF cnt<16 THENcnt:=cnt+1;-if cnt=7 then wire<='0'end if; 可以通過這綠色字體修改占空比。ELSE cnt:=0;-q<='1'wire<=not wire;END IF; END IF;END PROCESS;q<=wire;END arc;（2）9進制計數(shù)器程序如下LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT9 ISPORT (CLK1,RST,E

3、N : IN STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);END CNT9;ARCHITECTURE behave OF CNT9 ISBEGIN PROCESS (CLK1,RST,EN) VARIABLE CQI : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN IF RST = '1' THEN CQI := (OTHERS =>'0'); ELSIF CLK1'EVENT AND CLK1='1' THEN IF EN ='1'

4、 THEN IF CQI < 8 THEN CQI := CQI +1; ELSE CQI := (OTHERS =>'0'); END IF; END IF; END IF; CQ <= CQI; END PROCESS; END behave;（3）譯碼器的程序編寫。USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECL7S IS PORT (D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(2 D

5、OWNTO 0); LED7S :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END DECL7S;ARCHITECTURE one OF DECL7S ISBEGIN B <= A; PROCESS(D)BEGINCASE D ISWHEN "0000" => LED7S <= "0111111"WHEN "0001" => LED7S <= "0000110"WHEN "0010" => LED7S <= "10110

6、11"WHEN "0011" => LED7S <= "1001111"WHEN "0100" => LED7S <= "1100110"WHEN "0101" => LED7S <= "1101101"WHEN "0110" => LED7S <= "1111101"WHEN "0111" => LED7S <= "0000111&qu

7、ot;WHEN "1000" => LED7S <= "1111111"WHEN "1001" => LED7S <= "1101111"WHEN OTHERS => NULL;END CASE;END PROCESS;END;將上述三個程序主合成一個通過將32KHz分成1KHz,在譯碼器上顯示數(shù)字0到9.的主合程序，需進行元件例化。例化程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY KON IS PORT(ain,bin,ci

8、n:IN STD_LOGIC; AN:IN STD_LOGIC_VECTOR(2 DOWNTO 0); BN:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); YOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END KON;ARCHITECTURE one OF KON IS COMPONENT fenpin PORT(CLK:IN STD_LOGIC; Q:OUT STD_LOGIC); END COMPONENT; COMPONENT CNT9 PORT(CLK1,RST,EN:IN STD_LOGIC; CQ:OUT STD_LOGIC_VE

9、CTOR(3 DOWNTO 0); END COMPONENT; COMPONENT DECL7S PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT;SIGNAL e:STD_LOGIC;SIGNAL F:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN u1:fenpin PORT MAP(CL

10、K=>ain,Q=>e); u2:CNT9 PORT MAP(CLK1=>e,RST=>bin, EN=>cin,CQ=>F); u3:DECL7S PORT MAP(D=>F,A=>AN,LED7S=>YOUT);END ARCHITECTURE one;具體操作過程如下： File>new>VHDL點擊OK即可，再將分頻程序粘貼即可，再運行 在新建工程選中New Project wizard.如下圖所示開始新建工程如下圖所示注意工程名一定要與實體名一致，如fenpin就與實體名一致。單擊Next即可彈出如下圖再單擊Next即可。按下圖選好相應的芯片 再單擊Next再單擊下圖Next再單擊Next第二個程序以及第三個程序都只需保存編譯即可，不許再將工