有限狀態(tài)機(jī)的設(shè)計(jì)

1、第8章 有限狀態(tài)機(jī)的設(shè)計(jì)Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真本章內(nèi)容本章內(nèi)容有限狀態(tài)機(jī)的類型有限狀態(tài)機(jī)的類型一段式、兩段式和三段式狀態(tài)機(jī)寫法一段式、兩段式和三段式狀態(tài)機(jī)寫法狀態(tài)編碼狀態(tài)編碼有限狀態(tài)機(jī)的類型有限狀態(tài)機(jī)的類型moore型，也稱為摩爾型型，也稱為摩爾型mealy型，也稱為米利型型，也稱為米利型 moore型紅綠燈型紅綠燈 狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖模型代碼模型代碼module trafficlight1(clock,reset,red,yellow,green); input clock,reset; /輸入時(shí)鐘和復(fù)位信號(hào)輸入時(shí)鐘和復(fù)位信號(hào)output red,yellow,green

2、; /輸出紅黃綠的驅(qū)動(dòng)信號(hào)輸出紅黃綠的驅(qū)動(dòng)信號(hào)reg red,yellow,green;reg 1:0 current_state,next_state; /保存當(dāng)前狀態(tài)和下一狀態(tài)保存當(dāng)前狀態(tài)和下一狀態(tài)parameter red_state=2b00, yellow_state=2b01, green_state=2b10, delay_r2y=4d8, delay_y2g=4d3, delay_g2r=4d11; /參數(shù)聲明參數(shù)聲明/第一段第一段always，用于把下一狀態(tài)賦值給當(dāng)前狀態(tài)，用于把下一狀態(tài)賦值給當(dāng)前狀態(tài)always (posedge clock or posedge reset

3、) begin if(reset) current_state=red_state; else current_state=next_state;end/第二段第二段always，用于根據(jù)當(dāng)前狀態(tài)判斷下一狀態(tài)，用于根據(jù)當(dāng)前狀態(tài)判斷下一狀態(tài)， 并產(chǎn)生輸出并產(chǎn)生輸出always (current_state)begin case(current_state) red_state:begin red=1; yellow=0; green=0; repeat (delay_r2y) (posedge clock); next_state=yellow_state; end完成狀態(tài)描述完成狀態(tài)描述yel

4、low_state:begin red=0; yellow=1; green=0; repeat (delay_y2g) (posedge clock); next_state=green_state; end green_state:begin red=0; yellow=0; green=1; repeat (delay_g2r) (posedge clock); next_state=red_state; end default:begin red=1; yellow=0; green=0; next_state=red_state; end endcaseendendmodule 測(cè)試

5、信號(hào)測(cè)試信號(hào)initial clock=0;always #10 clock=clock;initialbegin reset=1; #1 reset=0; /產(chǎn)生一個(gè)復(fù)位信號(hào)沿產(chǎn)生一個(gè)復(fù)位信號(hào)沿 #10000 reset=1; /主要工作時(shí)間主要工作時(shí)間 #20 $stop;end功能仿真功能仿真時(shí)序仿真時(shí)序仿真增加一個(gè)可變計(jì)數(shù)器增加一個(gè)可變計(jì)數(shù)器always (posedge clock or posedge reset)begin if(reset) light_count=0; else if (light_count=light_delay) /達(dá)到規(guī)定的計(jì)數(shù)值達(dá)到規(guī)定的計(jì)數(shù)值lig

6、ht_delay時(shí)置時(shí)置1 light_count=1; else light_count=light_count+1;endcase(current_state) red_state:begin red=1; yellow=0; green=0; light_delay=red_delay; if(light_count=light_delay) next_state=yellow_state; end yellow_state:begin red=0; yellow=1; green=0; light_delay=yellow_delay; if(light_count=light_del

7、ay) next_state=green_state; endgreen_state:begin red=0; yellow=0; green=1; light_delay=green_delay; /延遲時(shí)間被賦值為延遲時(shí)間被賦值為green時(shí)的延遲時(shí)的延遲 if(light_count=light_delay) /達(dá)到延遲時(shí)間變?yōu)橄乱粻顟B(tài)達(dá)到延遲時(shí)間變?yōu)橄乱粻顟B(tài) next_state=red_state; end mealy型紅綠燈型紅綠燈 狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖設(shè)計(jì)模塊設(shè)計(jì)模塊module trafficlight3(clock,reset,x,red,yellow,green);inpu

8、t clock,reset;input x; /多添加了一個(gè)輸入端多添加了一個(gè)輸入端xoutput red,yellow,green;reg red,yellow,green;reg 1:0 current_state,next_state;parameter red_state=2b00, yellow_state=2b01, green_state=2b10, delay_r2y=4d8, delay_y2g=4d3, delay_g2r=4d11;always (posedge clock or posedge reset) /原態(tài)和新態(tài)的轉(zhuǎn)換原態(tài)和新態(tài)的轉(zhuǎn)換begin if(reset

9、) current_state=red_state; else current_state=next_state;endalways (current_state or x)begin case(current_state) red_state:begin red=1; yellow=0; green=0; if(x=1) /紅燈時(shí)若紅燈時(shí)若x為為1，則把下一狀態(tài)指向黃燈，則把下一狀態(tài)指向黃燈 begin repeat (delay_r2y) (posedge clock); next_state=yellow_state; end end yellow_state:begin red=0;

10、yellow=1; green=0; repeat (delay_y2g) (posedge clock); next_state=green_state; end green_state:begin red=0; yellow=0; green=1; repeat (delay_g2r) (posedge clock); next_state=red_state; end default:begin red=1; yellow=0; green=0; next_state=red_state; end endcaseendendmodule仿真波形仿真波形一段式狀態(tài)機(jī)一段式狀態(tài)機(jī) 檢測(cè)輸入信

11、號(hào)檢測(cè)輸入信號(hào)0110 狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換表狀態(tài)轉(zhuǎn)換表聲明部分聲明部分module fsm_seq1(x,z,clk,reset);input x,clk,reset;output z;reg z;reg2:0state;parameter s0=d0,s1=d1,s2=d2,s3=d3,s4=d4; 一段一段alwaysalways(posedge clk or posedge reset) /僅有一段僅有一段always begin if(reset) /復(fù)位信號(hào)有效復(fù)位信號(hào)有效 begin state=s0; /回到初始狀態(tài)回到初始狀態(tài) z=0; /z輸出輸出0 endS0狀態(tài)

12、狀態(tài)S1狀態(tài)狀態(tài)else casex(state) s0: begin if(x=1) begin state=s0; z=0; end else begin state=s1; z=0; end end s1: begin if(x=0) begin state=s1; z=0; end else begin state=s2; z=0; end end S2狀態(tài)狀態(tài)S3狀態(tài)狀態(tài)s2: begin if(x=0) begin state=s1; z=0; end else begin state=s3; z=0; end end s3: begin if(x=0) begin state=s

13、4; z=1; end else begin state=s0; z=0; end end S4狀態(tài)狀態(tài)結(jié)束結(jié)束s4: begin if(x=0) begin state=s1; z=0; end else begin state=s2; z=0; end end default: state=s0; endcase endendmodule功能仿真波形功能仿真波形時(shí)序仿真波形時(shí)序仿真波形一段式特點(diǎn)一段式特點(diǎn)僅有一段僅有一段always結(jié)構(gòu)，里面包含了結(jié)構(gòu)，里面包含了狀態(tài)轉(zhuǎn)換、復(fù)位和輸出；狀態(tài)轉(zhuǎn)換、復(fù)位和輸出；always結(jié)構(gòu)的敏感列表是時(shí)鐘沿，結(jié)構(gòu)的敏感列表是時(shí)鐘沿，所以最后的輸出結(jié)構(gòu)是以寄

14、存器形式所以最后的輸出結(jié)構(gòu)是以寄存器形式輸出，即時(shí)序邏輯輸出的輸出，即時(shí)序邏輯輸出的兩段式狀態(tài)機(jī)兩段式狀態(tài)機(jī) 聲明部分聲明部分module fsm_seq2(x,z,clk,reset);input x,clk,reset;output z;reg z;reg2:0state,nstate; /state表示原態(tài)，表示原態(tài)，nstate表示新態(tài)表示新態(tài)parameter s0=d0,s1=d1,s2=d2,s3=d3,s4=d4;第一段第一段always第二段第二段alwaysalways (posedge clk or posedge reset)begin if(reset) state=

15、s0; else state=nstate;end always(state or x)begin casex(state) s0: begin if(x=1) begin nstate=s0; z=0; end else begin nstate=s1; z=0; end end s1s2s1: begin if(x=0) begin nstate=s1; z=0; end else begin nstate=s2; z=0; end end s2: begin if(x=0) begin nstate=s1; z=0; end else begin nstate=s3; z=0; end

16、end s3s4s3: begin if(x=0) begin nstate=s4; z=1; end else begin nstate=s0; z=0; end end s4: begin if(x=0) begin nstate=s1; z=0; end else begin nstate=s2; z=0; end end default: nstate=s0; endcaseend 仿真波形仿真波形fsm_seq1的輸出的輸出z發(fā)生在每個(gè)發(fā)生在每個(gè)clk上升沿的位置，上升沿的位置，fsm_seq2的輸出的輸出z發(fā)生在發(fā)生在x變化的位置變化的位置fsm_seq1的輸出維持一個(gè)周期，的輸出

17、維持一個(gè)周期，fsm_seq2的的輸出維持半個(gè)周期。輸出維持半個(gè)周期。最后的輸出采用組合邏輯電路最后的輸出采用組合邏輯電路 三段式狀態(tài)機(jī)三段式狀態(tài)機(jī) 除除always外無(wú)區(qū)別外無(wú)區(qū)別/第一段第一段always，完成原態(tài)到新態(tài)的轉(zhuǎn)換，完成原態(tài)到新態(tài)的轉(zhuǎn)換always (posedge clk or posedge reset)begin if(reset) state=s0; else state=nstate;end /第二段第二段always，指定新態(tài)的變化，指定新態(tài)的變化always(state or x)begin casex(state) s0: begin if(x=1) nstat

18、e=s0; else nstate=s1; end s1: begin if(x=0) nstate=s1; else nstate=s2; end s2: begin if(x=0) nstate=s1; else nstate=s3; end s3: begin if(x=0) nstate=s4; else nstate=s0; end s4: begin if(x=0) nstate=s1; else nstate=s2; end default: nstate=s0; endcaseend always(state or x) /第三段第三段always，指定不同狀態(tài)下的輸出，指定不

19、同狀態(tài)下的輸出begin casex(state) s0: z=0; s1: z=0; s2: z=0; s3: begin if(x=0) z=1; else z=0; end s4: z=0; default: z=0; endcaseend Mealy型的五種輸出敏感列表型的五種輸出敏感列表always(state or x) if(state=xxx and x=yyy)always(state)always(nstate)always(posedge clk) case(state)always(posedge clk) case(nstate) 時(shí)序圖時(shí)序圖Moore型的四種輸出敏

20、感列表型的四種輸出敏感列表always(state)always(nstate)always(posedge clk) case(state)always(posedge clk) case(nstate)時(shí)序圖時(shí)序圖狀態(tài)編碼的選擇狀態(tài)編碼的選擇 二進(jìn)制碼二進(jìn)制碼 parameter s0=3b000,s1=3b001,s2=3b010, s3=3b011,s4=3b100; 格雷碼格雷碼 parameter s0=3b000,s1=3b001,s2=3b011, s3=3b010,s4=3b110; 獨(dú)熱碼獨(dú)熱碼 parameter s0=5b00001,s1=5b00010,s2=5b00

21、100, s3=5b01000,s4=5b10000; 獨(dú)熱碼狀態(tài)機(jī)獨(dú)熱碼狀態(tài)機(jī) 狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖設(shè)計(jì)代碼設(shè)計(jì)代碼聲明部分聲明部分module ex8_1(clock,reset,x,y1,y2);input clock,reset;input x;output y1,y2;reg y1,y2;reg3:0 cstate,nstate;/本例中采用獨(dú)熱碼，當(dāng)然使用二進(jìn)制碼也可本例中采用獨(dú)熱碼，當(dāng)然使用二進(jìn)制碼也可parameter s0=4b0001,s1=4b0010, s2=4b0100,s3=4b1000;/第一段第一段always，原態(tài)變新態(tài)，原態(tài)變新態(tài)always (posedg

22、e clock or posedge reset)begin if(reset) cstate=s0; else cstate=nstate;end /第二段第二段always，狀態(tài)轉(zhuǎn)換，狀態(tài)轉(zhuǎn)換always (cstate or x)begin case(cstate) s0:begin if(x=0) nstate=s1; else nstate=s3; end s1:begin if(x=0) nstate=s2; else nstate=s0; end s2:begin if(x=0) nstate=s3; else nstate=s1; end s3:begin if(x=0) ns

23、tate=s0; else nstate=s2; end default:nstate=s0; endcaseend s2:begin if(x=0) y1=0; else y1=0; end s3:begin if(x=0) y1=0; else y1=1; end default:y1=0; endcaseend/第三段第三段always，產(chǎn)生輸出，產(chǎn)生輸出always (cstate or x)begin case(cstate) s0:begin if(x=0) y1=1; else y1=0; end s1:begin if(x=0) y1=0; else y1=0; end懶！簡(jiǎn)化

24、輸出簡(jiǎn)化輸出always (cstate or x) /在輸出比較簡(jiǎn)單時(shí)，也可以使用在輸出比較簡(jiǎn)單時(shí)，也可以使用if來(lái)確定輸出值來(lái)確定輸出值begin if(cstate=s0 & x=0) y2=1; else if(cstate=s3 & x=1) y2=1; else y2=0;end進(jìn)一步精簡(jiǎn)進(jìn)一步精簡(jiǎn)always (cstate or x) begin if(cstate=s0 & x=0) | (cstate=s3 & x=1) y2=1; else y2=0;end功能仿真波形功能仿真波形時(shí)序仿真波形時(shí)序仿真波形格雷碼狀態(tài)機(jī)格雷碼狀態(tài)機(jī) 狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖聲明部分聲明部分module ex8_2(clock,reset,a,z1,z2,z3,z4);input clock,reset;i