數(shù)字邏輯原理與實(shí)踐3-2

1、1 1REVIEW OF LAST CLASS 2 2VDD = +5.0VVOUTVINTpTnVCCAZCMOS inverter常閉常閉常開常開常閉常開inP P 溝道溝道NN溝道溝道3 3VCCAZVDD = +5.0VZABQ4Q1Q3CMOS 2-input NAND gateCMOS 2-input NAND gateQ2CMOS inverter4 43.4 Electrical Behavior of CMOS 3.4 Electrical Behavior of CMOS CircuitsCircuits (CMOS(CMOS電路的電氣特性電路的電氣特性) )Logic v

2、oltage levels. ( 邏輯電壓電平邏輯電壓電平)DC noise margins(直流噪聲容限直流噪聲容限)Fanout.(扇出扇出)Speed, Power consumption(速度、功耗速度、功耗)Noise, Electrostatic discharge(噪聲、靜電放電噪聲、靜電放電)Open-drain outputs. Three-state outputs (漏極開路輸出、三態(tài)輸出漏極開路輸出、三態(tài)輸出)5 53.5.1 Logic Levels and Noise Margins 邏輯電平和噪聲容限邏輯電平和噪聲容限VDD = +5.0VVOUTVINTpTn0

3、 1 016 6CMOS邏輯系列（邏輯系列（HC）電平規(guī)格）電平規(guī)格高態(tài)高態(tài)不正常狀態(tài)不正常狀態(tài)低態(tài)低態(tài)VOLmaxVILmaxVIHminVOHminVCC0.1V地地0.1V0.7VCC0.3VCC典型值：VCC=5V+10%, Figure 3-26Figure 3-26 Logic levels andnoise margins for the HC-series CMOS logic family. vcc07 7直流噪聲容限直流噪聲容限（DC noise marginDC noise margin）多大的噪聲會(huì)使最壞輸出電壓被破壞得不可被輸入多大的噪聲會(huì)使最壞輸出電壓被破壞得不可被

4、輸入端識(shí)別端識(shí)別.高態(tài)高態(tài)不正常狀態(tài)不正常狀態(tài)低態(tài)低態(tài)VOLmax=0.1VVILmax=1.35VVIHmin=3.15VVOHmin=4.4V30%VCC the LOW-state DC noise margin is 1.25 V =1.35-0.1(V)The HIGH state DC noise margin. Is 1.25 V=4.4-3.15(V) .8 89 93.5.2 Circuit Behavior with Resistive Loads (帶電阻性負(fù)載的電路特性帶電阻性負(fù)載的電路特性)(P103)10103.5.2 Circuit Behavior with R

5、esistive 3.5.2 Circuit Behavior with Resistive Loads(Loads(帶電阻性負(fù)載的電路特性帶電阻性負(fù)載的電路特性)(P103)(P103)要求有一定的驅(qū)動(dòng)電流才能工作要求有一定的驅(qū)動(dòng)電流才能工作VCCAZVCCRThevRpRnVThev +VOUTVINaThvenin equivalent network11 11REMEMBERING THVENIN REMEMBERING THVENIN Any two-terminal circuit consisting of only voltage sources and resistors c

6、an be modeled by a Thvenin equivalent consisting of a single voltage source in series with a single resistor. The Thvenin voltage is the open-circuit voltage of the original circuit, and the Thvenin resistance is the Thvenin voltage divided by the short-circuit current of the original circuit.1212Ex

7、ample 1 (P104)Example 1 (P104)1313Resistive model for CMOS LOW outputResistive model for CMOS LOW outputwith resistive load.with resistive load.1414Resistive model for CMOS HIGH outputResistive model for CMOS HIGH outputwith resistive load.with resistive load.1515VOLmaxIOLmax輸出為低態(tài)時(shí)輸出為低態(tài)時(shí) VOUT 1M Rn電

8、阻性電阻性負(fù)載負(fù)載100 Sinking current吸收電流吸收電流1616VOHminIOHmax輸出為高態(tài)時(shí)輸出為高態(tài)時(shí) VOUT = VOHmin輸出端提供電流輸出端提供電流 sourcing current能提供的最大電流能提供的最大電流 IOHmax （拉電流）（拉電流）VCC = + 5.0VRpRn1M 電阻性電阻性負(fù)載負(fù)載200 Sourcing current 提供電流提供電流1717VOUT = 0VCC = + 5.0VRThevVThev +VIN = 1VCC = + 5.0VRThevVThev +VOUT = 1VIN = 0輸出為低態(tài)時(shí)，輸出為低態(tài)時(shí)，估計(jì)吸

9、收電流：估計(jì)吸收電流：ThevThevOUTRVI輸出為高態(tài)時(shí)，輸出為高態(tài)時(shí)，估計(jì)提供電流：估計(jì)提供電流：ThevThevCCOUTRVVI1818EXAMPLE 2 (P107)EXAMPLE 2 (P107)19193.5.3 Circuit Behavior with Nonideal Inputs (P108)20203.5.3 Circuit Behavior with Nonideal 3.5.3 Circuit Behavior with Nonideal InputsInputs非理想輸入時(shí)的電路特性非理想輸入時(shí)的電路特性VCC = + 5.0V400 2.5k VIN 1.5

10、VVOUT 4.31VVCC = + 5.0V4k 200 VIN 3.5VVOUT 0.24V輸出電壓變壞（有電阻性負(fù)載時(shí)更差）輸出電壓變壞（有電阻性負(fù)載時(shí)更差）更糟糕的是：更糟糕的是：Iwasted ， Pwasted 2121Example 3 (P110)Example 3 (P110)22223.5.4 Fanout(P111)23233.5.4 Fanout 3.5.4 Fanout （扇出（扇出）The fanout of a logic gate is the number of inputs that the gate can drive without exceeding

11、its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible output states, HIGH and LOW. 在不超出其最壞情況負(fù)載規(guī)格的條件下，在不超出其最壞情況負(fù)載規(guī)格的條件下， 一個(gè)邏輯門能驅(qū)動(dòng)的輸入端個(gè)數(shù)。一個(gè)邏輯門能驅(qū)動(dòng)的輸入端個(gè)數(shù)。扇出需考慮輸出高電平和低電平

12、兩種狀態(tài)扇出需考慮輸出高電平和低電平兩種狀態(tài) 總扇出總扇出minmin（高態(tài)扇出，低態(tài)扇出）高態(tài)扇出，低態(tài)扇出）直流扇出直流扇出 和和 交流扇出交流扇出2424EXAMPLE 3 (P111)EXAMPLE 3 (P111) IImax for an HC-series CMOS input in any state is 1 A .The LOW-state fanout for an HC-series output driving HC-series inputs is 20. IImax for an HC-series CMOS input in any state is 1 A .

13、The HIGH-state fanout for an HC-series output driving HC-series inputs is 20.2525EXAMPLE 4EXAMPLE 4CMOS(TTLoutput level)CMOSCMOS the fanout of an HC-series output driving HC-series inputs at TTLlevels is 4000.直流扇出直流扇出26263.5.5 Effects of Loading(3.5.5 Effects of Loading(負(fù)載效應(yīng)負(fù)載效應(yīng)) ) 輸出負(fù)載大于它的扇出能力時(shí)（輸出負(fù)

14、載大于它的扇出能力時(shí)（P111） In the LOW state, the output voltage (VOL) may increase beyond VOLmax.In the HIGH state, the output voltage (VOH) may fall below VOHmin.輸出電壓變差輸出電壓變差Propagation delay to the output may increase beyond specifications. Output rise and fall times may increase beyond their specifications

15、.傳輸延遲和轉(zhuǎn)換時(shí)間變長(zhǎng)傳輸延遲和轉(zhuǎn)換時(shí)間變長(zhǎng) The operating temperature of the device may increase, thereby reducing the reliability of the device and eventually causing device failure. 溫度可能升高，可靠性降低，器件失效溫度可能升高，可靠性降低，器件失效.27273.5.6 Unused Inputs(3.5.6 Unused Inputs(不用的不用的CMOSCMOS輸入端輸入端) )不用的不用的CMOS輸入端絕對(duì)不能懸空輸入端絕對(duì)不能懸空XZ1k +

16、5VXZ增加了驅(qū)動(dòng)信號(hào)的電容負(fù)增加了驅(qū)動(dòng)信號(hào)的電容負(fù)載，使操作變慢載，使操作變慢XZ1k1k 28283.6 CMOS Dynamic Electrical Behavior(P114)29293.6 CMOS Dynamic Electrical Behavior3.6 CMOS Dynamic Electrical Behavior CMOSCMOS動(dòng)態(tài)電氣特性動(dòng)態(tài)電氣特性考慮兩個(gè)方面：考慮兩個(gè)方面：速度速度功耗功耗轉(zhuǎn)換時(shí)間（轉(zhuǎn)換時(shí)間（transition time）傳播延遲（傳播延遲（propagation delay）靜態(tài)功耗（靜態(tài)功耗（static power dissipation

17、）動(dòng)態(tài)功耗（動(dòng)態(tài)功耗（dynamic power dissipation）30303.6 CMOS Dynamic Electrical 3.6 CMOS Dynamic Electrical BehaviorBehavior (CMOS(CMOS動(dòng)態(tài)電氣特性動(dòng)態(tài)電氣特性) ) CMOS器件的速度和功耗在很大程度器件的速度和功耗在很大程度上取決于器件及其負(fù)載的動(dòng)態(tài)特性。上取決于器件及其負(fù)載的動(dòng)態(tài)特性。速度取決于兩個(gè)特性：速度取決于兩個(gè)特性：transition time（轉(zhuǎn)換時(shí)間（轉(zhuǎn)換時(shí)間）propagation delay（傳播延遲（傳播延遲）邏輯電路的輸出從一種狀態(tài)變?yōu)榱硪环N狀態(tài)所需的時(shí)間

18、邏輯電路的輸出從一種狀態(tài)變?yōu)榱硪环N狀態(tài)所需的時(shí)間從輸入信號(hào)變化到產(chǎn)生輸出信號(hào)變化所需的時(shí)間從輸入信號(hào)變化到產(chǎn)生輸出信號(hào)變化所需的時(shí)間31313.6.1 Transition Time3.6.1 Transition Time ( (轉(zhuǎn)換時(shí)間轉(zhuǎn)換時(shí)間) ) rise time(上升時(shí)間上升時(shí)間) ) t tr r fall time(下降時(shí)間下降時(shí)間) ) t tf f the “on” transistor resistance(晶體管的晶體管的“導(dǎo)通導(dǎo)通”電阻電阻)stray capacitance(寄生電容寄生電容)VCC = + 5.0VRLRpRnVL+CL電容兩端電壓不能突變電容兩端

19、電壓不能突變?cè)趯?shí)際電路中在實(shí)際電路中可用時(shí)間常數(shù)可用時(shí)間常數(shù)近似轉(zhuǎn)換時(shí)間近似轉(zhuǎn)換時(shí)間P115 Figure 3-363232Example 4 (P117)Example 4 (P117)estimates of 10 ns for fall time .3333EXAMPLE 5 (P117)EXAMPLE 5 (P117)estimates of 20 ns for rise time .34343.6.2 Propagation Delay(3.6.2 Propagation Delay(傳播延遲傳播延遲) )P83 圖圖3-42VINVOUTLHtPHLtP信號(hào)通路：一個(gè)特定輸入信號(hào)到邏輯元件的信號(hào)通路：一個(gè)特定輸入信號(hào)到邏輯元件的 特定輸出信號(hào)所經(jīng)歷的電氣通路。特定輸出信號(hào)所經(jīng)歷的電氣通路。35353.6.2 Propagation Delay(3.6.2 Propagation Delay(傳播延遲傳播延遲