用verilog HDL設(shè)計(jì)的位頻率計(jì)

1、簡單4位數(shù)字頻率計(jì)設(shè)計(jì)一、 設(shè)計(jì)要求（1）、利用Verilog HDL語言行為描述方法，設(shè)計(jì)一個(gè)簡單的4位數(shù)字頻率計(jì)；（2）、要求輸入標(biāo)準(zhǔn)時(shí)鐘信號(hào)頻率為1MHz，系統(tǒng)可計(jì)數(shù)頻率范圍為1Hz9999Hz；（3）、系統(tǒng)具有復(fù)位信號(hào)，且當(dāng)計(jì)數(shù)頻率發(fā)生溢出時(shí)能夠給出指示信號(hào)，計(jì)數(shù)的頻率通過4個(gè)共陰數(shù)碼管進(jìn)行顯示（動(dòng)態(tài)掃描顯示）。二、 系統(tǒng)結(jié)構(gòu)框圖根據(jù)設(shè)計(jì)要求，輸入系統(tǒng)的標(biāo)準(zhǔn)時(shí)鐘信號(hào)要先經(jīng)過分頻后得到一個(gè)周期為2s占空比50%的信號(hào)，用來對(duì)輸入信號(hào)采樣，得到采樣信號(hào)GATED_CLK；為了能夠控制計(jì)數(shù)模塊對(duì)采樣的信號(hào)進(jìn)行正常計(jì)數(shù)及保存計(jì)數(shù)后的頻率，這要求，要在計(jì)數(shù)器剛好完成計(jì)數(shù)后立即將數(shù)據(jù)輸出給顯示部分

2、進(jìn)行顯示，并且要為下次計(jì)數(shù)做好準(zhǔn)備，因此數(shù)據(jù)信號(hào)處理部分還要有產(chǎn)生控制計(jì)數(shù)器的兩個(gè)信號(hào)LOAD和COUNTER_CLR，LOAD信號(hào)控制計(jì)數(shù)完成后的數(shù)據(jù)及時(shí)輸出給顯示，COUNTER_CLR信號(hào)控制計(jì)數(shù)器清零；計(jì)數(shù)模塊就是完成對(duì)采樣信號(hào)的計(jì)數(shù)，并當(dāng)計(jì)數(shù)發(fā)生溢出時(shí)產(chǎn)生溢出信號(hào)FLOW_UP；顯示控制模塊要完成將計(jì)數(shù)模塊輸入的信號(hào)進(jìn)行譯碼顯示。三、 信號(hào)描述測試信號(hào)采樣原理：GATED_CLK、LOAD、COUNTER_CLR信號(hào)的關(guān)系：程序中用到的信號(hào)變量：FREQUENCY_COUNTROL_BLOCKFREQUENCY_COUNTER_BLOCKFREQUENCY_DISPLY_BLOCKG

3、ATED_CLK采樣信號(hào)COUT計(jì)數(shù)輸出信號(hào)DOUT輸出到數(shù)碼管LOAD控制計(jì)數(shù)器信號(hào)FLOW_UP計(jì)數(shù)溢出信號(hào)CDIN計(jì)數(shù)輸入信號(hào)COUNTER_CLR清零計(jì)數(shù)器信號(hào)CLOCK_IN計(jì)數(shù)器時(shí)鐘信號(hào)DCLK_IN標(biāo)準(zhǔn)時(shí)鐘信號(hào)CLK_IN標(biāo)準(zhǔn)時(shí)鐘信號(hào)LOAD控制計(jì)數(shù)輸出RESET復(fù)位信號(hào)SIGNAL_TEST測試信號(hào)COUNTER_CLR清零計(jì)數(shù)信號(hào)RESET復(fù)位信號(hào)RESET復(fù)位信號(hào)四、 Verilog程序各子模塊verilog程序：（1）信號(hào)處理模塊_verilog：module FREQUENCY_COUNTROL_BLOCK(GATED_CLK,LOAD,COUNTER_CLR,CLK_

4、IN,SIGNAL_TEST,RESET);output GATED_CLK;output LOAD;output COUNTER_CLR;input CLK_IN;input SIGNAL_TEST;input RESET;reg LOAD;reg COUNTER_CLR;reg DIVIDE_CLK;reg19:0 cn;reg A1,A2;/信號(hào)分頻：由CLK_IN得到分頻后的信號(hào)DIVIDE_CLK(0.5Hz)always (posedge CLK_IN) beginif(RESET)beginDIVIDE_CLK<=0;cn<=0;endelse if(cn=10000

5、00) begincn<=0;DIVIDE_CLK<=DIVIDE_CLK; endelsecn<=cn+1;end/頻率計(jì)數(shù)控制信號(hào)的產(chǎn)生：產(chǎn)生LOAD信號(hào)和COUNTER_CLR信號(hào) always (posedge SIGNAL_TEST)beginA1<=DIVIDE_CLK;endalways (posedge SIGNAL_TEST)beginA2=A1;endalways (A1 or A2)beginLOAD=A1&&(!A2);endalways (posedge SIGNAL_TEST)COUNTER_CLR=LOAD;/產(chǎn)生驅(qū)動(dòng)計(jì)數(shù)模

6、塊的信號(hào)GATED_CLK，也就是被計(jì)數(shù)模塊檢測的信號(hào) assign GATED_CLK=SIGNAL_TEST&DIVIDE_CLK;endmodule（2）、計(jì)數(shù)器模塊：module FREQUENCY_COUNTER_BLOCK(COUT,FLOW_UP,CLOCK_IN,RESET,LOAD,COUNTER_CLR);output15:0 COUT;output FLOW_UP;input CLOCK_IN;input LOAD;input COUNTER_CLR;input RESET;reg15:0 TEMP;reg FLOW_UP;parameter B_SIZE=16;

7、 /二進(jìn)制位寬，為便于移植，所有定義了成參數(shù)regB_SIZE+3:0 bcd; /轉(zhuǎn)換后的BCD碼的位數(shù)要比二進(jìn)制多4位regB_SIZE-1:0 binary;regB_SIZE-1:0 bin; regB_SIZE+3:0 result;/計(jì)數(shù)器完成計(jì)數(shù)得到二進(jìn)制表示的頻率數(shù)值always (CLOCK_IN or RESET or LOAD or COUNTER_CLR)beginif(RESET|COUNTER_CLR)beginTEMP<=0;FLOW_UP<=0;endelse if(LOAD)binary<=TEMP;else if(TEMP>9999)

8、beginFLOW_UP<=1;binary<=9999;endelseif(CLOCK_IN)TEMP<=TEMP+1;end/將二進(jìn)制表示（或十六進(jìn)制表示）的數(shù)轉(zhuǎn)換為BCD碼的形式，便于數(shù)碼管譯碼顯示always (binary or RESET)beginbin=binary;result=0;if(RESET)bcd<=0;elsebeginrepeat(B_SIZE-1)beginresult0=binB_SIZE-1;if(result3:0>4)result3:0=result3:0+4'd3;if(result7:4>4)result

9、7:4=result7:4+4'd3;if(result11:8>4)result11:8=result11:8+4'd3;if(result15:12>4)result15:12=result15:12+4'd3;if(result19:16>4)result19:16=result19:16+4'd3;result=result<<1;bin=bin<<1;endresult0=binB_SIZE-1;bcd<=result;endend assign COUT=bcd15:0;endmodule（3）信號(hào)顯示

10、處理：module FREQUENCY_DISPLY_BLOCK(DOUT,DCLK_IN,RESET,CDIN);output10:0 DOUT;input15:0 CDIN;input DCLK_IN;input RESET;reg10:0 DOUT;reg3:0 Temp1;reg1:0 cn;always (posedge DCLK_IN) /設(shè)置成動(dòng)態(tài)掃描beginif(RESET)cn<=0;elsebegincn<=cn+1;case(cn)2'b00: begin DOUT10:7<=4'b0001; Temp1<=CDIN3:0;end

11、2'b01: begin DOUT10:7<=4'b0010; Temp1<=CDIN7:4;end2'b10: begin DOUT10:7<=4'b0100; Temp1<=CDIN11:8;end2'b11: begin DOUT10:7<=4'b1000; Temp1<=CDIN15:12;endendcaseendendalways (Temp1) /譯碼顯示begincase(Temp1)4'b0000: DOUT6:0<=7'b0111111; /3fh=04'b00

12、01: DOUT6:0<=7'b0000110; /06h=14'b0010: DOUT6:0<=7'b1010110; /56h=24'b0011: DOUT6:0<=7'b1001111; /4fh=34'b0100: DOUT6:0<=7'b1100110; /66h=44'b0101: DOUT6:0<=7'b1101101; /6dh=54'b0110: DOUT6:0<=7'b1111101; /7dh=64'b0111: DOUT6:0<=7&

13、#39;b0000111; /07h=74'b1000: DOUT6:0<=7'b1111111; /7fh=84'b1001: DOUT6:0<=7'b1101111; /6fh=9default: DOUT6:0<=7'b0111111; /3fhendcaseendendmodule頂層verilog程序：module FREQUENCY_COUNTER_DISPLY_BLOCK(DOUT,FLOW_UP,CLK,TEST_CLK_IN,RESET);output10:0 DOUT;output FLOW_UP;input CLK

14、;input TEST_CLK_IN;input RESET;wire gated_clk,load,counter_clr;wire15:0 cout_cdin;FREQUENCY_COUNTROL_BLOCK u1(.GATED_CLK(gated_clk),.LOAD(load),.COUNTER_CLR(counter_clr),.CLK_IN(CLK),.SIGNAL_TEST(TEST_CLK_IN),.RESET(RESET); FREQUENCY_COUNTER_BLOCK u2(.COUT(cout_cdin),.FLOW_UP(FLOW_UP),.CLOCK_IN(gated_clk),.RESET(RESET),.LOAD(load),.COUNTER_CLR(counter_clr);FREQUENCY_DISPLY_BLOCK u3(.DOUT(DOUT),.DCLK_IN(CLK),.RESET(RESET),.CDIN(cout_cdin); endmodule五、 仿真結(jié)果分析仿真結(jié)果如圖所示，輸入標(biāo)準(zhǔn)時(shí)鐘頻率為1MHz，經(jīng)過分頻后變成頻率為0.5Hz的信號(hào)，將其與測試信號(hào)相與得到采樣信號(hào)GATED_CLK，同時(shí)利用測試信號(hào)和0.5Hz的分頻信號(hào)可以產(chǎn)生LOAD信號(hào)和COUNTER_CLR