m序列Simulink仿真實(shí)現(xiàn)

1、m序列Simulink仿真Verilog實(shí)現(xiàn)1.4階m序列生成器Simulink模型如下：其中，可以在Unit Delay屬性中設(shè)置初始值為1000，由于Unit Delay輸出為double，所以要將其轉(zhuǎn)為Boolean以便進(jìn)行模二加運(yùn)算，使用XOR實(shí)現(xiàn)。下面分別是最后一級(jí)和所有級(jí)的輸出波形，可以看出，與上面的是一致的。Verilog實(shí)現(xiàn)timescale 1ns / 1ps/ Company:/ Engineer:/ Create Date: 11:02:17 05/01/2012/ Design Name:/ Module Name: PNcode/ Project Name:/modu

2、le PNcode(clk,rst,PNstate,PNout);input clk;input rst;output PNstate;output PNout;/ PN code n = 4, f(x) = 1 + x + x4parameter order = 4;reg PNout = 0;reg order-1 : 0 PNstate = 0;always (posedge clk)if(rst = 1)beginPNout = 0;PNstate = 4b1000; / PN seed = b1000endelsebeginPNout = PNstate0;PNstate = PNs

3、tate3+PNstate0, PNstate3:1;endendmodule測(cè)試文件：timescale 1ns / 1ps/ Company:/ Engineer:/ Create Date: 14:37:43 05/01/2012/ Design Name: PNcode/ Module Name: E:/me/CAST/Project/FPGAcomm/PNcode/PNcode_tb.v/ Project Name: PNcode/module PNcode_tb;/ Inputsreg clk;reg rst;/ Outputswire 3:0 PNstate;wire PNout;/ Instantiate the Unit Under Test (UUT)PNcode uut (.clk(clk),.rst(rst),.PNstate(PNstate),.PNout(PNout);initial begin/ Initialize Inputsclk = 0;rst = 1;/ Wait 100 ns for global reset to finish#100;rst = 0;/ Add stimulus hereendalways beginforever #10 clk = !clk;endendmoduleclk使用一個(gè)單獨(dú)的alway