交通燈控制電路設(shè)計(jì)與仿真

1、交通燈控制電路設(shè)計(jì)和仿真一、實(shí)驗(yàn)?zāi)康?、了解交通燈的燃滅規(guī)律。2、了解交通燈控制器的工作原理。3、熟悉VHDL語(yǔ)言編程，了解實(shí)際設(shè)計(jì)中的優(yōu)化方案。二、實(shí)驗(yàn)原理交通燈的顯示有很多方式，如十字路口、 丁字路口等，而對(duì)于同一個(gè)路口又有很多不同的顯示要求，比如十字路口，車(chē)輛如果只要東西和南北方向通行就很簡(jiǎn)單，而如果車(chē)子可以左右轉(zhuǎn)彎的通行就比較復(fù)雜，本實(shí)驗(yàn)僅針對(duì)最簡(jiǎn)單的南北和東西直行的情況。要完成本實(shí)驗(yàn)，首先必須了解交通路燈的燃滅規(guī)律。本實(shí)驗(yàn)需要用到實(shí)驗(yàn)箱上交通燈模塊中的發(fā)光二極管， 即紅、黃、綠各三個(gè)。依人們的交通常規(guī)，“紅燈停，綠燈行，黃燈提醒”。其交通的燃滅規(guī)律為：初始態(tài)是兩個(gè)路口的紅燈全亮，之后

2、，東西路口的綠燈亮，南北路口的紅燈亮，東西方向通車(chē)，延時(shí)一段時(shí)間后，東西路口綠燈滅，黃燈開(kāi)始閃爍。閃爍若干次后，東 西路口紅燈亮，而同時(shí)南北路口的綠燈亮，南北方向開(kāi)始通車(chē)，延時(shí)一段時(shí)間后，南北路口的綠燈滅，黃燈開(kāi)始閃爍。閃爍若干次后，再切換到東西路口方向，重復(fù)上述過(guò)程。在實(shí)驗(yàn)中使用8個(gè)七段碼管中的任意兩個(gè)數(shù)碼管顯示時(shí)間。東西路和南北路的通車(chē)時(shí)間均設(shè)定為20s。數(shù)碼管的時(shí)間總是顯示為19、18、172、1、0、19、18。在顯示時(shí)間小于3秒的時(shí)候，通車(chē)方向的黃燈閃爍。三、實(shí)驗(yàn)內(nèi)容本實(shí)驗(yàn)要完成任務(wù)就是設(shè)計(jì)一個(gè)簡(jiǎn)單的交通燈控制器，交通燈顯示用實(shí)驗(yàn)箱的交通燈模塊和七段碼管中的任意兩個(gè)來(lái)顯示。系統(tǒng)時(shí)鐘選

3、擇時(shí)鐘模塊的1KHz時(shí)鐘，黃燈閃爍時(shí)鐘要求為 2Hz，七段碼管的時(shí)間顯示為1Hz脈沖，即每1s中遞減一次，在顯示時(shí)間小于 3秒的時(shí)候，通車(chē)方向的黃燈以2Hz的頻率閃爍。系統(tǒng)中用S1按鍵進(jìn)行復(fù)位。實(shí)驗(yàn)箱中用到的數(shù)字時(shí)鐘模塊、按鍵開(kāi)關(guān)、數(shù)碼管和FPGA的接口電路，以及數(shù)字時(shí)鐘源、按鍵開(kāi)關(guān)、數(shù)碼管和FPGA的管腳連接在以前的實(shí)驗(yàn)中都做了詳細(xì)說(shuō)明，這里不在贅述。交通燈模塊原理和LED燈模塊的電路原理一致，當(dāng)有高電平輸入時(shí)LED燈就會(huì)被點(diǎn)亮，反之不亮。只是LED發(fā)出的光有顏色之分。其和 FPGA的管腳連接如下表19-1所示：信號(hào)名稱(chēng)對(duì)應(yīng)FFGA管玄弭說(shuō)明RI山縱向紅魚(yú)交逍信號(hào)LED if¥1D

4、4緘向黃色交通信號(hào)LED燈G11)5縱向館色交通信號(hào)LEU燈R2圜討虹色交道信號(hào)LED燈Y2B4橫間黃色交逋信號(hào)LED燈G2F3陌向垛生交通信號(hào)LEU燈四、實(shí)驗(yàn)步驟1、打開(kāi)QUARTUSII軟件，新建一個(gè)工程。2、 建完工程之后，再新建一個(gè) VHDL File，打開(kāi)VHDL編輯器對(duì)話(huà)框。3、按照實(shí)驗(yàn)原理和自己的想法，在 VHDL 編輯窗口編寫(xiě) VHDL 程序，用戶(hù) 可參照光盤(pán)中提供的示例程序。4、編寫(xiě)完 VHDL 程序后，保存起來(lái)。(1) -jtdkz.vhdlibrary ieee;use ieee.std_logic_1164.all;entity jtdkz is port(clk,sm

5、,sb:in std_logic;mr,my0,mg0,br,by0,bg0:out std_logic);end entity jtdkz; architecture art of jtdkz is type state_type is(A,B,C,D); signal state:state_type;begincnt: process(clk) isvariable s:integer range 0 to 45; variable clr,en:bit;beginif(clk'event and clk='1')thenif clr='0'the

6、n s:=0;elsif en='0' then s:=s; else s:=s+1;end if; case state iswhen A=>mr<='0'my0<='0'mg0<='1'br<='1'by0<='0'bg0<='0'if(sb and sm)='1' thenif s=45 then state<= B;clr:='0'en:='0'else state<=A;c

7、lr:='1'en:='1'end if;elsif(sb and(not sm)='1'then state<=B;clr:='0'en:='0'else state<=A;clr:='1'en:='1'end if;when B=>mr<='0'my0<='1'mg0<='0'br<='1'by0<='0'bg0<='0'if s=

8、5 then state<=C;clr:='0'en:='0'else state<=B;clr:='1'en:='1'end if;when C=>mr<='1'my0<='0'mg0<='0'br<='0'by0<='0'bg0<='1'if(sb and sm)='1' thenif s=25 then state<= D;clr:='0'

9、en:='0'else state<=C;clr:='1'en:='1'end if;elsif sb='0' then state<=D;clr:='0'en:='0'else state<=C;clr:='1'en:='1'end if;whe n D=>mr<='1'myO<='O'mgO<='O'br<='O'byO<='1'b

10、gO<='O： if s=5 the n state<=A;clr:='O'e n:='O：else state<=D;clr:='1'e n:='1'end if;end case;end if;end process ent;end architecture art;ritejk'：""=4 elkmr-j SinnmyO-i sbmgObrinstSinnl4.lion rtode： Fiaiicti on.alMaslsr Time Bar14.0 rJJPartwz孰Intw

11、vat329.03rwSiaitEn*Ag40.9 hSSO ni120. ,0 bSISO p M200.0 ns20 p nr291 卩皿豈】141ILSJb或1_&LbrbjO*3?lkru-i-ngQ11Tnr1amiryOr口皋AT1 i1 1 丨rLlR僑l *1L11丨.丨l . 11(2) cskz.vhdlibrary ieee;use ieee.std _lo gic_1164.all;use ieee.std_logic_ un sig ned.all; en tity cskz isport(i na:i n std_logic;outa:out std_log

12、ic);end en tity cskz;architecture art of cskz isbeginprocess(i na) isbeginif in a='1' the n outa<='1'else outa<='0'end if;end process;end architecture art;i Cf kzL .jL k- ina outa ； JL !L .-!i j: inft?E .址IMG(3) cnt45s.vhdlibrary ieee;use ieee.std _lo gic_1164.all;use i

13、eee.std_logic_ un sig ned.all;en tity cn t45s isport(sb,clk,e n45:in std_logic;dout45m,dout45b:out std_logic_vector(7 dow nto 0);end en tity cn t45s;architecture art of cn t45s issig nal cn t6b:std_logic_vector(5 dow nto 0);beginprocess(sb,clk,e n45)isbeginif sb='0'then cnt6b<=cnt6b-cnt6b

14、-1;elsif(clk'event and clk='1')thenif en 45='1'then cnt6b<=c nt6b+1;elsif en45='0' then cnt6b<=cnt6b-cnt6b-1;end if;end if;end process;process(c nt6b)isbegincase cn t6b iswhen "000000"=>dout45m<="01000101"dout45b<="01010000" wh

15、en "000001"=>dout45m<="01000100"dout45b<="01001001" when "000010"=>dout45m<="01000011"dout45b<="01001000" whe n "000011"=>dout45m<="01000010"dout45b<="01000111" when "000100"

16、;=>dout45m<="01000001"dout45b<="01000110" when "000101"=>dout45m<="01000000"dout45b<="01000101" when "000110"=>dout45m<="00111001"dout45b<="01000100"when "000111"=>dout45m<=&quo

17、t;00111000"dout45b<="01000011"when "001000"=>dout45m<="00110111"dout45b<="01000010"when "001001"=>dout45m<="00110110"dout45b<="01000001"when "001010"=>dout45m<="00110101"dout45b&

18、lt;="01000000"when "001011"=>dout45m<="00110100"dout45b<="01101001"when "001100"=>dout45m<="00110011"dout45b<="00111000"when "001101"=>dout45m<="00110010"dout45b<="00110111"

19、when "001110"=>dout45m<="00110001"dout45b<="00110110"when "001111"=>dout45m<="00110000"dout45b<="00110101"when "010000"=>dout45m<="00101001"dout45b<="00110100"when "010001"=

20、>dout45m<="00101000"dout45b<="00110011"when "010010"=>dout45m<="00100111"dout45b<="00110010"when "010011"=>dout45m<="00100110"dout45b<="00110001"when "010100"=>dout45m<="00

21、100101"dout45b<="00110000"when "010101"=>dout45m<="00100100"dout45b<="00101001"when "010110"=>dout45m<="00100011"dout45b<="00101000"when "010111"=>dout45m<="00100010"dout45b<=

22、"00100111"when "011000"=>dout45m<="00100001"dout45b<="00100110"when "011001"=>dout45m<="00100000"dout45b<="00100101"when "011010"=>dout45m<="00011001"dout45b<="00100100"when

23、 "011011"=>dout45m<="00011000"dout45b<="00100011"when "011100"=>dout45m<="00010111"dout45b<="00100010"when "011101"=>dout45m<="00010110"dout45b<="00100001"when "011110"=>

24、dout45m<="00010101"dout45b<="00100000"when "011111"=>dout45m<="00010100"dout45b<="00011001"when "100000"=>dout45m<="00010011"dout45b<="00011000"when "100001"=>dout45m<="000100

25、10"dout45b<="00010111"when "100010"=>dout45m<="00010001"dout45b<="00010110"when "100011"=>dout45m<="00010000"dout45b<="00010101"when "100100"=>dout45m<="00001001"dout45b<=&quo

26、t;00010100"when "100101"=>dout45m<="00001000"dout45b<="00010011"when "100110"=>dout45m<="00000111"dout45b<="00010010"when "100111"=>dout45m<="00000110"dout45b<="00010001"when &qu

27、ot;101000"=>dout45m<="00000101"dout45b<="00010000"when "101001"=>dout45m<="00000100"dout45b<="00001001"when "101010"=>dout45m<="00000011"dout45b<="00001000"when "101011"=>dout

28、45m<="00000010"dout45b<="00000111"when "101100"=>dout45m<="00000001"dout45b<="00000110"when others=>dout45m<="00000000"dout45b<="00000000"end case;end process;end architecture art;§雪bdowt4<5mp,.0elk

29、do 葉僦7, Dcnt45sinrfMaster Time Bar:Ops1 KBns Irtervai:132.8 ns StditEnd(4) c nt05s.vhdlibrary ieee;use ieee.std _lo gic_1164.all;use ieee.std_logic_ un sig ned.all;en tity cn t05s isport(clk,e nO 5m,e nO 5b:i n std_logic; dout5:out std_logic_vector(7 dow nto 0); end en tity cn t05s;architecture art

30、of cn t05s issig nal cn t3b:std_logic_vector(2 dow nto 0); beginprocess(clk,e n0 5m,e n05b)isbeginif(clk'event and clk='1')thenif en 05m='1'then cnt3b<=cnt3b+1;elsif en 05b='1'then cnt3b<=cnt3b+1;elsif en 05b='0'then cnt3b<=cnt3b-c nt3b-1; end if;end if;e

31、nd process;process(c nt3b)isbegincase cn t3b iswhen "000"=>dout5<="00000101"when "001"=>dout5<="00000100"when "010"=>dout5<="00000011"when "011"=>dout5<="00000010"when "100"=>dout5<

32、;="00000001"when others=>dout5<="00000000"end case;end process;end architecture art;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity cn t25s isport(sb,sm,clk,e n25:i n std_logic;dout25m,dout25b:out std_logic_vector(7 dow nto 0);end en tity

33、 cn t25s;architecture art of cn t25s issig nal cn t5b:std_logic_vector(4 dow nto 0);beginprocess(sb,sm,clk,e n25)isbeginif sb='0'then cnt5b<=cnt5b-c nt5b-1;elsif sm='0' the n cn t5b<=c nt5b-c nt5b-1;elsif(clk'event and clk='1') thenif en 25='1' then cnt5b<

34、;=cnt5b+1;elsif en 25='0' then cnt5b<=cnt5b-c nt5b-1;end if;end if;end process;process(c nt5b)isbegincase cn t5b iswhen "00000"=>dout25b<="00100101"dout25m<="00110000"when "00001"=>dout25b<="00100100"dout25m<="001010

35、01"when "00010"=>dout25b<="00100011"dout25m<="00101000"when "00011"=>dout25b<="00100010"dout25m<="00100111"when "00100"=>dout25b<="00100001"dout25m<="00100110"whe n "00101&q

36、uot;=>dout25b<="00100000"dout25m<="00100101"when "00110"=>dout25b<="00011001"dout25m<="00100100"when "00111"=>dout25b<="00011000"dout25m<="00100011"when "01000"=>dout25b<="

37、00010111"dout25m<="00100010"when "01001"=>dout25b<="00010110"dout25m<="00100001"when "01010"=>dout25b<="00010101"dout25m<="00100000"when "01011"=>dout25b<="00010100"dout25m<=&

38、quot;00011001"when "01100"=>dout25b<="00010011"dout25m<="00011000"when "01101"=>dout25b<="00010010"dout25m<="00010111"when "01110"=>dout25b<="00010001"dout25m<="00010110"when &qu

39、ot;01111"=>dout25b<="00010000"dout25m<="00010101"when "10000"=>dout25b<="00001001"dout25m<="00010100"when "10001"=>dout25b<="00001000"dout25m<="00010011"when "10010"=>dout25b&

40、lt;="00000111"dout25m<="00010010"when "10011"=>dout25b<="00000110"dout25m<="00010001"when "10100"=>dout25b<="00000101"dout25m<="00010000"when "10101"=>dout25b<="00000100"dou

41、t25m<="00010001"when "10110"=>dout25b<="00000011"dout25m<="00001000"when "10111"=>dout25b<="00000010"dout25m<="00000111"when "11000"=>dout25b<="00000001"dout25m<="00000110&quo

42、t;when others=>dout25b<="00000000"dout25m<="00000000"end case;end process;end architecture art;(6) xskz.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xskz is port(en45,en25,en05m,en05b:in std_logic; ain45m,ain45b,ain25m,ain25b,ain05:i

43、n std_logic_vector(7 downto 0); doutm,doutb:out std_logic_vector(7 downto 0);end entity xskz;architecture art of xskz is begin process(en45,en25,en05m,en05b,ain45m,ain45b,ain25m,ain25b,ain05)is beginif en45='1'then doutm<=ain45m(7 downto 0);doutb<=ain45b(7 downto 0);elsif en05m='1&

44、#39;then doutm<=ain05(7 downto 0);doutb<=ain05(7 downto 0); elsif en25='1'then doutm<=ain25m(7 downto 0);doutb<=ain25b(7 downto 0); elsif en05b='1'then doutm<=ain05(7 downto 0);doutb<=ain05(7 downto 0); end if;end process;end architecture art;:xskz-fen46doutm7- 07決“

45、2巧doutb7.O1enOSmenOb:3in4flmR.0Jfjin43bp.jOJin25m.Dain25bp.JDainOSR .0；Inst"*ZQ14. D MJKone10國(guó) &a dJOS靜g aiuESbl£i LE13 as n25rtlz?0 43 M5bv田 a n45fiEl doutbEl doutrianOSlienJOSnen25en.45QocmoooigooojcjoOCOO120.0 RE40 ¥ nsnojQCiooogiTCDOoooi lXdoooidc)oi locXcooi iTiijjmoi 1 wXomi

46、 11 lJQcu amu 】gjX (CBmmoc55 BOKXnomflomojooc)j5)o o:)>joo j i5i)>KO 1(0001 i師 omaz)>M a55tOomooM燉 mo lcXb iifioooo l l Laxamcjo oc)>oo ioaoi 伽 oottc如cgmooc貶5xxn 氓gjjjil<)gjQL l l)colom)阪ci 肚腫01 顧pq 11 績(jī)R i i.炬iomocfflij 氓iMX Ltomo l ipooo l l Lfoooimc)nDoo i loioco i lcJjoi i i 咖】Qo5

47、oh OPOX(:j55)oujjo l lpjooq l lJQoouo loc)!>jjjo Lo QTTTjTiiuooo i tffl»oioaj5a5I55555i5Iooo pocccoM)5 i)j555noaMOi LffloaMixXcoMiaijnioom iQmoiax>5Ii7ji>jii56Ii5i7>jMCaoi(7) ymq.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity ymq isport(clk:in

48、 std_logic;ain41,ain42,ain43,ain44:in std_logic_vector(3 downto 0);del:out std_logic_vector(2 dow nto 0);dout7:out std_logic_vector(6 dow nto 0);end en tity ymq;architecture art of ymq issig nal ain4: std_logic_vector(3 downto 0);sig nal ent: std_logic_vector(2 dow nto 0);beginprocess(clk)beginif cl

49、k'eve nt and clk='1' the nif cnt="011" the ncnt<="000"elsecn t<=c nt+1;end if;end if;end process;process(c nt,a in 41,a in 42,a in 43,a in44)begincase ent iswhen "000" => ain4<=ain41; del<="111"when "001" => ain4<=ain

50、42; del<="110"when "010" => ain4<=ain43; del<="101"when "011" => ain4<=ain44; del<="100"when "100" => ain4<=ain41; del<="000"when "101" => ain4<=ain41; del<="000"when &quo

51、t;110" => ain4<=ain41; del<="000"when "111" => ain4<=ain41; del<="000" end case;end process;process(a in 4)isbegincase ain4 iswhen "0000"=>dout7<="0111111"when "0001"=>dout7<="0000110"when "

52、0010"=>dout7<="1011011"when "0011"=>dout7<="1001111"when "0100"=>dout7<="1100110"when "0101"=>dout7<="1101101"when "0110"=>dout7<="1111101"when "0111"=>dout7<=

53、"0000111"when "1000"=>dout7<="1111111"when "1001"=>dout7<="1101111"when others=>dout7<="0000000"end case;end process;end architecture art;：ymqelk姻2. JO】3in4i3.0dout7p5.0)L3in42 3.0in$t9Master Tine Bar;14.0 ns4 * Poirier;33

54、.8 naInterval;IS.Bns豺可卜zag m.40.9 »虹g mSO.f ni100 0 MNaive11. cR5JS(DOQD X 0)01 x (MID x O0IL X DIOO )(aioi x ouo )(am X looo )c譯5回f MJOl X 0DO x 1000 x 0011 x 0100 )(0111 x L10D ；(Jill X100 ai n4 3| mu aBO X L0000110 >0111 :(ioio X mo 1(0101 x_S ain44(0000 X 0)11 X Di oo Y ODDO om ；C noo 尊

55、lioi (mo Zelk1 1 1田d*l(ni x cdo X ooi X oio X on )(1W X 101 )(110 X ill )(ow X ooH dflutT(oiiuiiXioc(KOOXlOOOOOl Xioow 10X1000011 Xioooi 00X1000101X300Q110X1000111 XlOOIOOOXlOOl(8) jtkzq.vhdlibrary ieee;use ieee.std_logic_1164.all;en tity jtkzq isport(clk,sm,sb:in std_logic; mr,mg,my,by,br,bg:out st

56、d_logic;del1:out std_logic_vector(2 dow nto 0);dout:out std_logic_vector(6 dow nto 0);end en tity jtkzq;architecture art of jtkzq iscomp onent div_clk isport(clk : in std_logic;clk1:out std_logic);end comp onent div_clk;comp onent jtdkz isport(clk,sm,sb:in std_logic;mr,myO,mgO,br,byO,bgO:out std_log

57、ic);end comp onent jtdkz;comp onent cskz isport(in a:in std_logic;outa:out std_logic);end comp onent cskz;comp onent cn t45s isport(sb,clk,e n45:in std_logic;dout45m,dout45b:out std_logic_vector(7 dow nto 0); end comp onent cn t45s;comp onent cn t05s isport(clk,e nO 5m,e nO 5b:i n std_logic;dout5:ou

58、t std_logic_vector(7 dow nto 0);end comp onent cn t05s;comp onent cn t25s isport(sb,sm,clk,e n25:i n std_logic; dout25m,dout25b:out std_logic_vector(7 dow nto 0); end component cnt25s; component xskz is port(en45,en25,en05m,en05b:in std_logic;ain45m,ain45b,ain25m,ain25b,ain05:in std_logic_vector(7 d

59、ownto 0); doutm,doutb:out std_logic_vector(7 downto 0);end component xskz;component ymq is port(clk:in std_logic;ain41,ain42,ain43,ain44:in std_logic_vector(3 downto 0);del:out std_logic_vector(2 downto 0); dout7:out std_logic_vector(6 downto 0);end component ymq;signal clk11:std_logic;signal en1,en

60、2,en3,en4:std_logic;signal s45m,s45b,s05,s25m,s25b:std_logic_vector(7 downto 0);signal ym1,ym2,ym3,ym4:std_logic_vector(3 downto 0);beginu1:div_clk port map(clk=>clk,clk1=>clk11);u2:jtdkz port map(clk=>clk11,sm=>sm,sb=>sb,mr=>mr,my0=>en2,mg0=>en1,br=>br,by0=>en4,bg0=>

61、;en3)Ju3:cskz port map(ina=>en1,outa=>mg);u4:cskz port map(ina=>en2,outa=>my);u5:cskz port map(ina=>en3,outa=>bg);u6:cskz port map(ina=>en4,outa=>by);u7:cnt45s port map(clk=>clk11,sb=>sb,en45=>en1,dout45m=>s45m,dout45b=>s45b); u8:cnt05s port map(clk=>clk11,en05m=>en2,dout5=>s05,en05b=>en4);u9:cnt25s