quartus ii 常見的19個錯誤、28個警告

1、(一) Quartus警告解析 1.Found clock-sensitive change during active clock edge at time<time> on register "<name>"原因：vector source file中時鐘敏感信號（如：數(shù)據(jù)，允許端，清零，同步加載等）在時鐘的邊緣同時變化。而時鐘敏感信號是不能在時鐘邊沿變化的。其后果為導(dǎo)致結(jié)果不正確。措施：編輯vector source file 2.Verilog HDL assignment warning at <location&

2、gt;: truncated with size <number> to match size of target (<number>原因:在HDL設(shè)計中對目標(biāo)的位數(shù)進(jìn)行了設(shè)定,如:reg4:0 a;而默認(rèn)為32位,將位數(shù)裁定到合適的大小措施:如果結(jié)果正確,無須加以修正,如果不想看到這個警告,可以改變設(shè)定的位數(shù) 3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:經(jīng)過綜合器優(yōu)化后，輸出端口已經(jīng)不起作用了 4

3、.Following 9 pins have nothing, GND, or VCC driving datain port -changes to this connectivity may change fitting results原因:第9腳，空或接地或接上了電源措施:有時候定義了輸出端口，但輸出端直接賦0，便會被接地，賦1接電源。如果你的設(shè)計中這些端口就是這樣用的，那便可以不理會這些warning 5.Found pins functioning as undefined clocks and/or memory enables原因:是你作為時鐘的PIN沒有約束信息?？梢?/p>

4、對相應(yīng)的PIN做一下設(shè)定就行了。主要是指你的某些管腳在電路當(dāng)中起到了時鐘管腳的作用，比如flip-flop的clk管腳，而此管腳沒有時鐘約束，因此QuartusII把“clk”作為未定義的時鐘。措施:如果clk不是時鐘，可以加“not clock”的約束；如果是，可以在clock setting當(dāng)中加入；在某些對時鐘要求不很高的情況下，可以忽略此警告或在這里修改:Assignments>Timing analysis settings.>Individualclocks.>. 6.Timing characteristics of device EPM570T144

5、C5 are preliminary原因:因為MAXII 是比較新的元件在 QuartusII 中的時序并不是正式版的,要等Service Pack措施:只影響 Quartus 的 Waveform 7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled措施:將setting中的timing Requirements&Option->More Timing setting->setting->

6、;Enable Clock Latency中的on改成OFF  8.Warning: Found clock high time violation at 14.8 ns on register"|counter|lpm_counter:count1_rtl_0|dffs11"原因:違反了steup/hold時間，應(yīng)該是后仿真，看看波形設(shè)置是否和時鐘沿符合steup/hold時間措施:在中間加個寄存器可能可以解決問題 9.warning: circuit may not operate.detected 46 non-operational paths

7、clocked by clock clk44 with clock skew larger than data delay原因:時鐘抖動大于數(shù)據(jù)延時,當(dāng)時鐘很快，而if等類的層次過多就會出現(xiàn)這種問題,但這個問題多是在器件的最高頻率中才會出現(xiàn)措施：setting->timing Requirements&Options->Default required fmax 改小一些，如改到50MHZ 10.Design contains <number> input pin(s) that do not drive logic原因:輸入引腳沒有驅(qū)動邏輯(驅(qū)動其他

8、引腳）,所有的輸入引腳需要有輸入邏輯措施:如果這種情況是故意的,無須理會,如果非故意,輸入邏輯驅(qū)動. 11.Warning：Found clock high time violation at 8.9ns on node'TEST3.CLK'原因：FF中輸入的PLS的保持時間過短措施：在FF中設(shè)置較高的時鐘頻率 12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s)

9、 resulting in clock skew原因:如果你用的 CPLD 只有一組全局時鐘時，用全局時鐘分頻產(chǎn)生的另一個時鐘在布線中當(dāng)作信號處理，不能保證低的時鐘歪斜(SKEW)。會造成在這個時鐘上工作的時序電路不可靠，甚至每次布線產(chǎn)生的問題都不一樣。措施:如果用有兩組以上全局時鐘的 FPGA 芯片，可以把第二個全局時鐘作為另一個時鐘用，可以解決這個問題。 13.Critical Warning: Timing requirements were not met. See Report window for details.原因：時序要求未滿足，措施：雙擊Compilation R

10、eport->Time Analyzer->紅色部分（如clock setup:'clk'等）->左鍵單擊list path,查看fmax的SLACK REPORT再根據(jù)提示解決,有可能是程序的算法問題  14.Can't achieve minimum setup and hold requirement <text> along<number> path(s). See Report window for details.原因：時序分析發(fā)現(xiàn)一定數(shù)量的路徑違背了最小的建立和保持時間，與時鐘歪斜有關(guān),一般是由

11、于多時鐘引起的措施：利用Compilation Report->Time Analyzer->紅色部分（如clockhold:'clk'等），在slack中觀察是hold time為負(fù)值還是setup time 為負(fù)值，然后在：Assignment->Assignment Editor->To中增加時鐘名(fromnode finder)，Assignment Name中增加和多時鐘有關(guān)的Multicycle 和Multicycle Hold選項，如hold time為負(fù)，可使Multicycle hold的值>multicycle,如設(shè)為2和1。

12、 15: Can't analyze file - file E:/quartusii/*/*.v is missing原因：試圖編譯一個不存在的文件，該文件可能被改名或者刪除了措施：不管他，沒什么影響 16.Warning: Can't find signal in vector source file for input pin|whole|clk10m原因：因為你的波形仿真文件（ vector source file ）中并沒有把所有的輸入信號(input pin)加進(jìn)去，對于每一個輸入都需要有激勵源的  17.Warning: U

13、sing design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0原因：模塊不是在本項目生成的，而是直接copy了別的項目的原理圖和源程序而生成的，而不是用QUARTUS將文件添加進(jìn)本項目措施：無須理會，不影響使用 18.Timing characteristic

14、s of device <name> are preliminary原因：目前版本的QuartusII只對該器件提供初步的時序特征分析措施：如果堅持用目前的器件，無須理會該警告。關(guān)于進(jìn)一步的時序特征分析會在后續(xù)版本的Quartus得到完善。 19.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family原因：用analyze_latches_as_synchronous_elements

15、setting可以讓Quaruts II來分析同步鎖存，但目前的器件不支持這個特性措施：無須理會。時序分析可能將鎖存器分析成回路。但并不一定分析正確。其后果可能會導(dǎo)致顯示提醒用戶：改變設(shè)計來消除鎖 存器 20.Warning:Found xx output pins without output pin load capacitance assignment原因：沒有給輸出管教指定負(fù)載電容措施：該功能用于估算TCO和功耗，可以不理會，也可以在Assignment Editor中為相應(yīng)的輸出管腳指定負(fù)載電容，以消除警告 21.Warning: Found 6 node(s)

16、in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 原因：使用了行波時鐘或門控時鐘，把觸發(fā)器的輸出當(dāng)時鐘用就會報行波時鐘，將組合邏輯的輸出當(dāng)時鐘用就會報門控時鐘措施：不要把觸發(fā)器的輸出當(dāng)時鐘，不要將組合邏輯的輸出當(dāng)時鐘，如果本身如此設(shè)計，則無須理會該警告 22.Warning (10268): Verilog HDL information at lcd7106.v(63):Always

17、 Construct contains both blocking and non-blocking assignments原因： 一個always模塊中同時有阻塞和非阻塞的賦值 23  Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig2" in design. -沒有編寫testbench文件，或者沒有編輯輸入變量的值  testbench里是元件申明和映射24. Warning: Compil

18、er packed, optimized or synthesized away node "temp19". Ignored vector source file node.  -"temp19"被優(yōu)化掉了 25. Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk" Warning: No output dependent

19、on input pin "sign"  -輸出信號與輸入信號無關(guān)26. Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.-在源文件中找不到對應(yīng)的節(jié)點“over”。27：Warning: No exact pin location assignment(s) for 16 pins of 16 total pins定義的管腳沒有和外部的管腳連接.28：Warning: Ignored loca

20、tions or region assignments to the following nodesWarning: Node "78ledcom4" is assigned to location or region, but does not exist in design設(shè)計中沒提到"78ledcom4" ，而分配了管腳給它。說明：有時候運行了TCL腳本文件后需要修改，修改后有一些先前分配的管腳不需要了，如果沒有delete，則會出現(xiàn)此提示。解決辦法：assignments->pins，把不用的管腳刪除即可（TCL腳本文件里的多余管腳分配語句

21、最好也一起delete）。 (二) Quartus常見錯誤分析 1. Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"-兩者不能連接起來 2. Error: VHDL Interface Declaration error in clk_gen.vhd(29): int

22、erface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.  -信號類型設(shè)置不對，out當(dāng)作buffer來定義 3. Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"  -引用的例化元件未定義實體entity "clk_gen"  4.  E

23、rror: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component  -在相關(guān)的元件里沒有當(dāng)前文件所定義的類型 5. Error: VHDL error at tongbu.vhd(16): can't infer regist

24、er for signal "gate" because signal does not hold its outside clock edge  6. Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or" 7. Error: VHDL Association List error at period_counter.vhd(38): act

25、ual parameter assigned to formal parameter "alarm", but formal parameter is not declared-連接表錯誤，形參"alarm"賦值給實參，形參沒定義，可能是形參與實參的位置顛倒了，規(guī)定形參在實參之前。 8. Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors因為前一個錯誤而導(dǎo)致的錯誤 9. Error: VHDL error at p

26、eriod_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type"alarm"的定義類型與使用的類型不一致 10.Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks  -同一進(jìn)程中含

27、有兩個或多個if(edge)條件，（一個進(jìn)程中之能有一個時鐘沿） 11. Error: Can't resolve multiple constant drivers for net "datain_reg22" at shift_reg.vhd(19) 12. Error:  can't infer register for signal "num0" because signal does not hold its outside clock edge 13. Error: Can't

28、elaborate top-level user hierarchy 14. Error: Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32)     -有兩個以上賦值語句，不能確定“cs_in”的值，  15. Error: Can't access JTAG chain     無法找到下載鏈16. Error: Can't name logic scfifo0 of