verilog_實(shí)現(xiàn)DES密碼算法

1、verilog 實(shí)現(xiàn)DES密碼算法 收藏1課題概述（任務(wù)、目的、要求） 本課題的任務(wù)：利用verilog語(yǔ)言編寫(xiě)出DES密碼算法，并在Quartus ii上綜合，得到RTL級(jí)電路。 本課題的目的：1. 通過(guò)本課題熟練掌握verilog語(yǔ)言，并理解DES加密原 理； 2.熟悉Quartus ii 軟件使用方法。 本課題的要求： 通過(guò)本課題的研究，要獨(dú)立完成本實(shí)驗(yàn)，得到綜合結(jié)果。 2設(shè)計(jì)思路及采取的方案 思路：首先，要分析DES加密過(guò)程，深入理解DES加密原理；然后提取DES數(shù)據(jù)路徑。方案：把DES分解成多個(gè)模塊，分別用verilog語(yǔ)言編寫(xiě)，最后利用頂層模塊調(diào)用完成整個(gè)DES編碼。 4總結(jié)與體會(huì)

2、（包括：設(shè)計(jì)中遇到的問(wèn)題及解決過(guò)程；設(shè)計(jì)中產(chǎn)生的錯(cuò)誤及原因分析；設(shè)計(jì)體會(huì)和收獲） 在設(shè)計(jì)過(guò)程中，遇到不少錯(cuò)誤，例如：在verilog語(yǔ)法方面，各種數(shù)據(jù)類型的定義，always語(yǔ)句中，“=”左邊數(shù)據(jù)要定義成reg型，assign語(yǔ)句“=”左邊要定義成wire型等等，另外在設(shè)計(jì)過(guò)程中還要把握層次，頭腦中要有清晰的思路，例如DES編程，首先要分模塊，然后調(diào)用，就很有講究，DES分為三大模塊：IP置換，IP逆置換，輪運(yùn)算，以及密鑰生成模塊。我們就要層次分明去編寫(xiě)，最后調(diào)用，否則就會(huì)亂成一片，信號(hào)就會(huì)弄不清楚。還有在設(shè)計(jì)當(dāng)中要養(yǎng)成良好的習(xí)慣，便于修改和查看。 5主要參考文獻(xiàn) 應(yīng)用密碼學(xué) 電子工業(yè)出版社

3、胡向東 魏琴芳編著 密碼芯片設(shè)計(jì)技術(shù)基礎(chǔ) 電子技術(shù)學(xué)院 戴紫彬 孫萬(wàn)忠 陳韜 編著 IC設(shè)計(jì)基礎(chǔ) 西安電子科技大學(xué)出版社 任艷穎 王彬編著 6附錄（原程序代碼及注釋等） module DES_top(DES_in,DES_key,DES_out); input 1:64 DES_in; input 1:64 DES_key; output 1:64 DES_out; wire 1:64 IP_a; wire 1:32 L1_L,L1_R,L2_L,L2_R,L3_L,L3_R,L4_L,L4_R,L5_L,L5_R,L6_L,L6_R,L7_L,L7_R,L8_L,L8_R, L9_L,L9_

4、R,L10_L,L10_R,L11_L,L11_R,L12_L,L12_R,L13_L,L13_R,L14_L,L14_R,L15_L,L15_R,L16_L,L16_R; IP IP(.IPin(DES_in),.IPout(IP_a); wire 1:48 lkey1,lkey2,lkey3,lkey4,lkey5,lkey6,lkey7,lkey8,lkey9,lkey10,lkey11,lkey12,lkey13,lkey14,lkey15,lkey16; key_top key_top(.key_in(DES_key),.key1(lkey1),.key2(lkey2),.key3(

5、lkey3),.key4(lkey4),.key5(lkey5),.key6(lkey6),.key7(lkey7),.key8(lkey8),.key9(lkey9),.key10(lkey10),.key11(lkey11),.key12(lkey12),.key13(lkey13),.key14(lkey14), .key15(lkey15),.key16(lkey16); desL desL1(.inR(IP_a33:64),.inL(IP_a1:32),.KEY(lkey1),.outL(L1_L),.outR(L1_R),desL2(.inR(L1_L),.inL(L1_R),.K

6、EY(lkey2),.outL(L2_L),.outR(L2_R), desL3(.inR(L2_L),.inL(L2_R),.KEY(lkey3),.outL(L3_L),.outR(L3_R), desL4(.inR(L3_L),.inL(L3_R),.KEY(lkey4),.outL(L4_L),.outR(L4_R), desL5(.inR(L4_L),.inL(L4_R),.KEY(lkey5),.outL(L5_L),.outR(L5_R), desL6(.inR(L5_L),.inL(L5_R),.KEY(lkey6),.outL(L6_L),.outR(L6_R), desL7

7、(.inR(L6_L),.inL(L6_R),.KEY(lkey7),.outL(L7_L),.outR(L7_R), desL8(.inR(L7_L),.inL(L7_R),.KEY(lkey8),.outL(L8_L),.outR(L8_R), desL9(.inR(L8_L),.inL(L8_R),.KEY(lkey9),.outL(L9_L),.outR(L9_R), desL10(.inR(L9_L),.inL(L9_R),.KEY(lkey10),.outL(L10_L),.outR(L10_R), desL11(.inR(L10_L),.inL(L10_R),.KEY(lkey1

8、1),.outL(L11_L),.outR(L11_R), desL12(.inR(L11_L),.inL(L11_R),.KEY(lkey12),.outL(L12_L),.outR(L12_R), desL13(.inR(L12_L),.inL(L12_R),.KEY(lkey13),.outL(L13_L),.outR(L13_R), desL14(.inR(L13_L),.inL(L13_R),.KEY(lkey14),.outL(L14_L),.outR(L14_R), desL15(.inR(L14_L),.inL(L14_R),.KEY(lkey15),.outL(L15_L),

9、.outR(L15_R), desL16(.inR(L15_L),.inL(L15_R),.KEY(lkey16),.outL(L16_R),.outR(L16_L); IP_1 IP_1(.IP_1in(L16_L,L16_R),.IP_1out(DES_out); endmodule /密鑰生成模塊 modulekey_top(key_in,key1,key2,key3,key4,key5,key6,key7,key8,key9,key10,key11,key12,key13,key14,key15,key16); input 1:64 key_in; output 1:48 key1,k

10、ey2,key3,key4,key5,key6,key7,key8,key9,key10,key11,key12,key13,key14,key15,key16 ;wire 1:56 i,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16; key key(.in(key_in),.C0(i1:28),.D0(i29:56); left_shiftera left_shiftera1 (.in(i),.outM(k1), left_shiftera2 (.in(k1),.outM(k2),left_shiftera3 (.in(k8),

11、.outM(k9),left_shiftera4 (.in(k15),.outM(k16); left_shifterb left_shifterb1(.in(k2),.outN(k3),left_shifterb2(.in(k3),.outN(k4),left_shifterb3(.in(k4),.outN(k5),left_shifterb4(.in(k5),.outN(k6),left_shifterb5(.in(k6),.outN(k7),left_shifterb6(.in(k7),.outN(k8),left_shifterb7(.in(k9),.outN(k10),left_sh

12、ifterb8(.in(k10),.outN(k11),left_shifterb9(.in(k11),.outN(k12),left_shifterb10(.in(k12),.outN(k13),left_shifterb11(.in(k13),.outN(k14),left_shifterb12(.in(k14),.outN(k15); keys keys1(.in(k1),.out(key1), keys2(.in(k2),.out(key2), keys3(.in(k3),.out(key3), keys4(.in(k4),.out(key4), keys5(.in(k5),.out(

13、key5), keys6(.in(k6),.out(key6), keys7(.in(k7),.out(key7), keys8(.in(k8),.out(key8), key1s9(.in(k9),.out(key9), keys10(.in(k10),.out(key10), keys11(.in(k11),.out(key11), keys12(.in(k12),.out(key12), keys13(.in(k13),.out(key13), keys14(.in(k14),.out(key14), keys15(.in(k15),.out(key15), keys16(.in(k16

14、),.out(key16); endmodule module key (in,C0,D0); input 1:64 in; output 1:28 C0,D0; wire 1:28 C0,D0; assign C0=in57,in49,in41,in33,in25,in17,in9,in1,in58,in50,in42,in34,in26,in18,in10,in2,in59,in51,in43,in35,in27,in19,in11,in3,in60,in52,in44,in36; assign D0=in63,in55,in47,in39,in31,in33,in15,in7,in62,

15、in54,in46,in38,in30,in22,in14,in6,in61,in53,in45,in37,in29,in21,in13,in5,in28,in20,in12,in4;endmodule /移位寄存器 module left_shiftera(in,outM); input 1:56 in; output 1:56 outM; wire 1:56 outM; assign outM=in2:56,in1; endmodule module left_shifterb(in,outN); input 1:56 in; output 1:56 outN; wire 1:56 out

16、N; assign outN=in3:56,in1:2; endmodule /置換選擇 module keys(in,out); input 1:56 in; output 1:48 out; assign out = in14,in17,in11,in24,in1,in5,in3,in28,in15,in6,in21,in10,in23,in19,in12,in4,in26,in8,in16,in7,in27,in20,in13,in2,in41,in52,in31,in37,in47,in55,in30,in40,in51,in45,in33,in48,in44,in49,in39,in

17、56,in34,in53,in46,in42,in50,in36,in29,in32;endmodule /IP置換 module IP(IPin,IPout); input 1:64 IPin; output 1:64 IPout; wire 1:64 IPout; assign IPout = IPin58,IPin50,IPin42,IPin34,IPin26,IPin18,IPin10,IPin2, IPin60,IPin52,IPin44,IPin36,IPin28,IPin20,IPin12,IPin4,IPin62,IPin54,IPin46,IPin38,IPin30,IPin

18、22,IPin14,IPin6,IPin64,IPin56,IPin48,IPin40,IPin32,IPin24,IPin16,IPin8,IPin57,IPin49,IPin41,IPin33,IPin25,IPin17,IPin9,IPin1,IPin59,IPin51,IPin43,IPin35,IPin27,IPin19,IPin11,IPin3,IPin61,IPin53,IPin45,IPin37,IPin29,IPin21,IPin13,IPin5,IPin63,IPin55,IPin47,IPin39,IPin31,IPin23,IPin15,IPin7;endmodule

19、/IP逆置換 module IP_1(IP_1in,IP_1out); input 1:64 IP_1in; output 1:64 IP_1out; wire 1:64 IP_1out; assign IP_1out = IP_1in40,IP_1in8,IP_1in48,IP_1in16,IP_1in56,IP_1in24,IP_1in64,IP_1in32, IP_1in39,IP_1in7,IP_1in47,IP_1in15,IP_1in55,IP_1in23,IP_1in63,IP_1in31, IP_1in38,IP_1in6,IP_1in46,IP_1in14,IP_1in54,

20、IP_1in22,IP_1in62,IP_1in30, IP_1in37,IP_1in5,IP_1in45,IP_1in13,IP_1in53,IP_1in21,IP_1in61,IP_1in29, IP_1in36,IP_1in4,IP_1in44,IP_1in12,IP_1in52,IP_1in20,IP_1in60,IP_1in28, IP_1in35,IP_1in3,IP_1in43,IP_1in11,IP_1in51,IP_1in19,IP_1in59,IP_1in27, IP_1in34,IP_1in2,IP_1in42,IP_1in10,IP_1in50,IP_1in18,IP_

21、1in58,IP_1in26, IP_1in33,IP_1in1,IP_1in41,IP_1in9,IP_1in49,IP_1in17,IP_1in57,IP_1in25;endmodule /輪運(yùn)算 module desL(inR,inL,KEY,outL,outR); input 1:32 inL,inR; input 1:48 KEY; output 1:32 outL, outR; wire 1:32 t; wire 1:32 outL,outR; desf desf(.fin(inR),.K(KEY),.fout(t); assign outL = inR; assign outR

22、= inL; endmodule /F函數(shù) module desf(fin,K,fout); input/置換運(yùn)算P module P(in,out); input1:32in; wire 1:32 out; output1:32out; assign out=in16,in7,in20,in21,in29,in12,in28,in17,in1,in15,in23,in26,in5,in18,in31,in10,in2,in8,in24,in14,in32,in27,in3,in9,in19,in13,in30,in6,in22,in11,in4,in25; endmodule /擴(kuò)展E盒 m

23、odule E_box(in,out); input 1:32 in; output 1:48 out; wire 1:48 out; assign out =in32,in1,in2,in3,in4,in5,in4,in5,in6,in7,in8,in9,in8,in9,in10,in11,in12,in13,in12,in13,in14,in15,in16,in17,in16,in17,in18,in19,in20,in21,in20,in21,in22,in23,in24,in25,in24,in25,in26,in27,in28,in29,in28,in29,in30,in31,in3

24、2,in1,;endmodule /S盒 module S_box (in,out); input 1:48 in; output 1:32 out; S1 S1(in1:6,out1:4); S2 S2(in7:12,out5:8); S3 S3(in13:18,out9:12);S4 S4(in19:24,out13:16);S5 S5(in25:30,out17:20);S6 S6(in31:36,out21:24);S7 S7(in37:42,out25:28);S8 S8(in43:48,out29:32); endmodule module S1(in,out); input 1:

25、6 in; reg 1:4 out; output 1:4 out; always (in1:6) begin case(in1:6) 6b000000 : out1:4 =6b000001 : out1:4 =6b000010 : out1:4 = 4d14; 4d0; 4d4; 6b000011 : out1:4 = 4d15;6b000100 : out1:4 = 4d13;6b000101 : out1:4 = 4d7;6b000110 : out1:4 = 4d1;6b000111 : 6b001000 : 6b001001 : 6b001010 : 6b001011 : 6b001

26、100 : 6b001101 : 6b001110 : 6b001111 : 6b010000 : 6b010001 : 6b010010 : 6b010011 : 6b010100 : 6b010101 : 6b010110 : 6b010111 : 6b011000 : out1:4 = 4d4; out1:4 = 4d2; out1:4 = 4d14; out1:4 = 4d15; out1:4 = 4d2; out1:4 = 4d11; out1:4 = 4d13; out1:4 = 4d8; out1:4 = 4d1; out1:4 = 4d3; out1:4 = 4d10; out

27、1:4 = 4d10; out1:4 = 4d6; out1:4 = 4d6; out1:4 = 4d12; out1:4 = 4d12; out1:4 = 4d11; out1:4 = 4d5; 6b011001 : out1:4 = 4d9;6b011010 : out1:4 = 4d9;6b011011 : out1:4 = 4d5;6b011100 : out1:4 = 4d0;6b011101 : 6b011110 : 6b011111 : 6b100000 : 6b100001 : 6b100010 : 6b100011 : 6b100100 : 6b100101 : 6b1001

28、10 : 6b100111 : 6b101000 : 6b101001 : 6b101010 : 6b101011 : 6b101100 : 6b101101 : 6b101110 : out1:4 = 4d3; out1:4 = 4d7; out1:4 = 4d8; out1:4 = 4d4; out1:4 = 4d15; out1:4 = 4d1; out1:4 = 4d12; out1:4 = 4d14; out1:4 = 4d8; out1:4 = 4d8; out1:4 = 4d2; out1:4 = 4d13; out1:4 = 4d4; out1:4 = 4d6; out1:4

29、= 4d9; out1:4 = 4d2; out1:4 = 4d1; out1:4 = 4d11; 6b101111 : out1:4 = 4d7;6b110000 : out1:4 = 4d15;6b110001 : out1:4 = 4d5;6b110010 : out1:4 = 4d12;6b110011 : 6b110100 : 6b110101 : 6b110110 : 6b110111 : 6b111000 : 6b111001 : 6b111010 : 6b111011 : 6b111100 : 6b111101 : 6b111110 : 6b111111 : endcase e

30、nd endmodule module S2(in,out); out1:4 = 4d11; out1:4 = 4d9; out1:4 = 4d3; out1:4 = 4d7; out1:4 = 4d14; out1:4 = 4d3; out1:4 = 4d10; out1:4 = 4d10; out1:4 = 4d0; out1:4 = 4d5; out1:4 = 4d6; out1:4 = 4d0; out1:4 = 4d13; input 1:6 in;reg 1:4 out;output 1:4 out;always (in1:6)begin case(in1:6)6b000000 :

31、6b000001 :6b000010 :6b000011 :6b000100 :6b000101 :6b000110 :6b000111 :6b001000 :6b001001 :6b001010 :6b001011 :6b001100 :6b001101 :6b001110 :6b001111 : out1:4 = 4d15; out1:4 = 4d3; out1:4 = 4d1; out1:4 = 4d13; out1:4 = 4d8; out1:4 = 4d4; out1:4 = 4d14; out1:4 = 4d7; out1:4 = 4d6; out1:4 = 4d15; out1:

32、4 = 4d11; out1:4 = 4d2; out1:4 = 4d3; out1:4 = 4d8; out1:4 = 4d4; out1:4 = 4d14; 6b010000 : out1:4 = 4d9;6b010001 : out1:4 = 4d12;6b010010 : out1:4 = 4d7;6b010011 : out1:4 = 4d0;6b010100 : 6b010101 : 6b010110 : 6b010111 : 6b011000 : 6b011001 : 6b011010 : 6b011011 : 6b011100 : 6b011101 : 6b011110 : 6

33、b011111 : 6b100000 : 6b100001 : 6b100010 : 6b100011 : 6b100100 : 6b100101 : out1:4 = 4d2; out1:4 = 4d1; out1:4 = 4d13; out1:4 = 4d10; out1:4 = 4d12; out1:4 = 4d6; out1:4 = 4d0; out1:4 = 4d9; out1:4 = 4d5; out1:4 = 4d11; out1:4 = 4d10; out1:4 = 4d5; out1:4 = 4d0; out1:4 = 4d13; out1:4 = 4d14; out1:4

34、= 4d8; out1:4 = 4d7; out1:4 = 4d10; 6b100110 : out1:4 = 4d11;6b100111 : out1:4 = 4d1;6b101000 : out1:4 = 4d10;6b101001 : out1:4 = 4d3;6b101010 : 6b101011 : 6b101100 : 6b101101 : 6b101110 : 6b101111 : 6b110000 : 6b110001 : 6b110010 : 6b110011 : 6b110100 : 6b110101 : 6b110110 : 6b110111 : 6b111000 : 6

35、b111001 : 6b111010 : 6b111011 : out1:4 = 4d4; out1:4 = 4d15; out1:4 = 4d13; out1:4 = 4d4; out1:4 = 4d1; out1:4 = 4d2; out1:4 = 4d5; out1:4 = 4d11; out1:4 = 4d8; out1:4 = 4d6; out1:4 = 4d12; out1:4 = 4d7; out1:4 = 4d6; out1:4 = 4d12; out1:4 = 4d9; out1:4 = 4d0; out1:4 = 4d3; out1:4 = 4d5; 6b111100 :

36、out1:4 = 4d2;6b111101 : out1:4 = 4d14;6b111110 : out1:4 = 4d15;6b111111 : out1:4 = 4d9; endcase end endmodule module S3(in,out); input 1:6 in; reg 1:4 out; output 1:4 out; always (in1:6) begin case(in1:6) 6b000000 : 6b000001 : 6b000010 : 6b000011 : 6b000100 : 6b000101 : out1:4 = out1:4 = out1:4 = ou

37、t1:4 = out1:4 = out1:4 = 4d10; 4d13; 4d0; 4d7; 4d9; 4d0; 6b000110 : out1:4 = 4d14;6b000111 : out1:4 = 4d9;6b001000 : out1:4 = 4d6;6b001001 : out1:4 = 4d3;6b001010 : 6b001011 : 6b001100 : 6b001101 : 6b001110 : 6b001111 : 6b010000 : 6b010001 : 6b010010 : 6b010011 : 6b010100 : 6b010101 : 6b010110 : 6b0

38、10111 : 6b011000 : 6b011001 : 6b011010 : 6b011011 : out1:4 = 4d3; out1:4 = 4d4; out1:4 = 4d15; out1:4 = 4d6; out1:4 = 4d5; out1:4 = 4d10; out1:4 = 4d1; out1:4 = 4d2; out1:4 = 4d13; out1:4 = 4d8; out1:4 = 4d12; out1:4 = 4d5; out1:4 = 4d7; out1:4 = 4d14; out1:4 = 4d11; out1:4 = 4d12; out1:4 = 4d4; out

39、1:4 = 4d11; 6b011100 : out1:4 = 4d2;6b011101 : out1:4 = 4d15;6b011110 : out1:4 = 4d8;6b011111 : out1:4 = 4d1;6b100000 : 6b100001 : 6b100010 : 6b100011 : 6b100100 : 6b100101 : 6b100110 : 6b100111 : 6b101000 : 6b101001 : 6b101010 : 6b101011 : 6b101100 : 6b101101 : 6b101110 : 6b101111 : 6b110000 : 6b11

40、0001 : out1:4 = 4d13; out1:4 = 4d1; out1:4 = 4d6; out1:4 = 4d10; out1:4 = 4d4; out1:4 = 4d13; out1:4 = 4d9; out1:4 = 4d0; out1:4 = 4d8; out1:4 = 4d6; out1:4 = 4d15; out1:4 = 4d9; out1:4 = 4d3; out1:4 = 4d8; out1:4 = 4d0; out1:4 = 4d7; out1:4 = 4d11; out1:4 = 4d4; 6b110010 : out1:4 = 4d1;6b110011 : o

41、ut1:4 = 4d15;6b110100 : out1:4 = 4d2;6b110101 : out1:4 = 4d14;6b110110 : 6b110111 : 6b111000 : 6b111001 : 6b111010 : 6b111011 : 6b111100 : 6b111101 : 6b111110 : 6b111111 : endcase end endmodule module S4(in,out); input 1:6 in; reg 1:4 out; out1:4 = 4d12; out1:4 = 4d3; out1:4 = 4d5; out1:4 = 4d11; ou

42、t1:4 = 4d10; out1:4 = 4d5; out1:4 = 4d14; out1:4 = 4d2; out1:4 = 4d7; out1:4 = 4d12; output 1:4 out;always (in1:6)begin case(in1:6)6b000000 :6b000001 :6b000010 :6b000011 :6b000100 :6b000101 :6b000110 :6b000111 :6b001000 :6b001001 :6b001010 :6b001011 :6b001100 :6b001101 :6b001110 :6b001111 :6b010000

43、:6b010001 : out1:4 = 4d7; out1:4 = 4d13; out1:4 = 4d13; out1:4 = 4d8; out1:4 = 4d14; out1:4 = 4d11; out1:4 = 4d3; out1:4 = 4d5; out1:4 = 4d0; out1:4 = 4d6; out1:4 = 4d6; out1:4 = 4d15; out1:4 = 4d9; out1:4 = 4d0; out1:4 = 4d10; out1:4 = 4d3; out1:4 = 4d1; out1:4 = 4d4; 6b010010 : out1:4 = 4d2;6b0100

44、11 : out1:4 = 4d7;6b010100 : out1:4 = 4d8;6b010101 : out1:4 = 4d2;6b010110 : 6b010111 : 6b011000 : 6b011001 : 6b011010 : 6b011011 : 6b011100 : 6b011101 : 6b011110 : 6b011111 : 6b100000 : 6b100001 : 6b100010 : 6b100011 : 6b100100 : 6b100101 : 6b100110 : 6b100111 : out1:4 = 4d5; out1:4 = 4d12; out1:4

45、= 4d11; out1:4 = 4d1; out1:4 = 4d12; out1:4 = 4d10; out1:4 = 4d4; out1:4 = 4d14; out1:4 = 4d15; out1:4 = 4d9; out1:4 = 4d10; out1:4 = 4d3; out1:4 = 4d6; out1:4 = 4d15; out1:4 = 4d9; out1:4 = 4d0; out1:4 = 4d0; out1:4 = 4d6; 6b101000 : out1:4 = 4d12;6b101001 : out1:4 = 4d10;6b101010 : out1:4 = 4d11;6b101011 : out1:4 = 4d1;6b101100 : 6b101101 : 6b101110 : 6b101111 : 6b110000 : 6b110001 : 6b110010 : 6b110011 : 6b110100 : 6b110101 : 6b110110 : 6b110111 : 6b111000 : 6b111001 : 6b111010 : 6b111011 : 6b111100