基于VHDL的出租車計(jì)價(jià)器系統(tǒng)設(shè)計(jì)

1、基于VHDL的出租車計(jì)價(jià)器系統(tǒng)設(shè)計(jì)大家好！大家好！l本次我們?cè)O(shè)計(jì)的任務(wù)是出租車計(jì)程計(jì)價(jià)表，利用QuartusII進(jìn)行設(shè)計(jì)，對(duì)編好的VHDL程序進(jìn)行編譯、仿真、下載。實(shí)現(xiàn)一個(gè)出租車計(jì)程計(jì)價(jià)表，具有車型設(shè)置、起步里程設(shè)置、起步價(jià)設(shè)置、分時(shí)計(jì)價(jià)設(shè)置、里程顯示、計(jì)費(fèi)顯示、計(jì)時(shí)顯示、點(diǎn)陣數(shù)碼管顯示及漢字?jǐn)?shù)字鐘的報(bào)時(shí)及發(fā)光二極管花色顯示等功能。 本次設(shè)計(jì)主要分六個(gè)部分本次設(shè)計(jì)主要分六個(gè)部分第一部分：里程計(jì)價(jià)部分第一部分：里程計(jì)價(jià)部分第二部分：計(jì)時(shí)部分第二部分：計(jì)時(shí)部分第三部分：數(shù)碼管顯示部分第三部分：數(shù)碼管顯示部分第四部分：點(diǎn)陣顯示部分第四部分：點(diǎn)陣顯示部分第五部分：數(shù)字鐘的報(bào)時(shí)及發(fā)光二極第五部分：數(shù)字鐘

2、的報(bào)時(shí)及發(fā)光二極 管花色顯示部分管花色顯示部分第六部分：整體電路連接部分第六部分：整體電路連接部分第一部分第一部分 里程計(jì)價(jià)部分里程計(jì)價(jià)部分lDiv模塊作用l對(duì)芯片給的10MHZ的頻率進(jìn)行分頻，然后傳輸給計(jì)數(shù)器A,提供掃描頻率。第一部分第一部分 里程計(jì)價(jià)部分（續(xù)）里程計(jì)價(jià)部分（續(xù)）LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;use ieee.std_logic_arith.all; ENTITY div IS PORT (clk_sys: IN std_logic; clk: OUT std_

3、logic; clk_scan:out std_logic); END div;ARCHITECTURE a OF div IS signal q: std_logic_vector(23 DOWNTO 0); BEGIN PROCESS (clk_sys) BEGIN if(clk_sysevent and clk_sys = 0) then q = q + 1; end if; clk = q(4); clk_scan=q(2); - -注：為方便仿真，在此 clk = q(4); clk_scan=q(2);而在計(jì)程車的設(shè)計(jì)中用clk = q(18); clk_scan=q(9); en

4、d process;end a;第一部分第一部分 里程計(jì)價(jià)部分（續(xù)里程計(jì)價(jià)部分（續(xù))l計(jì)數(shù)器A作用l對(duì)車輪傳感器送來的車輪脈沖信號(hào)clk進(jìn)行計(jì)數(shù)分頻，車輪每轉(zhuǎn)一圈送出一個(gè)脈沖。車每行駛100m，計(jì)數(shù)器A輸出1個(gè)“100m脈沖信號(hào)oclk”，不同車型的車輪直徑不一樣，計(jì)數(shù)器A的分頻系數(shù)也不一樣。 第一部分第一部分 里程計(jì)價(jià)部分（續(xù)里程計(jì)價(jià)部分（續(xù))library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity cnt_A isport(rese

5、t,clk:in std_logic;start:in std_logic;cartype:in std_logic_vector(1 downto 0);oclk:out std_logic);end cnt_A;architecture behave of cnt_A issignal mode:std_logic_vector(5 downto 0);signal temp:std_logic_vector(5 downto 0);beginmode=000011 when cartype=00 else-注：為方便仿真，在此mode=000011 而在計(jì)程車的設(shè)計(jì)中用mode=“111

6、100 111010 when cartype=01 else111000 when cartype=10 else 110110 ;process (start,clk)beginif (reset=0) then temp0);elsif rising_edge (clk) thenif start=1 thenif temp= (mode) thentemp0);elsetemp=temp+1;end if;end if;end if;end process;oclk=1 when (temp=mode) else0;end behave;第一部分第一部分 里程計(jì)價(jià)部分（續(xù)里程計(jì)價(jià)部分（

7、續(xù))計(jì)數(shù)器B作用對(duì)輸入的100m脈沖oclk進(jìn)行累加在開始時(shí)輸出起步里程數(shù)據(jù)，而當(dāng)超出起步里程時(shí)自動(dòng)輸出實(shí)際公里數(shù)據(jù)給譯碼/動(dòng)態(tài)掃描模塊每計(jì)滿500m路程送出1個(gè)脈沖clkout給 計(jì)數(shù)器C。第一部分第一部分 里程計(jì)價(jià)部分（續(xù)里程計(jì)價(jià)部分（續(xù))LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;USE ieee.std_logic_arith.ALL;ENTITY cnt_B isport (reset,clkin: in std_logic;dip:in std_logic_vector (2 do

8、wnto 0);length:out std_logic_vector(12 downto 0);clkout:out std_logic);end cnt_B;ARCHITECTURE behave of cnt_B issignal licheng: std_logic_vector(6 downto 0);signal temp0: std_logic_vector(12 downto 0);signal temp1:std_logic_vector(3 downto 0); beginwith dip selectlicheng=conv_std_logic_vector(30,7)

9、when000,conv_std_logic_vector(40,7) when001,conv_std_logic_vector(50,7) when010,conv_std_logic_vector(60,7) when011,conv_std_logic_vector(70,7) when100,conv_std_logic_vector(80,7) when101,conv_std_logic_vector(90,7) when110,conv_std_logic_vector(100,7) when others;p1:process (clkin)Beginif (reset=0)

10、 then temp00);elsif rising_edge (clkin) thentemp0=temp0+1;end if;end process p1;p2:process (temp0,clkin)beginif (reset=0) then temp10);elsif rising_edge (clkin) thenif (temp0=licheng) thenif (temp1=conv_std_logic_vector (4,4) thentemp10);else temp1=temp1+1;end if;end if;end if;end process p2;clkout=

11、1 when (temp1=conv_std_logic_vector(4,4) else 0;length=000000& licheng when(temp0=licheng) else temp0;end behave;第一部分第一部分 里程計(jì)價(jià)部分（續(xù)里程計(jì)價(jià)部分（續(xù))計(jì)數(shù)器C作用實(shí)現(xiàn)步長可變（即單價(jià)可調(diào)）的累加計(jì)數(shù)分時(shí)計(jì)價(jià)控制端“hourin”輸入信號(hào)為0時(shí)，每500m計(jì)費(fèi)0.6元分時(shí)計(jì)價(jià)控制端“hourin”輸入信號(hào)為1時(shí)，每500m計(jì)費(fèi)0.9元。 第一部分第一部分 里程計(jì)價(jià)部分（續(xù)里程計(jì)價(jià)部分（續(xù))library ieee;use ieee.std_logic_1164.

12、all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;use ieee.std_logic_arith.all;entity cnt_c isport(hourin:in std_logic;reset:in std_logic;clkin:in std_logic;dip:in std_logic_vector(1 downto 0);money:out std_logic_vector(12 downto 0);end cnt_c;architecture behave of cnt_c issignal qibu:std

13、_logic_vector(12 downto 0);Signaltemp0:std_logic_vector(12 downto 0);beginwith dip selectqibu=conv_std_logic_vector (50,13) when 00,conv_std_logic_vector (60,13) when 01,conv_std_logic_vector (80,13) when 10,conv_std_logic_vector (100,13) when others;process (clkin)beginif(reset=0) then temp00);elsi

14、f rising_edge (clkin) thenif hourin=0 thentemp0=temp0+0110;else temp0=temp0+1001;end if; end if;end process;money=qibu+temp0;end behave;第二部分第二部分 計(jì)時(shí)部分計(jì)時(shí)部分lSecond模塊作用l輸入100m脈沖信號(hào)oclk作為“秒”輸入l調(diào)“分”端口setmin用于設(shè)定“分”l對(duì)秒輸入進(jìn)行60分頻，輸出enmin即“分”信號(hào)l輸出“秒”數(shù)據(jù)第二部分第二部分 計(jì)時(shí)部分（續(xù)）計(jì)時(shí)部分（續(xù)）LIBRARY ieee;use ieee.std_logic_1164.a

15、ll;use ieee.std_logic_unsigned.all;ENTITY second ISPORT(clk, reset,setmin : INSTD_LOGIC;enmin : OUT STD_LOGIC;daout: out std_logic_vector (6 downto 0);END entity second;ARCHITECTURE fun OF second ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);SIGNAL enmin_1,enmin_2:STD_LOGIC;BEGINdaout = count;enmin_

16、2=(not setmin and clk);enmin=(enmin_1 or enmin_2);process ( clk , reset , setmin) begin if (reset=0) thencount = 0000000;elsif (clk event and clk=1) thenif (count(3 downto 0)=1001) thenif (count 16#60#) thenif (count=1011001) thenenmin_1=1; count=0000000; ELSEcount=count+7; end if;else count=0000000

17、;end if;elsif (count 16#60#) then count = count+1;enmin_1=0 after 100 ns; else count=0000000;end if;end if;end process;END fun;第二部分第二部分 計(jì)時(shí)部分（續(xù)）計(jì)時(shí)部分（續(xù)）lMinute模塊作用l輸入enmin即“分”信號(hào)l調(diào)“時(shí)”端口sethour用于設(shè)定“時(shí)”l對(duì)分輸入進(jìn)行60分頻，輸出enhour即“時(shí)”信號(hào)l輸出“分”數(shù)據(jù)第二部分第二部分 計(jì)時(shí)部分（續(xù)）計(jì)時(shí)部分（續(xù)）LIBRARY ieee;use ieee.std_logic_1164.all;use ie

18、ee.std_logic_unsigned.all;ENTITY minute ISPORT(clk, clk1,reset,sethour : IN STD_LOGIC;enhour : OUT STD_LOGIC;daout: out std_logic_vector (6 downto 0);END entity minute;ARCHITECTURE fun OF minute ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);SIGNAL enhour_1,enhour_2:STD_LOGIC;BEGINdaout = count;enhou

19、r_2=(not sethour and clk1);enhour=(enhour_1 or enhour_2);process ( clk,reset,sethour) begin if (reset=0) thencount = 0000000;elsif (clk event and clk=1) thenif (count(3 downto 0)=1001) thenif (count 16#60#) thenif (count=1011001) thenenhour_1=1; count=0000000;ELSEcount=count+7; end if;else count=000

20、0000;end if;elsif(count 16#60#) then count = count + 1;enhour_1=0 after 100 ns;elsecount=0000000;end if;end if;第二部分第二部分 計(jì)時(shí)部分（續(xù)）計(jì)時(shí)部分（續(xù)）lhour模塊作用l輸入enhour即“時(shí)”信號(hào)l輸出“時(shí)”數(shù)據(jù)第二部分第二部分 計(jì)時(shí)部分（續(xù)）計(jì)時(shí)部分（續(xù)）LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY hour ISPORT(clk,reset: IN STD_L

21、OGIC;daout: out std_logic_vector (5 downto 0);END entity hour;ARCHITECTURE fun OF hour ISSIGNAL count: STD_LOGIC_VECTOR( 5 downto 0);BEGINdaout = count;process ( clk,reset) begin if (reset=0) thencount = 000000;elsif (clk event and clk=1) thenif (count(3 downto 0)=1001) thenif (count 16#23#) thencou

22、nt=count + 7; else count=000000;end if;elsif(count 16#23#) then count = count + 1;else count=000000;end if;end if;end process;END fun;end process;END fun;第三部分：數(shù)碼管顯示部分第三部分：數(shù)碼管顯示部分lBCD7模塊作用l輸入licheng信號(hào)和money信號(hào)轉(zhuǎn)換成相應(yīng)的七段數(shù)碼管數(shù)據(jù)信號(hào)和地址信號(hào)輸出第三部分：數(shù)碼管顯示部分（續(xù)）第三部分：數(shù)碼管顯示部分（續(xù)）library ieee;use ieee.std_logic_1164.all;

23、use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity BCD7 isport(money,licheng:in std_logic_vector(13 downto 0);clk_scan:in std_logic;SEG:out std_logic_vector(7 downto 0);DIP:out std_logic_vector(7 downto 0);end BCD7;architecture Arch of BCD7 issignal q:std_logic_vector(2 downto 0);si

24、gnal Dq,Db,Ds,Dg:std_logic_vector(3 downto 0);signallDq,lDb,lDs,lDg:std_logic_vector(3 downto 0);signal data: std_logic_vector(3 downto 0);signal sel:std_logic_vector(2 downto 0);beginP1:process(clk_scan)beginif(rising_edge(clk_scan) then q=q+1;end if;end process P1;P2:process(money)variable money_i

25、nt:integer range 0 to 9999;variable rb:integer range 0 to 1000;variable rs:integer range 0 to 100;beginmoney_int:=conv_integer(money);Dq=conv_std_logic_vector(money_int/1000,4);rb:=money_int rem 1000;Db=conv_std_logic_vector(rb/100,4);rs:=rb rem 100;Ds=conv_std_logic_vector(rs/10,4);Dg=conv_std_logi

26、c_vector(rs rem 10,4);end process P2;P2_2:process(licheng)variable licheng_int:integer range 0 to 9999;variable rb:integer range 0 to 1000;variable rs:integer range 0 to 100;beginlicheng_int:=conv_integer(licheng);lDq=conv_std_logic_vector(licheng_int/1000,4);rb:=licheng_int rem 1000;lDb=conv_std_lo

27、gic_vector(rb/100,4);rs:=rb rem 100;lDs=conv_std_logic_vector(rs/10,4);lDg=conv_std_logic_vector(rs rem 10,4);第三部分：數(shù)碼管顯示部分（續(xù)）第三部分：數(shù)碼管顯示部分（續(xù)）end process P2_2;P3:process(q)beginseldata= lDq; DIPdata= lDb; DIPdata= lDs; DIPdata= lDg; DIPdata= Dq; DIPdata= Db; DIPdata= Ds; DIPdata= Dg; DIPdata=0000;DIPS

28、EGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEG=00000000; end case;end if;end process P4;end Arch;第三部分：數(shù)碼管顯示部分（續(xù)）第三部分：數(shù)碼管顯示部分（續(xù)）c47模塊作用輸入second數(shù)據(jù)信號(hào)、minute數(shù)據(jù)信號(hào)和hour數(shù)據(jù)信號(hào)轉(zhuǎn)換成相應(yīng)的七段數(shù)碼管數(shù)據(jù)信號(hào)和地址信號(hào)輸出當(dāng)hour輸入為236時(shí)，hourout輸出為1，當(dāng)hour輸入為722時(shí)，hourout輸出為0。第三部分：數(shù)碼管顯示部分（續(xù)）第三部分：數(shù)碼管顯示部分（續(xù)）library ieee;

29、use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity c47 isport(sec,min:in std_logic_vector(6 downto 0);hour:in std_logic_vector(5 downto 0);clk_scan:in std_logic;SEG:out std_logic_vector(7 downto 0);DIP:out std_logic_vector(7 downto 0);hourout:out std_logi

30、c);end;architecture one of c47 issignal q:std_logic_vector(2 downto 0);signal dig1,dig2,dig3,dig4:std_logic_vector(3 downto 0);signaldig5,dig6,dig7,dig8:std_logic_vector(3 downto 0);signal data: std_logic_vector(3 downto 0);signal sel:std_logic_vector(2 downto 0);beginP1:process(clk_scan)beginif(ris

31、ing_edge(clk_scan) then q=q+1;end if;end process P1;P2:process(hour,min,sec) begin dig1=00& hour(5 downto 4);dig2=hour(3 downto 0);dig3=1111;dig4=0& min(6 downto 4);dig5=min(3 downto 0);dig6=1111;dig7=0& sec(6 downto 4);dig8=sec(3 downto 0);end process P2;P4:process(q)beginseldata= dig1;

32、DIPdata= dig2;DIPdata= dig3;DIPdata= dig4;DIPdata= dig5;DIPdata= dig6;DIPdata= dig7;DIPdata= dig8;DIPdata=1111;DIPSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEGSEG=00000000; end case;end if;end process P5;P6:process(hour)beginif ( hour=100011 or hour=000000 or hour=000001 or hour=00

33、0010 or hour=000011 or hour=000100 or hour=000101 or hour=000110 ) then hourout=1;else hourout=0;end if;end process P6; end one;第四部分第四部分 點(diǎn)陣顯示部分點(diǎn)陣顯示部分lDM_ROM點(diǎn)陣顯示模塊作用l將要顯示的漢字或字母按照“1”為點(diǎn)亮，“0”為熄滅的規(guī)則設(shè)計(jì)程序，并顯示在兩個(gè)8行8列的點(diǎn)陣顯示模塊上。第四部分第四部分 點(diǎn)陣顯示部分（續(xù)）點(diǎn)陣顯示部分（續(xù)）library ieee;use ieee.std_logic_1164.all;use ieee.std_lo

34、gic_unsigned.all;use ieee.std_logic_arith.all;entity DM_ROM isport(reset:in std_logic;clk_scan:in std_logic;DM_OUT:out std_logic_vector(7 downto 0);add_rom:out std_logic_vector(7 downto 0);end DM_ROM;architecture Arch of DM_ROM issignal q:std_logic_vector(4 downto 0);signal sel:std_logic_vector(4 do

35、wnto 0);beginadd_rom=000&sel;P1:process(clk_scan,reset)beginIF reset=0 THEN q0);ELSIF(rising_edge(clk_scan) then q=q+1;end if;end process P1;P3:process(q)beginselDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUTDM_OUT=00000001; end case;end process

36、P3;end Arch;第五部分：數(shù)字鐘的報(bào)時(shí)及發(fā)光二極第五部分：數(shù)字鐘的報(bào)時(shí)及發(fā)光二極 管花色顯示部分管花色顯示部分lalert_new模塊作用l00分鐘時(shí)從00秒59秒時(shí)段speaker按照1K赫茲的頻率報(bào)時(shí)l循環(huán)點(diǎn)亮發(fā)光二極管。第五部分：數(shù)字鐘的報(bào)時(shí)及發(fā)光二極管花色顯示部分（續(xù)）第五部分：數(shù)字鐘的報(bào)時(shí)及發(fā)光二極管花色顯示部分（續(xù)）LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY alert_new ISPORT(clk : INSTD_LOGIC;cp1khz:INSTD_LOG

37、IC;dain : IN STD_LOGIC_VECTOR(6 DOWNTO 0);speak: OUT STD_LOGIC;lamp :OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END alert_new ;ARCHITECTURE fun OF alert_new ISsignal count :lamper:process(clk)beginif (rising_edge(clk)then if (count = 10) thenif (count =00) thenlamp = 001 ;elsif (count = 01) thenlamp = 010 ;el

38、sif(count=10) then lamp = 100 ;end if;count = count + 1;else count = 00;end if;end if;end process lamper;END fun ;std_logic_vector( 1 downto 0);signal count1: std_logic_vector( 1 downto 0);BEGINspeaker:process (clk)begin speak =10) then count1=00;elsecount1 = count1 + 1;end if; end if;end if;end pro

39、cess speaker;第六部分：整體電路連接部分第六部分：整體電路連接部分l64選32數(shù)據(jù)選擇器作用lsel=1時(shí)選擇輸出里程計(jì)費(fèi)部分lsel=0時(shí)選擇輸出計(jì)時(shí)部分。第六部分：整體電路連接部分（續(xù)）第六部分：整體電路連接部分（續(xù)）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MUX64_32 IS PORT( d_in1,add_rom1,seg_in1,dip1 :IN STD_LOGIC_VECTOR(7 DOWNTO 0);seg_in2,dip2,d_in2,add_

40、rom2 :IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL :IN STD_LOGIC;d_out,add_rom_out,seg_o,dip_out :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END MUX64_32; ARCHITECTURE ARCH OF MUX64_32 IS BEGIN seg_o=seg_in1 WHEN SEL=1 ELSE seg_in2;dip_out=dip1 WHEN SEL=1 ELSE dip2;d_out=d_in1 WHEN SEL=1 ELSE d_in2;add_rom_out=add_

41、rom1 WHEN SEL=1 ELSE add_rom2; END ARCH;第六部分：整體電路連接部分（續(xù)）第六部分：整體電路連接部分（續(xù)）l32選16數(shù)據(jù)選擇器作用lsel=1時(shí)選擇輸出數(shù)碼管數(shù)據(jù)和地址信息lsel=0時(shí)選擇輸出點(diǎn)陣數(shù)據(jù)和地址信息第六部分：整體電路連接部分（續(xù)）第六部分：整體電路連接部分（續(xù)）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX32_16 IS PORT( d_in, add_rom :IN STD_LOGIC_VECTOR(7 DOWNTO 0);seg_in,dip :IN STD_LOGIC_VE

42、CTOR(7 DOWNTO 0);SEL :IN STD_LOGIC;seg_o,d_out :OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END MUX32_16; ARCHITECTURE ARCH OF MUX32_16 IS BEGIN seg_o=seg_in WHEN SEL=1 ELSE d_in ;d_out=dip WHEN SEL=1 ELSE add_rom ; END ARCH;第六部分：整體電路連接部分（續(xù)）第六部分：整體電路連接部分（續(xù)）控制模塊作用當(dāng)SEL=0時(shí)add_PIO對(duì)應(yīng)點(diǎn)陣地址當(dāng)SEL=1時(shí)add_PIO對(duì)應(yīng)數(shù)碼管地址當(dāng)RST_P

43、IO = 0時(shí)不寫入底板當(dāng)RST_PIO = 1時(shí)寫入底板第六部分：整體電路連接部分（續(xù)）第六部分：整體電路連接部分（續(xù)）library ieee; use ieee.std_logic_1164.all;entity KH_Cntrl_2 is port(SEG: in std_logic_vector(7 downto 0);DIO: in std_logic_vector(7 downto 0);sel,RST_PIO: in std_logic;nCS0_PIO: out std_logic;nOE_PIO,nWE_PIO: out std_logic;data_PIO: inout

44、std_logic_vector(7 downto 0);add_PIO: out bit_vector(4 downto 0);end KH_Cntrl_2;architecture KH_Model_A of KH_Cntrl_2 is SIGNAL temp:std_logic_vector(8 downto 0);begintemp=sel & DIO;process(temp,RST_PIO,sel)begin if(RST_PIO = 0) thennCS0_PIO = 1;nOE_PIO = 1;nWE_PIO = 1;elsenCS0_PIO = 0;nOE_PIO = 1;