AD數(shù)據(jù)手冊(cè)部分內(nèi)容中文翻譯

1、AD9959數(shù)據(jù)手冊(cè)（部分）GENERAL DESCR IP TiON 述The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, am

2、plification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is per

3、formed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.AD9959含有四個(gè)直接數(shù)字頻率合成器(DDS，提供各通道獨(dú)立的頻率、相位和振幅控 制。這種靈活性可以用來(lái)糾正信號(hào)之間的不平衡，這種不平衡是由于模擬處理，如濾波，放 大，或PCB布局相關(guān)的不匹配導(dǎo)致。因?yàn)樗型ǖ拦灿靡粋€(gè)系統(tǒng)時(shí)鐘，因此固有

4、的同步。也 支持多個(gè)設(shè)備的同步。AD9959可以執(zhí)行16級(jí)頻率、相位、振幅(FSK PSK ASK調(diào)制，通 過(guò)將數(shù)據(jù)傳到配置引腳執(zhí)行。此外，AD9959還支持頻率、線性掃頻、相位或振幅的應(yīng)用，如 雷達(dá)和儀表。The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI- compatible mode of operation that is virtually identical to the SPI

5、 operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ SDIO_2/SDIO_3)that allow four programmable modes of serial I/O operation.AD9959的串行I/O端口提供了多種配置，提供顯著的靈活性。串行I / O端口提供了一個(gè) SPI兼容的操作模式，SPI操作與較早的模擬設(shè)備公司 DDS產(chǎn)品幾乎相同。靈活性是通過(guò)四個(gè) 數(shù)據(jù)引腳(sdio_0 /

6、 sdio_1 /sdio_2 / sdio_3)允許四可編程串行I/O操作模式來(lái)實(shí)現(xiàn)的。The AD9959 uses advanced DDStechnology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency t

7、uning word, 14 bits of phase offset, and a 10-bit output scale multiplier.AD9959采用先進(jìn)的DDS技術(shù)，提供低高性能低功耗。該器件集成了四個(gè)高速10位DAC具有優(yōu)良的寬帶和窄帶SFDR每個(gè)通道有一個(gè)專門的32位頻率調(diào)諧字，14位相位偏移，和 一個(gè) 10 位幅度調(diào)節(jié)輸出。The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Eac

8、h DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLKas the input and the DAC providing the output. The REFCLKinput source is common to all channels and can be driven directly or used in

9、combination with an integrated REFCLKmultiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLKsource. The crystal must be between 20 MHz

10、 and 30 MHz. The crystal can be used in combination with the REFCLK multiplier.DAC的輸出供給參考必須通過(guò)電阻接到 AVDD或接到AVDD中心抽頭變壓器。每個(gè) DAC 有自己的可編程參考，能提供各通道的不同滿量程電流。REFCL作為輸入時(shí)，DDS核心作為一個(gè)高分辨率分頻器，以DAC提供輸出。REFCLI輸入源對(duì)所有通道是一樣的，可直接驅(qū)動(dòng)或 用于與一個(gè)集成的REFCL1乘法器組合（PLL）,最高500 MS PS PLL倍增因子可編程，從4到 20的整數(shù)。REFCL輸入還可作為一個(gè)振蕩器電路，支持外部晶振作為參考源

11、。該晶振必須介 于20兆赫和30兆赫。晶振可用于與REFCLI倍頻組合。The AD9959 comes in a sp ace-savi ng 56-lead LFCS P package. The DDS core (AVDD and DVDD pins) is po wered by a 1.8 V supply. The digital I/O in terface (SPI) op erates at 3.3 V and requires DVDD_I/O (Pin 49) be conn ected to 3.3 V. The AD9959 op erates over the i

12、n dustrial temp erature range of -40° C to +85 C.AD9959使用節(jié)省空間的56引腳LFCS封裝。DDS的核心(AVDD和 DVDD弓I腳)由1.8 V 供電。數(shù)字I / O接口(SPD的工作在3.3 V,要求dvdd_I/O (引腳49)連接到3.3 V。AD9959 可運(yùn)行在超過(guò)工業(yè)溫度范圍的-40 °C到85°C。ABSOLUTE MAXIMUM RATINGS色對(duì)最大額定值Rati ng額定值150° C4 V2 V-0.7 V to +4 V5 mA-65° C to +150°

13、; C-40° C to +85° C 300° C21° C/W2° C/WTable 2.表 2 P arameter 參數(shù)Maximum Jun cti on Temp erature 最大結(jié)溫DVDD_I/O (Pin 49)AVDD, DVDDDigital Input Voltage (DVDD_I/O = 3.3 V數(shù) 字輸入電壓Digital Out put Curre nt 數(shù)字輸出電流Storage Temp erature Range 存儲(chǔ)溫度Op erati ng Temp erature Range操作溫度Lead T

14、emp erature (10 sec Solderi ng焊接溫度0 JA0 JCTable 3. Pin Fu nction Descri ptio ns 引腳說(shuō)明引腳助記符I/O14針描述3MASTER_RESET I6高電平有效復(fù)位引腳；將使 AD9959內(nèi)部寄存器復(fù)位 到缺省狀態(tài)，如寄存器圖和位描述部分的描述。4PWR DWN CTLI4外部電源控制（PDQ40-43P0-P3I1、35、7用于調(diào)制（FSK,PSK,ASK數(shù)據(jù)引腳，啟動(dòng)/停止掃頻累 加器或用于輸出幅度的斜坡上升或下降 .數(shù)據(jù)同步于 引腳SYNC_CLK（同步時(shí)鐘 54腳）.數(shù)據(jù)必需滿足 SYNC_CLK設(shè)置和保持時(shí)間

15、的要求；引腳的功能由數(shù) 據(jù)配置說(shuō)明位（PPC控制（FR114:12）.46IO_UPDATEI8上升沿使I/O 口緩沖中的數(shù)據(jù)傳送到活動(dòng)寄存器。數(shù) 據(jù)同步于引腳SYNC_CLK（同步時(shí)鐘54腳）.IO-UPDATE必需滿足sync CLK設(shè)置和保持時(shí)間的要 求，以保證到DAC輸出的數(shù)據(jù)有固定的延遲管道，否 貝嘰不確定有± 1個(gè)同路時(shí)鐘（sync clk周期的數(shù)據(jù)管道存在。最小的脈沖寬度是1個(gè)同步時(shí)鐘周期。47CSI10低電平片選；允許多器件共用I/O總線。48SCLKI12I/O操作的串行數(shù)據(jù)時(shí)鐘；數(shù)據(jù)位在SCLK勺上升沿寫 入，在下降沿讀取。50SDIO 0I/O9串行數(shù)據(jù)引腳51

16、 51SDIO_1 SDIO_2I/O11、13用于串行數(shù)據(jù)引腳或啟動(dòng)輸出幅度的斜坡上升或下 降53SDIO_3I/O14用于串行數(shù)據(jù)引腳或啟動(dòng)輸出幅度的斜坡上升或下 降；在單位或2位模式，此引腳用于SYNC_I/O如果 SYNC 1/C功能未使用，連接到地或邏輯 0。在單位或 者2位模式中，不要讓此引腳浮地。THEOR Y OF OP ERATIO操作原理DDS CORE DDS 核心The AD9959 has four DDS cores, each consisting of a 32-bit phase accumulator and p hase-to-a mp litude co

17、nv erter. Together, these digital blocks gen erate a digital sine wave whe n the p hase accumulator is clocked and the p hase in creme nt value (freque ncy tuning word) is greater than 0. The phase-to-amplitude converter simultaneously translates phase information to amp litude in formati on by a co

18、s( 0) op erati on. The out put freque ncy (fOUT) of each DDS cha nnel is a function of the rollover rate of each p hase accumulator. The exact relati on shi p is give n in the follow ing equati on:AD9959有四個(gè)DDS內(nèi)核，每個(gè)含32相位累加器和相位-幅度轉(zhuǎn)換器。這些數(shù)字模塊在一 起產(chǎn)生數(shù)字正弦波，當(dāng)相位累加器的時(shí)鐘和相位增量值(頻率調(diào)諧字)大于 0。相位幅度轉(zhuǎn) 換器同時(shí)通過(guò)COS(0 )操作，轉(zhuǎn)

19、換相位信息到幅度信息。每個(gè) DDS通道輸出頻率(fout)是 每個(gè)相位累加器的轉(zhuǎn)換函數(shù)。確切的關(guān)系在下面的等式中給出：£(FTW)(fs)232foutwhere: fs is the system clock rate.FTW is the frequency tuning word and is 0 < FTW < 231. 232 rep rese nts the p hase accumulator cap acity.其中：fs是系統(tǒng)時(shí)鐘速率。FTW是頻率調(diào)諧字和0W FTWC 231。232表示相位累加器容量。Because all four cha nn e

20、ls share a com mon system clock, they are in here ntly synchroni zed. 因?yàn)樗兴膫€(gè)通道共用一個(gè)系統(tǒng)時(shí)鐘，他們是本質(zhì)同步的。The DDS core architecture also supp orts the cap ability to p hase offset the out put sig nal, which is performed by the cha nnel phase offset word (CPOW). The CPOW is a 14-bit register that stores a p ha

21、se offset value. This value is added to the out put of the p hase accumulator to offset the curre nt p hase of the out put sig nal. Each cha nnel has its own p hase offset word register. This feature can be used for placing all cha nn els in a known p hase relati onship relative to one ano ther.The

22、exact value of p hase offset is give n by the follow ing equati on:POW?=尹 X360 °DDS的核心架構(gòu)還支持輸出信號(hào)的相位偏移，由信道的相位偏移（ epow）字實(shí)現(xiàn)。cpow 是一個(gè)14位的寄存器，存儲(chǔ)相位偏移值。此值添加到相位累加器的輸出，偏移電流信號(hào)相位。 每個(gè)通道都有自己的相位偏移字寄存器。此功能可用于設(shè)置所有通道的相位相關(guān)關(guān)系。相位 偏移量實(shí)際值由以下方程給出：DIGITAL-TO-ANALOG CONVERT數(shù)模轉(zhuǎn)換The AD9959 incorpo rates four 10-bit curre

23、nt out put DACs. The DACc onverts a digital code (amp litude) into a discrete an alog qua ntity. The DAC curre nt out puts can be modeled as a curre nt source with high out put imp eda nee (typi cally 100 k Q ). Un like many DACs, these curre nt out puts require term in atio n into AVDD via a resist

24、or or a cen ter-ta pped tran sformer for exp ected curre nt flow.AD9959采用四個(gè)10位電流輸出DAC DAC將數(shù)字代碼(幅度)轉(zhuǎn)換成離散的模擬量。DAC的電流輸出可以被建模為高輸出阻抗的電流源(通常為100 KQ)。不像許多DAC這些電流輸出要求通過(guò)電阻器或中心抽頭變壓器接到AVDD以獲得預(yù)期的電流。Each DAC has comp leme ntary out puts that p rovide a comb ined full-scale out put curre nt (Iout+ Iout). The out

25、puts always sink curre nt, and their sum equals the full-scale curre nt at any point in time. The full-scale curre nt is con trolled by means of an exter nal resistor (RSET) and the scalable DAC current control bits discussed in the Modes of Operation section. The resistor, RSETjs connected between

26、the DAC_RSETpin and analog ground (AGND). The full-scale current is in versely prop orti onal to the resistor value as follows:18.91Rset =廠lout(max)每個(gè)DAC互補(bǔ)輸出提供一個(gè)組合的滿量程輸出電流(輸出電流和輸入電流)。輸出總是吸收電流，在任何時(shí)間點(diǎn)它們的和等于滿量程電流。 滿量程電流通過(guò)一個(gè)外部電阻器(RSET 控制和操作模式部分中討論的 DAC的電流位進(jìn)行尺度控制。電阻 RSET連接DAC_RES腳和 模擬地(AGND)之間。滿量程電流與電阻值成

27、反比：The maximum full-scale out put curre nt of the comb ined DAC out puts is 15 mA, but limiti ng the out put to 10 mA p rovides op timal sp urious-free dyn amic range (SFDR) p erforma nee. The DAC out put voltage comp lia nee range is AVDD + 0.5 V to AVDD - 0.5 V. Voltagesdevel oped bey ond this ran

28、ge may cause excessive harm onic distorti on. Proper atte nti on should be p aid to the load termin atio n to kee p the out put voltage within its comp lia nee ran ge. Exceed in gthis range could poten tially dam-age the DAC out put circuitry.最大滿量程的輸出組合 DAC電流為15 mA,但限制輸出到10毫安以提供最優(yōu)的無(wú)雜散動(dòng) 態(tài)范圍(SFDR性能。DA

29、C的輸出電壓范圍為 AVDD + 0.5 V電壓AVDD-0.5V。超出了這個(gè)范 圍可能會(huì)導(dǎo)致諧波失真過(guò)大。應(yīng)注意負(fù)載，以保持其輸出電壓在其合規(guī)范圍。超過(guò)這個(gè)范圍 可能損壞DAC輸出電路。MODES OF OP eratio操 作模式There are many combinations of modes (for example, single- tone, modulation, linear sweep) that the AD9959 can perform simultaneously. However, some modes require multiple data pins,

30、which can impose limitations. The following guidelines can help determine if a specific combination of modes can be performed simultaneously by the AD9959.有許多組合模式(例如 單音 調(diào)制 線性掃頻) AD9959 能夠同時(shí)進(jìn)行。然而 一些 模式需要多個(gè)數(shù)據(jù)引腳 它可以施加限制。下面的指南可以幫助確定模式的特定組合是否可 以用AD9959同時(shí)進(jìn)行。CHANNEL CONSTRAINT GUIDELINE!約束準(zhǔn)貝 U Sin gle-t on

31、e mode, two-level modulatio n mode, and lin ear swee p mode can be en abled on any channel and in any combination at the same time 單音模式，兩電平調(diào)制模式，線性掃頻繁模式，可以啟用在任何通道，并在同一時(shí)間任何組 合。 Any one or two channels in any combination can perform four-level modulation. The remaining channels can be in single-tone mo

32、de.任何一個(gè)或兩個(gè)通道可在任何組合執(zhí)行四電平調(diào)制。剩余的通道可以在單音模式。 Any channel can perform eight-level modulation. The three remaining channels can be in single-tone mode.任何一個(gè)通道都可以執(zhí)行八電平調(diào)制。三個(gè)剩余信道可以在單音模式。 Any channel can perform 16-level direct modulation. The three remaining channels can be in single-tone mode.任何一個(gè)通道都可以執(zhí)行 16電平

33、直接調(diào)制。三個(gè)剩余信道可以在單音模式。 The RU/RD function can be used on all four channels in single-tone mode. See the Output Amplitude Control Mode section for the RU/RD function.所有四個(gè)通道可以在單音模式下使用RU / RD功能。見輸出幅度控制塊。 When Profile Pin P2 and Profile Pin P3 are used for RU/RD, any two channels can perform two-level modu

34、lation with RU/RD or any two channels can perform linear frequency or phase sweep with RU/RD. The other two channels can be in single-tone mode.當(dāng)配置引腳P2和配置引腳P3用于RU/ RD,任何兩個(gè)通道可以執(zhí)行二電平調(diào)制與RU/ RD,或任何兩個(gè)通道可以執(zhí)行線性頻率或相位掃描與RU/RDb其他兩個(gè)通道可以處于單音模式。 When Profile Pin P3 is used for RU/RD, any channel can be used in e

35、ight-level modulation with RU/RD. The other three channels can be in single-tone mode.當(dāng)配置引腳P3用于RU/ RD,任何通道可以用在八電平調(diào)制與 RU/RD另三通道可以在單音 模式。? When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any one or two channels, any three channels, or all four channels can perform two-level modulation wit

36、h RU/RD. Any channels not in the two-level modulation can be in single-tone mode.當(dāng) sdio_1 sdio_2 和 sdio_3 引腳用于 RU/RD 任何一個(gè)或兩個(gè)通道 三通道 四通道或可 以進(jìn)行兩級(jí)調(diào)制。其它任何通道不在兩級(jí)調(diào)制的 可以處于單音模式。? When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any one or two channels can perform four-level modulation with RU/RD.

37、 Any channels not in four-level modulation can be in single-tone mode.當(dāng) sdio_1 sdio_2 和 sdio_3 引腳用于 RU/RD 任何一個(gè)或兩個(gè)通道可以進(jìn)行四級(jí)調(diào)制。其 它任何通道進(jìn)行單頻模式。? When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any channel can perform16-level modulation with RU/RD. The other three channels can be in single-to

38、ne mode.當(dāng)sdio_1, sdio_2，和sdio_3引腳用于RU/RD,任何一個(gè)通道可以進(jìn)行16級(jí)調(diào)制，其他三個(gè) 渠道可以在單頻模式。? Amplitude modulation, linear amplitude sweep modes, and the RU/RD function cannot operat e simultaneously, but frequency and phase modulation can operate simultaneously as the RU/RD function.振幅調(diào)制，線性振幅掃描模式，和RU/ RD功能不能同時(shí)操作，但是，頻率

39、和相位調(diào)制可以同時(shí)隨著RU/RD功能操作。PO WER SUPP LIE電源供應(yīng)The AVDD and DVDD supply pins provide power to the DDS core and supporting analog circuitry. These pins connect to a 1.8 V nominal power supply. The DVDD_I/O pin connects to a 3.3 V nominal power supply. All digital inputs are 3.3 V logic except for the CLK_MO

40、DE_SEiLnput. CLK_MODE_SEL (Pin 24) is an analog input and should be operated by 1.8 V logic.AVDD和DVDD引腳提供DDS核心的電力供應(yīng)，和支持模擬電路。這些引腳連接到 1.8 V額定 電源。dvdd_I/O引腳連接到3.3 V額定電源。所有數(shù)字輸入3.3 V邏輯，除了 clk_mode_sel輸 入。clk_mode_sel (引腳24)是一個(gè)模擬輸入和應(yīng)由1.8伏邏輯操作。SINGLE-TONE MOD單音模式Single-tone mode is the default mode of oper

41、ation after a master reset signal. In this mode, all four DDS channels share a common address location for the frequency tuning word (Register 0x04) and phase offset word (Register 0x05). Channel enable bits are provided in combination with these shared addresses. As a result, the frequency tuning w

42、ord and/or phase offset word can be independently programmed between channels (see the following Step 1 through Step 5). The channel enable bits do not require an I/O update to enable or disable a channel.單音模式是主復(fù)位信號(hào)后的缺省操作模式。在這種模式下，所有四個(gè)DDS通道共享頻率調(diào)諧字(寄存器0x04)和相位偏移字(寄存器0x05)。通道使能位與這些共享地址組合使用。 作為結(jié)果，頻率調(diào)諧字

43、和 /或相位偏移字可以在通道之間獨(dú)立編程(見下面步驟 1 到步驟 5)。 通道使能位不要求 I/O 更新使能或禁用信道。See the Register Maps and Bit Descriptions section for a description of the channel enable bits in the channel select register (CSR, Register 0x00). The channel enable bits are enabled or disabled immediately after the CSR data byte is writ

44、ten.CSR寄存器請(qǐng)參見寄存器映射和位描述部分，信道使能位的描述在通道選擇寄存器( 0x00)。在CSF數(shù)據(jù)字節(jié)寫入后，通道使能位立即使能或禁用。Address sharing enables channels to be written simultaneously, if desired. The default state enables all channel enable bits. Therefore, the frequency tuning word and/or phase offset word is common to all channels but written

45、only once through the serial I/O port.如果需要的話，地址共享使信道能夠同時(shí)寫入。默認(rèn)狀態(tài)啟用所有通道使能位。因此， 頻率調(diào)諧字和 /或相位偏移字是所有通道共用的，可以只通過(guò)串行輸入輸出端口寫一次。The following steps present a basic protocol to program a different frequency tuning word and/or phase offset word for each channel using the channel enable bits.下面的步驟介紹了一個(gè)基本的協(xié)議，用來(lái)使用通

46、道使能位對(duì)每個(gè)通道編程實(shí)現(xiàn)不同頻率 調(diào)諧字和 / 或相位偏移字。1Power up the DUT and issue a master reset. A master reset places the part in single-tone mode and single-bit mode for serial programming operations (refer to the Serial I/O Modes of Operation section). Frequency tuning words and phase offset words default to 0 at thi

47、s point.DUT 上電和執(zhí)行主復(fù)位。主復(fù)位將部件置于單音模式和單位模式串行編程操作(參照串 行 I/O 模式操作部分)。頻率調(diào)諧字和相位偏移字默認(rèn)為 0 在這一點(diǎn)上。2. Enable only one channel enable bit (Register 0x00) and disable the other channel enable bits.只讓一個(gè)通道使能位使能(寄存器 0x00)和禁用其他通道使能位。3. Using the serial I/O port, program the desired frequency tuning word (Register 0x04

48、) and/or the phase offset word (Register 0x05) for the enabled channel.使用串行I/O 口，為使能通道的頻率調(diào)諧字(寄存器0x04)和/或相位偏移字(寄存器0x05) 編程。4. Repeat Step 2 and Step 3 for each channel.每個(gè)通道重復(fù)步驟 2 和步驟 3。5 Send an I/O update signal. After an I/O update, all channels should output their programmed frequency and/or phase

49、 offset value.發(fā)送 I/O 更新信號(hào)。在 I/O 更新后，所有通道應(yīng)輸出其編程頻率和 /或相位偏移值。Single-Tone ModeMatched Pipeline Delay 單音模式匹配管道延遲In single-tone mode, the AD9959 offers matched pipeline delay to the DAC input for all frequency, phase, and amplitude changes. This avoids having to deal with different pipeline delays between

50、 the three input ports for such applications. The feature is enabled by asserting the matched pipe delays active bit found in the channel function register (CFR,Register 0x03). This feature is available in single-tone mode only在單頻模式，對(duì)于DAC輸入的所有頻率，相位和振幅的變化提供相匹配的AD9959管道延遲。這避免了此類應(yīng)用處理這些三個(gè)輸入端口之間的不同管道延遲。該

51、功能是通過(guò)維持在 通道功能寄存器(CFR寄存器0x03)中的匹配管道延遲活動(dòng)位實(shí)現(xiàn)。此功能僅適用于單音 模式。REFERENCE CLOCK MOD參勞時(shí)鐘模式The AD9959 supports multiple reference clock configurations to generate the internal system clock. As an alternative to clocking the part directly with a high frequency clock source, the system clock can be generated usi

52、ng the internal, PLL-based reference clock multiplier. An on-chip oscillator circuit is also available for providing a low frequency reference signal by connecting a crystal to the clock input pins. Enabling these features allows the part to operate with a low frequency clock source and still provid

53、e a high update rate for the DDS and DAC. However, using the clock multiplier changes the output phase noise characteristics. For best phase noise performance, a clean, stable clock with a high slew is required (see Figure 17 and Figure 18).AD9959支持參考時(shí)鐘的多個(gè)配置，產(chǎn)生內(nèi)部的系統(tǒng)時(shí)鐘。作為一種選擇，部件時(shí)鐘直接 使用一個(gè)高頻率的時(shí)鐘源，系統(tǒng)時(shí)鐘可

54、以使用內(nèi)部，基于PLL參考時(shí)鐘乘法器生成。一個(gè)片上振蕩器電路也可通過(guò)連接晶體的時(shí)鐘輸入引腳，提供一個(gè)低頻參考信號(hào)。啟用這些功能， 允許部件操作低頻時(shí)鐘操作源，仍然可以提供一個(gè)高更新速率的 DDS 和數(shù)模轉(zhuǎn)換器。然而， 要使用時(shí)鐘乘法器改變輸出相位噪聲特性。 對(duì)于最佳相位噪聲性能， 高轉(zhuǎn)換速率時(shí)一個(gè)干凈，穩(wěn)定的時(shí)鐘是必需的（見圖 17 圖 18）。SCALABLE DAC REFERENCE CURRENT CONTROL M可縮放 DAC參考電流控制模式RSET is common to all four DACs. As a result, the full-scale currents a

55、re equal by default. The scalable DAC reference can be used to set the full-scale current of each DAC independent from one another. This is accomplished by using the register bits CFR9:8. Table 5 shows how each DAC can be individually scaled for independent channel control. This scaling provides for

56、 binary attenuation.RSET是所有四個(gè)DAC共用的。其結(jié)果是，滿量程電流在缺省情況下相等。可縮放 DAC 參考用于設(shè)置每個(gè)DAC獨(dú)立的滿量程電流。這是通過(guò)使用寄存器位 CFR 9:8完成。表5顯示 了如何讓每個(gè)DAC可以單獨(dú)縮放獨(dú)立的信道控制。這個(gè)縮放提供二進(jìn)制衰減。LSB Current State LSB的當(dāng)前狀態(tài) Full scale 全尺度Half scale 半尺度Quarter scale 四分之一尺度Eighth scale 八分之一尺度Table 5. DAC Full-Scale Curren表 5 DAC滿量程電流 CFR9:811011000POWER

57、-DOWN FUNCTIONS 電功能The AD9959 supports an externally controlled power-down feature and the more common software programmable power-down bits found in previous Analog Devices DDS products. The software control power-down allows the input clock circuitry, the DAC, and the digital logic (for each separ

58、ate channel) to be individually powered down via unique control bits (CFR7:6). These bits are not active when the externally controlled power-down pin (PWR_DWN_CTL) is high. When the input pin, PWR_DWN_CTL, is high, the AD9959 enters a power-down mode based on the FR16 bit. When the PWR_DWN_CTL input pin is low, the external power-down control is inactive. When FR16 = 0 and the PWR_DWN_CTLinput pin is high, the AD9959 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digit