單片機(jī)89C52中英文對(duì)照翻譯(經(jīng)典版)

1、 DescriptionThe AT89S52 is a low-power,microcontroller with 8Kbytes of in-system programmable Flash memory.The device is manufactured using Atmels high -density nonvolatilememory technology and is compatible with the industry-standard 80C51instruction set and pinout. The on-chip Flash allows the pro

2、grammemoryto be reprogrammed in-system or by a conventional nonvolatile grammable Flash ona monolithic chip, the Atmel AT89S52 is apowerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52provides the

3、following standard features: 8K bytes of Flash, 256 bytes ofRAM, 32 I/O lines, Watchdog timer, two data pointers, three 16 -bittimer/counters, a six-vector two-level interrupt architecture, a full duplexclock circuitry. In addition, theto zeroPin DescriptionSupply voltage.1 / 16 Ground.Port 0 is an

4、8-bit open drainbidirectional I/O port. As anoutput port,each pin can sink eight TTL inputs. When 1sare written to port 0 pins, thepins can be used as highimpedanceinputs.Port0 can also be configured tobe the multiplexed loworder address/data bus during accesses to externalprogram and data memory. I

5、n this mode, P0 has internal pullups.Port 0also receives the code bytes during Flash programming and outputs thecode bytes during program verification.Externalduring program verification.Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port2 output buffers can sink/source four TTL

6、 inputs.When 1s are written toPort 2 pins, they are pulled high bythe internal pullups and can be used asinputs. As inputs,Port 2 pins that are externally being pulled low willsourcecurrent (IIL) because of the internal pullups.Port 2 emits the high -order address byte during fetchesfrom external pr

7、ogram memory andduring accesses toexternal data memory that use 16 -bit addresses (MOVXDPTR). In this application, Port 2 uses strong internal pull -ups whenemitting 1s. During accesses to external data memory that use 8 -bit2 / 16 addresses (MOVX RI), Port 2 emits the contents of the P2 SpecialFunc

8、tion Register. Port 2 also receives the high -order address bits andsome control signals during Flash programming and verification.source current (IIL) because of the pullups.Port 3of various special features of the AT89S52, as shown in the followingtable.Port 3 also receives some control signals fo

9、r Flash programming andverification.Reset input. A high on this pin for two machine cycles while theoscillator is running resets the device. This pin drives High for 96oscillator periods after the Watchdog times out.The DISRTO bit in SFRAUXR (address 8EH) can be used to disable this feature. In the

10、defaultstate of bit DISRTO,the RESET HIGH out feature is enabled.that one ALE pulse is skipped during each access to external datamemory.If desired, ALE operation can be disabled by setting bit 0 ofSFRis in external execution mode.Program Store Enable (PSEN) is the read strobe to externalprogramEA/V

11、PPInput to the inverting oscillator amplifier and input to the internalclock operating circuit.XTAL2A map of the on-chipFunctionRegister (SFR) space is shown in Table 1.Noteaddresses are occupied, and unoccupied addressesmemory area called the Specialimplemented on the chip.Read accesses to these ad

12、dresses will in generalreturn random data, and write accesses will have an indeterminateeffect.User software should not write 1s to these unlisted locations,sincethey may be used in future products to invokenew features. In that case,the reset or inactive values of the new bits will always be 0.Time

13、r 2 Registers:Control and status bits are contained in registers T2CON (shown inTable 2) and T2MOD (shown in Table 3) for Timer 2. The register pair4 / 16 (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16 -bit capture mode or 16-bit auto-reload mode.The individual interrupt enable

14、bits are in the IE register. Twopriorities can be set for each ofthe six interrupt sources in the IP register.Memory OrganizationMemory. Up to 64K bytes each of external Program and Data Memory canIf the EA pin is connected to GND, all program fetexternal memory.On the AT89S52, if EA is connected to

15、 VCC, programfetches to addresses 0000H through 1FFFH are directed to internalmemory and fetches to addresses 2000H through FFFFH are to externalmemory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128bytes occupy a parallel address space to the Special Function Registers.Thi

16、s means that the upper 128 bytes have the same addresses as the SFRspace but are physically separate from SFR space. When an instr uctionMOV R0, #data5 / 16 so theThe WDT is intended as a recovery method in situationswhere theCPU may be subjected to software upsets. The WDT consists of a 13 -bitcoun

17、ter and the Watchdog Timer Reset (WDTRST) SFR. The WDT isdefaulted to disable from exiting reset. To enable the WDT, a user mustwrite01EH and 0E1H in sequence to the WDTRST register (SFR location0A6H). When the WDT is enabled, it will increment every machine cyclewhile the oscillator is running. The

18、 WDT timeout period is dependent onthe external clock frequency. There is no way to disable the WDT exceptthrough reset (either hardware reset or WDT overflow reset). When WDToverflows, it will drive an output RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and

19、 0E1H in sequence to13-bitcounteroverflows8191(1FFFH), and this will reset the device. When the WDT is enabled, itwill increment every machine cycle while the oscillator is running. Thismeans the user must reset the WDT at least every 8191 machine cycles. Toreset the WDT the user must write 01EH and

20、 0E1H to WDTRST. WDTRSTis a write-only register. The WDT counter cannot be read or written. WhenWDT overflows, it will generate an output RESET pulse at the RST pin.The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To makethe best use of the WDT, it should be serviced in those sections of code

21、that will periodically be executed within the time required to prevent aWDT reset.6 / 16 WDT During Power-down and IdleIn Power-down mode theoscillator stops, which means the WDT alsostops. While in Power-down mode, the user does not need to service theWDT. There are two methods of exiting Power-dow

22、n mode: by a hardwarereset or via a level-activated external interrupt which is enabled prior toentering Power-down mode. When Power-downWDT does not overflow within a few states of exiting Power -down, it isbest to reset the WDT just before entering Power-down mode. Beforegoing into the IDLE mode,

23、the WDIDLE bit in SFR AUXR is used todetermine whether the WDT continues toThe UART in the AT89S52 operates the same way as the UART in theAT89C51 and AT89C52. For further information on the UAR T operation,refer to the ATMEL Web site (). From the home page, select8051 -Architecture Flash Microcontr

24、oller,7 / 16 Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0and Timer 1 in the AT89C51 and AT89C52. Forfurther information on theTimer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer oran event counter. The type of operation is selected by bit C/T

25、2 in the SFRCapture ModeIn the capture mode, two options are selected by bit EXEN2 inT2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon8 / 16 Timer 2 can be programmed to count up or down when configured inits 16-bit auto-reload mode. This feature is invoked by the DCEN (DownCounte

26、r Enable) bit located in the SFR T2MOD (see Table 4). Upon reset,the DCEN bit is set to 0 so that timer 2 will default to count up. WhenDCEN is set, Timer 2 can count up or down, depending on the value of theT2EX pin.Figure 6 shows Timer 2 automaticallyIf EXEN2 = 0, Timer 2 counts up to 0FFFFH and t

27、hen sets the TF2 bitupon overflow. The overflow also causes the timer registers to be reloadedat T2EX makes Timer 2 count up. The timer will oveset the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and9 / 16 編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的10 / 16 程序校驗(yàn)時(shí)，輸出指令字節(jié)。程序校驗(yàn)時(shí)，需要外部上拉電阻。P2 口： P2 口是一個(gè)具有內(nèi)部

28、上拉電阻的 8 位雙向 I/O 口，P2 輸出緩沖器能驅(qū)動(dòng) 4 個(gè)TTL 邏輯電平。對(duì) P2 端口寫 “1” 時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（ IIL ）。在訪問外部程序存儲(chǔ)器或用 16 位地址讀取外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行 MOVX DPTR ）時(shí)， P2 口送出高八位地址。在這種應(yīng)用中， P2 口使用很強(qiáng)的內(nèi)部上拉發(fā)送 1。在使用 8位地址（如MOVX RI ）訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)， P2口輸出 P2 鎖存器的內(nèi)容。在 flash編程和校驗(yàn)時(shí)， P2 口也接收高 8位地址字節(jié)和一些控制信號(hào)。（PROG ）也用

29、作編程輸入脈沖。在一般情況下，ALE 以晶振六分之一的11 / 16 EA/VPP: 訪問外部程序存儲(chǔ)器控制信號(hào)。為使能從外部程序存儲(chǔ)器讀取指令， EA必須接 GND 。為了執(zhí)行內(nèi)部程序指令， EA應(yīng)該接VCC 。在flash 編程期間， EA也接收 12 伏VPP 電壓。XTAL1: 振蕩器反相放大器和內(nèi)部時(shí)鐘發(fā)生電路的輸入端。XTAL2: 振蕩器反相放大器的輸出端。特殊功能寄存器寄存器 T2CON 和T2MOD 包含定時(shí)器 2 的控制位和狀態(tài)位，寄存器對(duì)RCAP2H 和RCAP2L 是定時(shí)器 2的捕捉 /自動(dòng)重載寄存器。中斷寄存器：IE 中設(shè)12 / 16 著從外部尋址，尋址地址為： 20

30、00HFFFFH 。AT89S52 有256 字節(jié)片內(nèi)數(shù)據(jù)存儲(chǔ)器。高 128 字節(jié)與特殊功能寄存器重疊。也就是說高 128 字節(jié)與特殊功能寄存器有相同的地址，而物理上是分開的。當(dāng)一條指令訪問高于 7FH 的地址時(shí)，尋址方式?jīng)Q定 CPU 訪問高 128字 節(jié) RAM 還 特 殊 功 能 寄 存 器 空 間 。 直 接 尋 址 方 式 訪 問 特 殊 功 能 寄 存 器（SFR ）。例如，下面的直接尋址指令訪問0A0H （P2 口）存儲(chǔ)單元 MOVMOV R0 , #data堆棧操作也是簡介尋址方式。因此，高 128 字節(jié)數(shù)據(jù) RAM 也可用于堆棧WDT 是一種需要軟件控制的復(fù)位方式。 WDT 由13 位計(jì)數(shù)器和特殊功能寄存器中的看門狗定時(shí)器復(fù)位存儲(chǔ)器（ WDTRST ）構(gòu)成。 WDT 在默認(rèn)情況 下 無 法 工 作 ； 為 了 激 活 WDT ， 戶 用 必 須 往 WDTRST 寄 存 器 （ 地 址 ：0A6H ）中依次寫入 01EH 和0E1H 。當(dāng) WDT 激活后，晶振工作， WDT 在每個(gè)機(jī)器周期都會(huì)增加。 WDT 計(jì)時(shí)周期依賴于外部時(shí)鐘頻率。除了復(fù)位（硬件復(fù)位或 WDT 溢出復(fù)位），沒有辦法停止 WDT 工作。當(dāng) WDT 溢出，它將驅(qū)動(dòng)RSR 引腳一