fpga2016會議覆蓋架構(gòu)研討會

1、FPGA2016WorkshoponOverlayArchitecturesforHaydenKwok-HaySo,John GreggP erfaceajSpatial FPGA2016WorkshoponOverlayArchitecturesforHaydenKwok-HaySo,John GreggP erfaceajSpatial Debug & Debug Without Re-programming in FPGAs: On-Chip Vinodil,JamesHwang,WelsonSun,YogeshChobe,TomShui,e SDSoC: A Higher-level

2、Programming Environment for Zynq SoC and Ultrascale+ TanNguyen,SwathiT.Gurumani,KyleRupnow,DemingFCUDA-SoC: FPGACompiler.5-egration for Field-Programmable SoC with the CUDA-Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. g, Oren Firestein, Haselman, Stephen Heil, Kyle Holohan, Matt Humphr

3、ey, Tams Juhsz , Pu neet Sitaram a, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, AgileCo-DesignforaReconfigurable1:NeuralNetworksandOpenCL 1 Naveen Suda, Vikas Chandra, Ganesh Dasika, Vrudhula,Jae-sunSeo,Yunty, Yu

4、fei Ma, Sarma B. Throughput-OptimizedOpenCL-basedFPGAAcceleratorforLarge-Scale Convolutional Neural Networks.16-25JiantaoQiu,JieWang,SongYao,KaiyuanGuo,BoxunLi,ErjinZhou,JinchengYu,Tang,NingyiXu,SenSong,Yu Wang,: BingzheLi,M.HassanNajafi,DavidJ.Using Stochastic Computing to Reduce the Hardware Requi

5、rements for a Restricted Boltzmann Machine Classifier.36-41g,Min-YuTsai,Bo-YiHuang,Chia-HengAPlatform-ObliviousApproachforHeterogeneousComputing:ACaseStudywithCarlo-basedSimulationforMedicalApplications.BingzheLi,M.HassanNajafi,DavidJ.Using Stochastic Computing to Reduce the Hardware Requirements fo

6、r a Restricted Boltzmann Machine Classifier.36-41g,Min-YuTsai,Bo-YiHuang,Chia-HengAPlatform-ObliviousApproachforHeterogeneousComputing:ACaseStudywithCarlo-basedSimulationforMedicalApplications.42-Nadeshn,JohnWickerson,Felixerstein,eA.ACaseforWork-stealingonFPGAswithOpenCLAtomics.48-,urPhysicalDesign

7、of3DFPGAsEmbeddedwithMicro-channel-basedeling,DanaHow,DavidM.Lewis,Herman Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock singApplications 3Technical 3:Circuit Design, GraceZgheib,ortkipanidze,MuhsenOwaida,DavidNovo,Paolo SafeenHuda,Jason TimothyA.Linscott,BenjaminGojman,

8、RaphaelRubin,AndrDeHon GuohaoDai,YuzeChi,YuWang,:FPGA A Case Study of FPGP: sing Framework TayoOguntebi,Kunle ,KerminFleming,MichaelAdler,Felixerstein,JoelS. JinchengSu,XuanZeng,DianEfficientMemoryPartitioningforParallelDatasviaDataReuse.138-EveningPanel DerekelAcquiresAltera:HowWilltheWorldofFPGAsb

9、e5:Architecture JinchengSu,XuanZeng,DianEfficientMemoryPartitioningforParallelDatasviaDataReuse.138-EveningPanel DerekelAcquiresAltera:HowWilltheWorldofFPGAsbe5:ArchitectureandTools 5TuanD.A.Nguyen,AkashPRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems.149- David M. Lewis,

10、 Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken: hua,ChinnakkannuAdaikkalaRaj,HarnhuaNg,Kirvy Teo,NachiketCaseforDesign-SpecificMachineimingClosureofFPGADesigns.169-SenMa,Zeyad Aklah,David PaulGrigoras,PavelBurovskiy

11、,Wayne NachiketKapre,DehengGJanarbek Matai, Dustin ond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Resolve: Generation of High-orting Architectures from High-MichaelJ.Wirthlin,AndrewM.Keller,ChaseMcCloskey,ParkerRidd,DavidLee,SEU Mitigation and Validation of the LEON3 Soft sor Using Triple Redundancyf

12、orSpace Technical XinhengLiu,YaoChen,TanNguyen,SwathiT.Gurumani,KyleRupnow,DemingHighLevelSynthesis XinhengLiu,YaoChen,TanNguyen,SwathiT.Gurumani,KyleRupnow,DemingHighLevelSynthesisofComplexApplications:An,JohnWickerson,eA. AutomaticallyOptimizing the Latency, Area,andAccuracy of CProgramsfor High-D

13、avidReducingMemoryRequirementsforHigh-PerformanceandNumericallyStableGaussian GabrielWeisz,JosephMelber,YuWang,KerminFleming,ErikoNurvitadhi,JamesC.A Study of er-Chasing Performance on Shared-Memory 1 termmed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain PatrickA Low DDR Bandwidth 100

14、FPS iononFPGA(Abstract2D Discrete Wavelet EhsanGhasemi,:A Scalable Heterogeneous Dataflow Architecture For Big DatayticsUsingFPGAs (Abstract Only).274Ze-keWang,HuiYanCheah,JohnsPaul,BingshengHe,Wei luZha,XiJin,Tian An Improved Global Stereo-Matching on FPGA for Real-Time Applications WenchaoQian,Chr

15、istopherBabecki,RobertKaram,SwarupENFIRE: An Energy-efficient Fine-grainedSpatio-temporal Reconfigurable Computing Fabric (Abstact Only).275akshyaGoswami,DineshFloorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract MatthiasHinkfoth,RalfIncreasingtheUtilityofSelf-Calibration

16、MethodsinHigh-Systems(AbstractTimeJames J. Davis, g, Joshua M. Levine, Edward A. Stott, Peter Y. K. eA. LiTing,HarriWijaya,NachiketMachine-Learning driven Auto-Tuning of High-Level Synthesis for James J. Davis, g, Joshua M. Levine, Edward A. Stott, Peter Y. K. eA. LiTing,HarriWijaya,NachiketMachine-

17、Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract RonakKogta,SureshPurini,AjitingOptimizationfromScalarsorstoFPGAsinHLS(Abstract2 terJieLei,Yu-TingChen,YunsongLi,JasonA High-throughput Architecture for Lossless HLS (Abstract Only).277GirishDeshpande,DineshK.on FPGA DesignedAnAc

18、tivityAwarePlacementApproachFor3DFPGAs(AbstractTianqiWang,Bo Peng,Xian Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only).277SabrinaZereen,SundeepmmedA.S.Khalid,AnFPGA-BasedControllerfora77GHzMEMSTri-ModeAutomotiveRadar(Abstract BoPeng,TianqiWang,XiJin,C

19、huanjunAnFPGA-SOCBasedAcceleratingSolutionforN-bodyOND,SwathiT.Gurumani,SuhaibA.Fahmy,DemingChen,KyleAutomated Verification Code Generation in HLS Using Software Execution Tra (Abstract Only).278JingYe,YuHu,XiaoweiDCPUF: Placement and Routing based Dynamically Configured UnclonableFunctiononFPGA(Abs

20、tactSebastienBellon,ClaudioFavi,MiroslawMalek,MarcoMacchetti,coEvaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only).279YuBai,MingjieStochastic-BasedSpin-ProgrammableGateArraywithEmergingMTJDeviceTechnology (Abstract Only).279,JianWang,eiTestingFPGAerconnectsBasedonRepeatableConfigurationModulester3StefanVisser,HaraldHomulle,EdoardoA1GSa/s,ReconfigurableSoft-coreFPGAA