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1、Assignment1. Design an 8-bit upand downsynchronouscounter inVHDLwith thefollowing(1) The same portsAssignment1. Design an 8-bit upand downsynchronouscounter inVHDLwith thefollowing(1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-s(2

2、) The counter is with an asynchronous t assigns a specific initial value (3) The counter is synchronous data load control input for a new value of and an enable control input for allowing the up and down counting. The load input has a priority over the enable control input. This t when the operation

3、 isin sthe counter operationis(4) Some ypes, such as STD_LOGIC, UNSIGNED, SIGNED EGER, may Synthesize the design. Create a set of reasonable input waveforms for your design completeboth behavioral t-place&routesimulationsernalsignalsand/orincluded in waveformorlist 1、題目使用VHDL-所inout 8 bit reset 端口、l

4、oad 端口，load 先級(jí)比enable即 counterenable8 bit 8bit2、程序2、程序library use use entitycounter_bidirport inininstd_logic; up_down: instd_logic; incnt_inout: inoutstd_logic_vector(7downtoend architectureBehavioralofcounter_bidirsignalcnt_in: std_logic_vector(7downtosignalcnt_out:std_logic_vector(7downto0); 3、Te

5、st -signaloe:3、Test -signaloe:std_logic:=0; signalload:std_logic :=load0,cnt_inout 為輸出enable=currenttime:400ns wait for 300 ns;load=-當(dāng) t_inout作為輸入時(shí)(把 t_inoutcnt_incnt為高阻狀態(tài)-否則，即cnt_inout作為輸出時(shí)(把 t_out(即計(jì)數(shù)器計(jì)數(shù)輸出值)-end s(load,cnt_out,cnt_inout) if (load=1) cnt_inoutZ); cnt_in = cnt_inout;cnt_inout=cnt_ou

6、t; end if;end -counter_control: s(clk,-當(dāng)復(fù)位信號(hào)rst=1,cnt_out否則在時(shí)鐘的上升沿檢測(cè) t_inout-當(dāng)作為輸入時(shí)load=1 ), 把cnt_in中的數(shù)取進(jìn)來(lái)-end s(clk,rst) if (rst = 1)cnt_out0);elsif rising_edge(clk)if (load = 1) thencnt_out = cnt_in; elsif(enable=1) thenif (up_down = 0) then cnt_out=cnt_out+1;cnt_out=cnt_out-1; end if;endif; end if;end 4功能仿真（前仿4功能仿真（前仿真根據(jù)TestBench進(jìn)入程序之后，首先復(fù)位，這時(shí)cnt_out 0 4 之后，把 cnt_inout 變成了輸入信號(hào)，并且給其賦了10000011；在load 加載該值之后，200ns 之后將cnt_inoutcnt_inout131100ns129(時(shí)50 ns)，然后遇到了up_down=0，開始做遞增。5、ISim 時(shí)序仿真（后仿真在ISE Prope PropertiesFPGA，仿真器（Simulator）選擇為“ISim在仿真（Simulation）下拉列表中，選擇在ISim在后仿真的波形中，可以看到輸出（輸入）信號(hào)cnt