電子秒表設(shè)計(jì)VHDL

1、一、設(shè)計(jì)題目：基于VHDL語(yǔ)言的電子秒表設(shè)計(jì)（可調(diào)時(shí)，有鬧鐘、定時(shí)功能）二、設(shè)計(jì)目的：掌握較復(fù)雜的邏輯設(shè)計(jì)和調(diào)試學(xué)習(xí)用原理圖+VHDL語(yǔ)言設(shè)計(jì)邏輯電路學(xué)習(xí)數(shù)字電路模塊層次設(shè)計(jì)掌握QuartusII軟件及Modelsim軟件的使用方法三、設(shè)計(jì)內(nèi)容：（一）設(shè)計(jì)要求1、具有以二十四小時(shí)計(jì)時(shí)、顯示、整點(diǎn)報(bào)時(shí)、時(shí)間設(shè)置和鬧鐘的功能。2、設(shè)計(jì)精度要求為1S。（二）.系統(tǒng)功能描述1 .系統(tǒng)輸入：系統(tǒng)狀態(tài)及校時(shí)、定時(shí)轉(zhuǎn)換的控制信號(hào)為k、set、ds；時(shí)鐘信號(hào)clk,采用實(shí)驗(yàn)箱的50MHz；系統(tǒng)復(fù)位信號(hào)為reset。輸入信號(hào)均由按鍵產(chǎn)生。系統(tǒng)輸出：8位LED七段數(shù)碼管顯示輸出，蜂鳴器聲音信號(hào)輸出。多功能數(shù)字鐘系

2、統(tǒng)功能的具體描述如下：計(jì)時(shí)：set=1, ds=1工作狀態(tài)下，每日按24h計(jì)時(shí)制計(jì)時(shí)并顯示，蜂鳴器無(wú)聲，逢整點(diǎn)報(bào) 時(shí)。校時(shí)：在set=0,ds=0狀態(tài)下，按下“k鍵”，進(jìn)入“小時(shí)”校準(zhǔn)狀態(tài)，之后按下“k鍵” 則進(jìn)入“分”校準(zhǔn)狀態(tài)，繼續(xù)按下“k鍵”則進(jìn)入“秒校準(zhǔn)”狀態(tài)，之后如此循環(huán)。1）“小時(shí)”校準(zhǔn)狀態(tài)：在“小時(shí)”校準(zhǔn)狀態(tài)下，顯示“小時(shí)”數(shù)碼管以Hz的頻率遞增計(jì)數(shù)。2）“分”校準(zhǔn)狀態(tài)：在“分”校準(zhǔn)狀態(tài)下，顯示“分”的數(shù)碼管以1Hz的頻率遞增計(jì)數(shù)。3）“秒”復(fù)零狀態(tài)：在“秒復(fù)零”狀態(tài)下，顯示“分”的數(shù)碼管以1Hz的頻率遞增計(jì)數(shù)。整點(diǎn)報(bào)時(shí)：蜂鳴器在“59”分鐘的第5059，以1秒為間隔分別發(fā)出100

3、0Hz，500Hz的 聲音。顯示：采用掃描顯示方式驅(qū)動(dòng)8個(gè)LED數(shù)碼管顯示小時(shí)、分、秒。鬧鐘：鬧鐘定時(shí)時(shí)間到，蜂鳴器發(fā)出交替周期為1s的1000Hz、500Hz的聲音，持續(xù)時(shí) 間為一分鐘；鬧鐘定時(shí)設(shè)置:在set=0,ds=1狀態(tài)下，按下*”，進(jìn)入鬧鐘的“時(shí)”設(shè)置狀態(tài)，之后按下“k鍵”進(jìn)入鬧鐘的“分”設(shè)置狀態(tài)，繼續(xù)按下“k鍵”則進(jìn)入“秒”設(shè)置狀態(tài) 之后如 此循環(huán)。1）鬧鐘“小時(shí)”設(shè)置狀態(tài)：在鬧鐘“小時(shí)”設(shè)置狀態(tài)下，顯示“小時(shí)”的數(shù)碼管以1Hz 的頻率遞增計(jì)數(shù)。2）鬧鐘：“分”設(shè)置狀態(tài)：在鬧鐘“分”設(shè)置狀態(tài)下，顯示“分”的數(shù)碼管以1Hz的頻率遞增計(jì)數(shù)。定時(shí)器功能：在set=1,ds=0狀態(tài)下，按下

4、“虹，進(jìn)入定時(shí)器的“時(shí)”設(shè)置狀態(tài)，之后按下“k鍵”進(jìn)入定時(shí)器的“分”設(shè)置狀態(tài)，繼續(xù)按下“k鍵”則進(jìn)入“秒”設(shè)置狀態(tài)，之 后如此循環(huán)。在dsk=1時(shí)，定時(shí)器以1s為單位開始倒時(shí)，當(dāng)dsk=0,停止倒時(shí)，在最后的 十秒時(shí)間，蜂鳴器發(fā)出聲音。rstrstINPUT =_VccPIN_A:CB6)INPUT/ccPIN_fR2INPUTPIN_AAfeB)INPUT=CCPIN_A可arm)INPUTPIN_此INPUT IVCCPIN_YrdSk INPUT/CCPIN_Chfenge_1INPUTPIN_A姓ange_2、INPUT 1PIN_Y14（三）各功能模塊設(shè)計(jì)說(shuō)明及源程序1. 1000H

5、z分頻模塊產(chǎn)生1000Hz頻率2.1Hz模塊產(chǎn)生1Hz頻率計(jì)時(shí)，定時(shí)，鬧鐘，校時(shí)模塊通過(guò)裝換不同的狀態(tài)，分別實(shí)現(xiàn)計(jì)時(shí)，定時(shí)，鬧鐘，校時(shí)功能；源程序如下頂層顯示模塊顯示數(shù)碼管，源代碼如下：（四）.Modelsim綜合仿真圖nun.111111111OOOOD11000000000001000oooo loooomin11ooooIjuuIMessages I IF/disp/rst/disp/dk/disp/k/disp/set/disp/alarm/disp/ds/disp/dsk/di5p,icharige_l/disp,icharnge_2/disp/fm/disp/dig/disp/mi

6、n/disp/y/disp/hour/disp/sec/disp/clkout/disp/fmo/disp/a/disp/dig_r/disp/yj-/disp/rst/disp/dk/disp/set/disp/ds/disp/k/disp/alarm/disp/dsk/disp,icharnge_l/disp,ich.3rige_2nun.111111111OOOOD11000000000001000oooo loooomin11ooooIjuuIMessages I IF/disp/rst/disp/dk/disp/k/disp/set/disp/alarm/disp/ds/disp/d

7、sk/di5p,icharige_l/disp,icharnge_2/disp/fm/disp/dig/disp/min/disp/y/disp/hour/disp/sec/disp/clkout/disp/fmo/disp/a/disp/dig_r/disp/yj-/disp/rst/disp/dk/disp/set/disp/ds/disp/k/disp/alarm/disp/dsk/disp,icharnge_l/disp,ich.3rige_2iiooooriiboooo ooooooIlOOOOOOQU四.總結(jié)及體會(huì)通過(guò)這次電子設(shè)計(jì)大賽課程設(shè)計(jì)，我學(xué)到了很多，對(duì)于原本掌握的不好的數(shù)字

8、 邏輯相關(guān)知識(shí)，在課程設(shè)計(jì)具體實(shí)踐中有了很深刻的認(rèn)識(shí)，在對(duì)于 Quartus+Modelsim仿真的操作上也有很大的提高，增加了操作的熟練程度。通過(guò)實(shí)驗(yàn)調(diào)試，我才真正地認(rèn)識(shí)到了信號(hào)與變量的區(qū)別以及他們的使用方法。 這份報(bào)告是用VHDL代碼寫的，比較長(zhǎng)。相比之下，VERILOG語(yǔ)言顯得簡(jiǎn)潔多了。 不過(guò)可能是對(duì)VERILOG的學(xué)習(xí)還不夠，調(diào)試中出現(xiàn)比較多的問(wèn)題。故最后還是選擇 了 VHDL語(yǔ)言的這份。最后，感謝在思維陷入困境時(shí)給予我指點(diǎn)，讓我獲得靈感的同學(xué)們！附錄：各模塊源程序1.1000Hz 模塊library ieee;use ieee.std_logic_1164.all;use ieee.

9、std_logic_unsigned.all;use ieee.std_logic_arith.all;entity frediv_1000 isport(clk : in std_logic;clkout : out std_logic);end frediv_1000;architecture rt3 of frediv_1000 isbeginprocess(clk)variable count:integer range 0 to 50000;beginif clkevent and clk = 1 thenif count = 49999 thencount := 0;elsecou

10、nt := count + 1;if count = 24999 thenclkout = 1;elseclkout = 0;end if;end if;end if;end process;end rt3;2. 1HZ模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity frediv isport(clk : in std_logic;clkout : out std_logic);end frediv;architectur

11、e rt1 of frediv isbeginprocess(clk)variable count:integer range 0 to 50000000;beginif clkevent and clk = 1 thenif count = 49999999 thencount := 0;elsecount := count + 1;if count = 24999999 thenclkout = 1;elseclkout = 0;end if;end if;end if;end process;end rtl;3.計(jì)時(shí)，定時(shí)，鬧鐘，校時(shí)模塊 library ieee;use ieee.st

12、d_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust isport(rst,clk,k,set,alarm,ds,dskchange_1,change_2fmosec,min,hour);end adjust;architecture rt1 of adjust issignal clk_1Hz,clk_1000Hz,clk_500Hzsignal sec_r,min_r,hour_rsignal sec_ra,min_ra,hour_ra:in std_logic

13、;:in std_logic;:in std_logic;: out std_logic;:out std_logic_vector(7 downto 0):std_logic;:std_logic_vector(7 downto 0);:std_logic_vector(7 downto 0);:std_logic_vector(7 downto 0);signal fm_1:std_logic;signal cht,cmt,cst,cha,cma,csa,chd,cmd,csd :std_logic;signal sel_show:std_logic_vector(1 downto 0);

14、type state_type is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11);signal state:state_type;component fredivport(clk : in std_logic;clkout : out std_logic);end component;component frediv_1000port(clk : in std_logic;clkout : out std_logic);end component;beginU1:frediv port map(clk,clk_1Hz);U3:frediv_1000 port

15、map(clk,clk_1000Hz);500Hzprocess(clk_1000Hz,rst)beginif (rising_edge(clk_1000Hz) thenif(rst = 0) then clk_500Hz =0;elseclk_500Hz =not clk_500Hz;end if;end if;end process;process(clk)beginif sel_show(1 downto 0) = 11 then-shizhongsec = sec_r;min = min_r;hour = hour_r;else if sel_show(1 downto 0) = 01

16、 then-naozhongsec = sec_ra;min = min_ra;hour = hour_ra;else if sel_show(1 downto 0) = 10 then-dingshisec = sec_rd;min = min_rd;hour = hour_rd;else if sel_show(1 downto 0) = 00 then-shizhongsec = sec_r;min = min_r;hour = hour_r;end if;end if;end if;end if;process(clk_1Hz)beginif(rising_edge(clk_1Hz)t

17、henif(rst=0)thenstate=s0;sel_show(1 downto 0)=11;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;else if (set = 1and ds=1)thensel_show(1 downto 0)=11;if(state=s4 or state=s5 or state=s6 or state=s7 or state=s8 or state=s9 or state=s10 or state=s11)thenstate=s0;else if( state=s0)thenif(k=0)then

18、state=s1;else state=s0;end if;else if(state=s1)thencht=T;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s2;else state=s1;end if;else if(state=s2)thencht=, 05 : cmt=, r : cst=，05 ; cha=，O : cma=，O : csa=，O; chd=，05 : cmd=，05 : csd=，05 ; if (k二O) thenstate=s3:else state=s2:end if:els

19、e if ( state=s3 ) thencht=, 05 : cmt=, 05 : cst=，r ; cha=，O : cma=，O : csa=，O; chd=，05 : cmd=，05 : csd=，05 ; if (k二O) thenstate=sO;else state=s3:end if:end if:end if:end if:end if;end if:else if (set二Oand ds=，T)thensel_show(l downto 0)二Ol；cht=, 05 : cmt=, 05 : cst=，05 ;cha=，O : cma=，O : csa=，O;chd=，

20、05 : cmd=，05 : csd=，05 ;if(state=sO or state二si or state=s2 or state=s3 or state=s8 or state=s9 or state=slO or state=sll)thenstate=s4;else if( state=s4)thenif(k=0)thenstate=s5;elsestate=s4;end if;else if( state=s5)thencht=0;cmt=0;cst=0;cha=T;cma=0;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s6;elsesta

21、te=s5;end if;else if(state=s6 )thencht=0;cmt=0;cst=0;cha=0;cma=T;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s7;elsestate=s6;end if;else if(state=s7)thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=T;chd=0;cmd=0;csd=0;if(k=0)thenstate=s4;elsestate=s7;end if;end if;end if;end if;end if;end if;else if(set=1and ds=0

22、)thensel_show(1 downto 0)=10;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(state=s0 or state=s1 or state=s2 or state=s3 or state=s4 or state=s5 or state=s6 or state=s7)thenstate=s8;else if( state=s8)thenif(k=0)thenstate=s9;elsestate=s8;end if;else if( state=s9)thencht=0;cmt=0;cst=0;cha=0;

23、cma=0;csa=0;chd=T;cmd=0;csd=0;if(k=0)thenstate=s10;elsestate=s9;end if;else if(state=s10 )thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=T;csd=0;if(k=0)thenstate=s11;elsestate=s10;end if;else if(state=s11)thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=T;if(k=0)thenstate=s8;elsestate=s11;

24、end if;end if;end if;end if; end if;end if;elsesel_show(1 downto 0) = 00;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;end if;end if;end if;end if;end if;end process;process(clk_1Hz)beginif clk_1Hzevent and clk_1Hz = 1 thenif rst = 0 thensec_r = 00000000;min_r = 00000000;hour_r = 9 then min_

25、r(3 downto 0) = 5 then min_r(7 downto 4) = 0000;else min_r(7 downto 4) = min_r(7 downto 4) + 1;end if;else min_r(3 downto 0) = min_r(3 downto 0) + 1;end if;else if (change_2 = 0 and cmt = 1) thenif min_r(3 downto 0) = 0 then min_r(3 downto 0) = 1001;if min_r(7 downto 4) = 0 then min_r(7 downto 4) =

26、0101;elsemin_r(7 downto 4) = min_r(7 downto 4) - 1;end if;elsemin_r(3 downto 0) = min_r(3 downto 0) - 1;end if;else if (change_1 = 0 and cht = 1) thenif (hour_r(7 downto 4) = 2 and hour_r(3 downto 0) = 3 ) then hour_r = 9)thenhour_r(3 downto 0) = 0000;hour_r(7 downto 4) = hour_r(7 downto 4) + 1;else

27、hour_r(3 downto 0) = hour_r(3 downto 0) + 1;end if;end if;else if (change_2 = 0 and cht = 1) thenif (hour_r(7 downto 4) = 0 and hour_r(3 downto 0) = 0 ) then hour_r = 00100011;elseif(hour_r(3 downto 0) = 0 and hour_r(7 downto 4) 2)then hour_r(3 downto 0) = 1001;hour_r(7 downto 4) = hour_r(7 downto 4

28、) - 1;elsehour_r(3 downto 0) = 9 thensec_r(3 downto 0) = 5 thensec_r(7 downto 4) = 0000;elsesec_r(7 downto 4) = sec_r(7 downto 4) + 1;end if;elsesec_r(3 downto 0) = sec_r(3 downto 0) + 1;end if;else if (change_2 = 0 and cst = 1) thenif sec_r(3 downto 0) = 0 thensec_r(3 downto 0) = 1001;if sec_r(7 do

29、wnto 4) = 0 thensec_r(7 downto 4) = 0101;elsesec_r(7 downto 4) = sec_r(7 downto 4) - 1;end if;elsesec_r(3 downto 0) = 9 thensec_r(3 downto 0) = 5 thensec_r(7 downto 4) = 9 thenmin_r(3 downto 0) = 5 thenmin_r(7 downto 4) = 0000;if hour_r(7 downto 4) = 2 thenif hour_r(3 downto 0) = 3 thenhour_r = 0000

30、0000;elsehour_r(3 downto 0) = 9)thenhour_r(3 downto 0) = 0000;hour_r(7 downto 4) = hour_r(7 downto 4) + 1; elsehour_r(3 downto 0) = hour_r(3 downto 0) + 1; end if;end if;elsemin_r(7 downto 4) = min_r(7 downto 4) + 1;end if;elsemin_r(3 downto 0) = min_r(3 downto 0) + 1;end if;elsesec_r(7 downto 4) =

31、sec_r(7 downto 4) + 1;end if;elsesec_r(3 downto 0) = sec_r(3 downto 0) + 1;end if;end if;endif;endif;endif;endif;endif;endif;endif;end process;process(clk_1Hz)beginif clk_1Hzevent and clk_1Hz = 1 thenif rst = 0 thensec_ra = 00000000;min_ra = 00000000;hour_ra= 9 then min_ra(3 downto 0) = 5 then min_r

32、a(7 downto 4) = 0000; elsemin_ra(7 downto 4) = min_ra(7 downto 4) + 1; end if;elsemin_ra(3 downto 0) = min_ra(3 downto 0) + 1;end if;else if (change_2 = 0 and cma = 1) thenif min_ra(3 downto 0) = 0 then min_ra(3 downto 0) = 1001;if min_ra(7 downto 4) = 0 thenmin_ra(7 downto 4) = 0101;elsemin_ra(7 do

33、wnto 4) = min_ra(7 downto 4) - 1;end if;elsemin_ra(3 downto 0) = min_ra(3 downto 0) - 1;end if;else if (change_1 = 0 and cha = 1) thenif (hour_ra(7 downto 4) = 2 and hour_ra(3 downto 0) = 3 ) then hour_ra = 9)thenhour_ra(3 downto 0) = 0000;hour_ra(7 downto 4) = hour_ra(7 downto 4) + 1;elsehour_ra(3

34、downto 0) = hour_ra(3 downto 0) + 1;end if;end if;else if (change_2 = 0 and cha = 1) thenif (hour_ra(7 downto 4) = 0 and hour_ra(3 downto 0) = 0 ) then hour_ra = 00100011;elseif(hour_ra(3 downto 0) = 0 and hour_ra(7 downto 4) 2)then hour_ra(3 downto 0) = 1001;hour_ra(7 downto 4) = hour_ra(7 downto 4

35、) - 1; elsehour_ra(3 downto 0) = 9 thensec_ra(3 downto 0) = 5 thensec_ra(7 downto 4) = 0000;elsesec_ra(7 downto 4) = sec_ra(7 downto 4) + 1;end if;elsesec_ra(3 downto 0) = sec_ra(3 downto 0) + 1;end if;else if (change_2 = 0 and csa = 1) thenif sec_ra(3 downto 0) = 0 thensec_ra(3 downto 0) = 1001;if

36、sec_ra(7 downto 4) = 0 thensec_ra(7 downto 4) = 0101;elsesec_ra(7 downto 4) = sec_ra(7 downto 4) - 1;end if;elsesec_ra(3 downto 0) = sec_ra(3 downto 0) - 1;end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;process(clk_1Hz)beginif clk_1Hzevent and clk_1Hz = 1 thenif rst = 0 t

37、hensec_rd = 00000000;min_rd = 00000000;hour_rd = 9 then min_rd(3 downto 0) = 5 thenmin_rd(7 downto 4) = 0000;elsemin_rd(7 downto 4) = min_rd(7 downto 4) + 1;end if;elsemin_rd(3 downto 0) = min_rd(3 downto 0) + 1;end if;else if (change_2 = 0 and cmd = 1) thenif min_rd(3 downto 0) = 0 then min_rd(3 do

38、wnto 0) = 1001;if min_rd(7 downto 4) = 0 thenmin_rd(7 downto 4) = 0101;elsemin_rd(7 downto 4) = min_rd(7 downto 4) - 1;end if;elsemin_rd(3 downto 0) = min_rd(3 downto 0) - 1;end if;else if (change_1 = 0 and chd = 1) thenif (hour_rd(7 downto 4) = 2 and hour_rd(3 downto 0) = 3 ) then hour_rd = 9)thenh

39、our_rd(3 downto 0) = 0000;hour_rd(7 downto 4) = hour_rd(7 downto 4) + 1;elsehour_rd(3 downto 0) = hour_rd(3 downto 0) + 1;end if;end if;else if (change_2 = 0 and chd = 1) thenif (hour_rd(7 downto 4) = 0 and hour_rd(3 downto 0) = 0 ) then hour_rd = 00100011;elseif(hour_rd(3 downto 0) = 0 and hour_rd(

40、7 downto 4) 2)then hour_rd(3 downto 0) = 1001;hour_rd(7 downto 4) = hour_rd(7 downto 4) - 1;elsehour_rd(3 downto 0) = 9 thensec_rd(3 downto 0) = 5 thensec_rd(7 downto 4) = 0000;elsesec_rd(7 downto 4) = sec_rd(7 downto 4) + 1;end if;elsesec_rd(3 downto 0) = sec_rd(3 downto 0) + 1;end if;else if (chan

41、ge_2 = 0 and csd = 1) thenif sec_rd(3 downto 0) = 0 thensec_rd(3 downto 0) = 1001;if sec_rd(7 downto 4) = 0 thensec_rd(7 downto 4) = 0101;elsesec_rd(7 downto 4) = sec_rd(7 downto 4) - 1;end if;elsesec_rd(3 downto 0) = sec_rd(3 downto 0) - 1;end if;else if dsk=0 thenif sec_rd(3 downto 0) = 0 thensec_

42、rd(3 downto 0) = 1001;if sec_rd(7 downto 4) = 0 thensec_rd(7 downto 4) = 0101;if min_rd(3 downto 0) = 0 then min_rd(3 downto 0) = 1001;if min_rd(7 downto 4) = 0 thenmin_rd(7 downto 4) = 0101;if hour_rd(7 downto 4) = 0 then if hour_rd(3 downto 0) = 0 then hour_rd = 00100011; elsehour_rd(3 downto 0) =

43、 hour_rd(3 downto 0) - 1;end if;elseif(hour_rd(3 downto 0) = 0)thenhour_rd(3 downto 0) = 1001;hour_rd(7 downto 4) = hour_rd(7 downto 4) - 1; elsehour_rd(3 downto 0) = hour_rd(3 downto 0) - 1; end if;end if;elsemin_rd(7 downto 4) = min_rd(7 downto 4) - 1;end if;elsemin_rd(3 downto 0) = min_rd(3 downt

44、o 0) - 1;end if;elsesec_rd(7 downto 4) = sec_rd(7 downto 4) - 1;end if;elsesec_rd(3 downto 0) = sec_rd(3 downto 0) - 1;end if;end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;fmo=fm_1;process(clk)beginif clkevent and clk = 1 thenif(min_r=min_ra and hour_r=hour_ra and sec_r(

45、0)=0 and alarm=0)then fm_1=clk_1000Hz;else if(min_r=min_ra and hour_r=hour_ra and sec_r(0) =1 and alarm=0 )then fm_1=clk_500Hz;else if ( min_r(7 downto 4 )= 5 and min_r(3 downto 0)= 9 and sec_r(7 downto 4) =5 and sec_r(0)=1 ) thenfm_1=clk_1000Hz;else if ( min_r(7 downto 4 )= 5 and min_r(3 downto 0)=

46、 9 and sec_r(7 downto 4) =5 and sec_r(0) = 0) thenfm_1=clk_500Hz;else if (dsk=0 and min_rd(7 downto 0)=00000000 and hour_r(7 downto 0)=00000000 and sec_rd(7 downto 4)=0 and sec_rd( 0)=1) then fm_1=clk_1000Hz;else if (dsk=0 and min_rd(7 downto 0)=00000000 and hour_r(7 downto 0)=00000000 and sec_rd(7 downto 4)=0 and sec_rd(0)=0) then fm_1=clk_500Hz;elsefm_